einen a . See a eee See Ee ee ee ecuisel see Se So eeuny come RE gio eet ae AT & T MELEC (I C) . 25 D M OOSOO2b 0003950 b ATtst T 75-29 Advance Data Sheet (i) T7290 DS1/T1/CEPT Line Interface Features Fully integrated ISDN DS1/T1/CEPT line interface =" Two on-chip phase-lock loops (PLLs) to facllitate = Compatibility with CB119, Pub 43801, Pub 43802, Pub -!0K synchronization without external crystals 62411, TR-TSY-000170, TR-TSY-000009, CCITT G.703, Three clocking modes to accommodate any system G.735, G.823, and 1.431 specifications clocking requirements Dual-rail system interface Multiple tink status and alarm features On-chip transmit equalization Microprocessor interface option for control features On-chip Jitter attenuator # AIS (Blue Alarm) transmission = Monolithic clock recovery with acquisition aide Loopback modes for fault isolation a sow power CMOS In a 28-pin, plastic DIP or SOJ = Minimal external circuitry required package High Jitter accommodation (>0.4 U.1.) Description The T7290 ISDN DS1/T1/CEPT Line Interface is a single-chip, CMOS line transceiver capable of operation at the domestic DS1/T1 cartier rate (1.544 Mbits/s) or the international CEPT1 rate (2.048 Mbits/s). The T7290 device combines features found In existing IIne-interface devices and adds other deslrable features. The on-chip, low-Impedance output drivers provide shaped waveforms to the transformer, guaranteeing template conformance. The T7290 device Interfaces to the digital cross-connect (DSX) at lengths up to 655 feet during DS1 operation and interfaces to line impedances of 75 0 or 120 2 during CEPT operation. 17290 line interface is also capable of transmitting waveforms compatible with T1 lines. The T7290 line interface provides phase-locked loop clock recovery and data retiming on received data. Also, on-chip, selectable, jitter attenuation is available. The jitter attenuator can be placed in the receive or transmit data path. No external crystals are required with the T7290 device. Digital control circuitry allows for multiple loopbacks, testing, and alarm status monitoring. A microprocessor Interface option allows for either control via a microprocessor or direct pin-selectable control (hardware mode). The T7290 device is manufactured by using a low-power CMOS technology. The block diagram is shown in Figure 1.pees AT & T MELEC (I C) 17290 DS1/T1/CEPT Line Interface Ma 00S500eb ese D 7 ke eRe Alte 00395) 8 mi T-25-11-29 a etme dt 090 TRANSMIT LINE 3 t ogo TRANSMIT DATA RECEIVE -3 LINE TRANSMIT CLOCK * RECEIVED DATA DATA RATE & LINE LENGTH INSERT SELECT BLUE SIGNAL - OUTPUT DRIVERS }* anette SIGNAL AND INSERTION MONITOR [7] EQUALIZATION _ c~ r 7 ! JITTER | LOOPBACKS Lp2| CONTROL LPi | ONTRO ATTENUATOR | iip3 Le | PLL2 Receive [| ., chock = Le EXTRACTION & N NUT r] RETIMING , PLU CLK uP INTERFACE qv q LOSS OF ERROR SIGNAL INDICATIONS Figure 1. Block Diagram RECEIVED CLOCKeT eee pa at ee SER re ee AT & T MELEC (I C) set ae. i a ate eS. ese D User Information Pin Descriptions Ecic)1 ~~ o28heEce TRIC) 2 27 Ec3 Vooa (| 3 261] GNDp GNDAC] 4 25 [7] R2 RIS 241] Vopp TIO6 23/7 T2 MODE2(}7 22 [] RNDATA MODE1(] 8 17290 21] RPDATA LoopBLj9 20 CI RCLK Loopa C] 10 19 [J TNDATA TessO 11 18 F TPDATA Los (12 17 LD TCLK ESA[] 13 16 [.] EXCLK TSC] 14 15(cs Figure 2. Pin Function Diagram Table 1. Pin Descriptions Pin Symbol Type Name/Function 1,27,28 | ECiIEC3 i Equalizer/Rate Control 13. Three control leads for selecting transmit equalizers. 2 TRI | 3-State (Active-Low). This pin is set low to 3-state all digital output buffers. This control should be used during in-circuit testing. 3 VDDA 5 V+ 10% Analog Supply. 4 GNDA I Analog Ground. 5 R1 I Receive Bipolar Ring. Negative bipolar receive data. 6 T1 | Receive Bipolar Tip. Positive bipolar receive data. 7,8 MODE2, MODE1 I Mode Select 2 and 1. Two control leads for selecting clock and data paths through the jitter attenuator. 9, 10 LOOPB, LOOPA | Loopback Control B and A. Two control leads for selecting clock and data loopback paths. , 11 TBS | Transmit Blue Signal. This pin is set high to transmit the blue signal. A remote loopback has priority over the transmit blue signal If the remote loopback and transmit blue signal are operated simultaneously. 12 LOS Oo Loss of Signal. This pin is set high upon the loss of the data signal at the receiver inputs. LOS can be tied directly to TBS to initiate a transmit blue signal upon loss of signal. mm 00500eb8 0003952 T M8 T-95-11-24 T7290 DS1/T1/CEPT Line Interfaceee ee TE ET pacientes = : merger a genes "an tle AT & T MELEC (I C) eSE D m@ 0050026 0003953 1 ml T-75-|\-29 T7290 DS1/T1/CEPT Line Interface sete Table 1. Pin Descriptions (Continued) oe - Pin | Symbol | Type Name/Function 18 | ESA oO Jitter Attenuator Undertlow/Overflow Alarm. This pin is set high if the phase jitter of the incoming signal exceeds the IImits of the jitter attenuator. 14 | TSC 0 Transmitter Short-Circuit. This pin is set high if either T2 or R2 is shorted to the power supply or ground or if T2 and R2 are shorted together. 15 | CS I Chip Select for Microprocessor Interface (Active-Low). CS loads data Into the device during its falling edge and latches the data during its rising edge. CS Is set low for hardware mode. 16 | EXCLK | External Clock. DS1/T1 clock signal (1.544 MHz + 130 ppm) or CEPT clock signal (2.048 MHz + 50 ppm) for transmit blue signal, loss of signal clock insertion, jitter attenuator calibration, and PLL1 acquisition aide. This clock should be void of jitter. , 17 | TCLK I Transmit Clock. DS1/T1 clock signal (1.544 MHz + 130 ppm) or CEPT Clock signal (2.048 MHz + 50 ppm). 18 | TPDATA { Transmit Positive Data. DS1/T1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) positive bipolar data. 19 | TNDATA 1 Transmit Negative Data. DS1/T1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) negative bipolar data. 20 | RCLK O Receive Clock. Receive clock signal for the terminal equipment. 21 | RPDATA O Receive Positive Data. DS1/T1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) positive data. 22 | RNDATA oO Receive Negative Data. DS1/T1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) negative data. 23 | T2 oO Transmit Bipolar Tip. Positive bipolar transmit data. 24 | Voopp V+ 10% Digital Supply. 25 | R2 Oo Transmit Bipolar Ring. Negative bipolar transmit data. 26 | GNDo _ Digital Ground. Architecture Recelve Path Data Interface. The receive line-interface transmission format of the T7290 device is alternate mark inversion (AMI). The recelve digital output format is dual-rail, non-return to zero (NRZ). (See Receiver Specifications under the Electrical Characteristics section.) Clock Recovery and Data Retiming. The bipolar input signals from T1 and R1 are peak-detected and sliced by the receiver front-end. Timing recovery Is performed by a phase-locked loop (PLL1), An acqulsition aide circuit for PLL1 trains an Internal oscillator to either the DS1/T1 or CEPT1 frequency by using EXCLK as a reference. EC1, EC2, and EC3 rate control inputs must be set appropriately for DS1 or CEPT operation. Jitter. PLL1 is designed to accommodate large amounts of input jitter with high power-supply rejection for operation In nolsy environments. PLL1 has a minimum input jitter tolerance exceeding all requirements shown in Figure 7. The recelver transfers Incoming jitter to RCLK with no more than 2 dB of gain at any frequency. Data Patterns. Any data pattern with a minimum long-term 1s density of 12.5% with 15 or less consecutive 0s is allowed. ,AT & T MELEC (I C) eSE D M@ 0050026 0003954 3 mm T-75-1-29 T7290 DS1/T1/CEPT Line Interface Loss-of-Signal. Both digital and analog loss-of-signal detection Is used in the T7290 device. The digital signal detector is described later under the Digital Logic section, The analog signal detector uses the output of the receiver peak detector to determine if a signal is present at T1 and R1. If the input amplitude drops below approximately 0.48 V for DS1/T1 operation or 0.28 V for CEPT operation, the analog detector output becomes active. Hysteresis (250 mV) Is provided in the analog detector to eliminate LOS chattering. !n normal operation, either the analog or the digital detector sets LOS high; however, in full local loopback (LP1), only the digital signal detector Is used to monitor the looped signal. Transmit Path Output Pulse Shape. A summary of the transmitter specifications are given under the Electrical Characteristics section. The T1 output pulse shape is shown In Figure 3. Pulse overshoot varlations are allowed according to the limits shown in Figure 4. The DS1 pulse shape template is specified at the DSX and is Illustrated in Figure 5. CEPT transmit waveforms at the device output conform to the template shown in Figure 6. e W = 324 ns + 45 ns leg- 200 ns MAX -_______ 72 ____-____ gm e_o T1 100% A=3V+403V 50% 50% BASE LINE TO PEAK OVERSHOOT 50% 2.7<A+0.20 <33V 100% 294 < W+15ns < 354 648 ns + 15 ns trtf < 100 ns Figure 3. T1 Output Pulse Characteristics 7 mee ar te ee . or =n coe BE ee ST ee edi deca, ww SPD oe cee AT & T MELEC (I C) 25 D M COSOO@b 0003955 5 mi T-75-(1-29 T7290 DS1/T1/CEPT Line Interface Ti (ns} uw =1.0 WY, 5 Y z ? / g p ; Uy z Z b Uy; 2 YP Yo -05 | ! 0 250 500 750 1000 4250 NANOSECONDS DSX-1 Pulse Template Corner Points Maximum Curve Minimum Curve Normalized Normalized ns Voltage ns Voltage 0 0.05 0 0.05 250 0.05 350 0.05 325 0.80 350 0.50 325 1.15 400 0.95 150 425 1.15 500 0.95 500 1.05 600 0.90 100 @- 675 1.05 650 0.50 725 ~0.07 650 0.45 50 875 0.05 800 0.45 1250 0.05 925 0.20 50 100 150 200 250 300 350 400 450 500 1100 0.05 1250 0.05 T2 (ns) @ INDICATES EXAMPLE WHICH CONFORMS WITH LIMITS Note; Successive corner polnts are joined by straight lines. Figure 4. T1 Pulse Overshoot Limits Figure 5. DSX-1 Isolated Pulse TemplateAT & T MELEC (I C) eo, OSE D m@ 00500eb 0003956 7 mm T7290 DS1/T1/CEPT Line Interface 269 ns (244 + 25) le 194 n8 20% (244 ~ 80) 10% 4 on f Z V = 100% i SS ee LL Y NOMINAL PULSE ' 4 20% 4 Y Al 50% | | 10% 10% 17 | oa 0% ee ee + 10% t NAG, if 20% 219 ns (244 = 25) 244 n8 488 ns Figure 6. CCITT G.703 Pulse Template Output Pulse Generation. The transmitter accepts a clock with positive and negative data (dual-rail NRZ format) and converts the signal to a balanced bipolar data signal (AMI format), Positive 1s are produced by a positive pulse on T2, and negative 1s are produced by a positive pulse on R2. Binary Os are converted to null pulses. All pulse shapes are controlled on-chip according to equalizer contro! Inputs as defined In Table 2. Transmitter (244 + 244) specifications are listed under the Electrical Characteristics section. Table 2. Equalizer/Rate Control Maximum! Service | Equalization Cable Loss | EC1 | EC2 | EC3 TH 2at 0 0 0 DS1 0 131 0.6 0 0 1 DS1 131 262' 1.2 0 1 0 DS1 262 393 1.8 0 1 1 DS1 393' 524 2.4 1 0 0 DS1 524 656 3.0 1 0 1 CEPT 7659 _ 1 1 0 CEPT 120 2 _ 1 1 1 * Distance to DSX in feet for 22-Ga. PIC (ABAM) Cable [DS1 only]. Use maximum loss figures for other cable types, t gB at 772 kHz. According to FCC Part 68, Subpart D, Option A for 0 dB line build-out. ce tan tA TRE ene Senecio a8 T-75-11-29 _ eee cue eae es pe cenmesetines et ess sath ne eens as ede eae! siete : att Okie ac AT & T MELEC (I ) eSE D m@ 0050026 0003957 1 mi T~15-1)-24 T7290 DS1/T1/CEPT Line Interface se aE Jitter Attenuation. Jitter transfer functions describe the amount of jitter that is delivered from the input to the output of specified equipment. The jitter attenuator circuit can be placed in the receive data path or the transmit data path, or it can be omitted altogether. Placement of this circult is controlled as described in Table 3. When attenuation is selected, the T7290 device exhibits a jitter transfer function which has no peaking and a single 14.5 Hz pole frequency. Figure 8 displays a typical jitter transfer function. The amount of generated output jitter when no input jitter is present is measured by using the scheme shown in Figure 9, The Jitter filters depicted represent the PUB 62411 specification for a 1.544 MHz data rate. The jitter produced at the labeled points does not exceed the following peak-to-peak levels: 0.05 U.I. at point 1, 0.025 U.I. at point 2, 0.025 U.I. at point 3, and 0.02 U.I. at point 4. A similar test can be performed for CCITT 1.431 qualification at the 2.048 MHz data rate. The two jitter filters of Interest include 20 Hz 100 kHz (0.125 U.I.) and 700 Hz 100 kHz (0.02 U.I.). The jitter tolerance of the attenuator meets the requirements of the TR-TSY-000009, PUB43802, and CCITT G.823 (see Figure 7), The attenuator also ensures that jitter accommodation Is a minimum of 22 U.!. peak-to-peak (1 U.I. = 1 bit = 360) during attenuation. The Jitter attenuator function Is the same for both transmit and receive paths. Table 3. Connectivity of Jitter Attenuator Connectivity of Jitter Attenuator | MODE1 | MODE2 Bypass 0 0 Transmit Path 0 1 Recelve Path 1 0 Test Mode! 1 1 * Jitter attenuator is powered down during this mode (see Operating Conditions under the Etectrical Characteristics Section). t Not to be used for normal operation.er ee ee ct ee aes AT & T MELEC (I C) ese D ae BE: @@ 005002e6 0003956 0 me T511-29 T7290 DS1/T1/CEPT Line Interface 500.0 = TR-TSY-000170, 2 PN SS PUB 43801 a C - Sa PUB 62411 = 5 50.0 /- PUB 62411 Gg < = TR-TSY-000009, XY (LOOP TIMED) c PUB 43802 \ c 5.0 |- a, NNR E YN x Pp A e = \ 5 0.5 F CCITT G.823 rT a OE | | l 1 10 100 1000 10,000 100,000 JITTER FREQUENCY (Hz) Data Points (Hz, U.I.) TR-TSY-000170, | TR-TSY-000009, PUB 62411 CCITT G.823 PUB 43801 PUB 43802 PUB 62411 | Loop Timed 1, 2.9 10, 300 10, 5 1, 138 1, 138 20, 1.5 10k, 0.3 500, 5 48, 138 85, 138 2.4k, 1.5 50k, 0.3 8k, 0.1 10k, 0.2 10k, 0.4 18k, 0.2 40k, 0.1 100k, 0.2 100k, 0.4 100k, 0.2 _ - Figure 7. Jitter Tolerance Requirementsoe meee ce ene te et cc sernvane Site ah RE A T & T MELEC (I C) T7290 DS1/T1/CEPT Line Interface sm 25E D MM OOS0026 0003959 2 mT-75-/]-29 ok 40 dB/DECADE ae CCITT G.735, 3 20 dB/ CCITT 1.431 z ~20b DECADE 9 - = 30 TYPICAL TR-TSY-000009, it PERFORMANCE E 40 |-20 dB/DECADE ft f -50F 20 dB/DECADE E ~60}- -70 | 1 [hi | 1 10 40 100 350 1k 25k 15k 400 10 k JITTER FREQUENCY (Hz) Data Points (Hz, dB) TR-TSY-000009, | CCITT G.735, PUB 43802 CCITT 1.431 10, 0.5 10, 0.5 350, 0.5 40, 0.5 2.5k, 33.6 400, 19.5 15k, 49,.2 15k, 19.5 Figure 8. Jitter Transfer Function of the Jitter Attenuator 10ee AT & T MELEC me ee BR ve oh ee (Ic) soins. eet ee 256 D M OOSOO2 OO039L0 4 mI -95-})-24 T7290 DS1/T1/CEPT Line Interface FILTERS (SLOPES MUST BE 20 dB PER DECADE) 4 TO EACH POINT e O a------- 7 10 Hz 8 kHz PEAK DETECTOR 3 a }+C) MEASURED >} eR 8 kHz 40 kHz SIGNAL TRUE RMS VOLTMETER ] / | ) 2 @---~ | r -O TO EACH POINT 10 Hz 40 kHz 1 SPECTRUM O +7771 ANALYZER Figure 9. Measurement of Generated Jitter Digital Logic Alarms. There are three alarms: digital loss of signal (LOS), jitter attenuator underflow/overflow alarm (ESA), and transmitter short circuit (TSC). A digital loss of signal (LOS = 1) is indicated If 128 or more consecutive Os occur in the receive data stream during DS1/T1 operation. During CEPT operation, an LOS Is indicated when 32 or more consecutive 0s occur In the receive data stream. LOS Is then deactivated when four or more 1s occur in 32 bits of data (T1, DS1, and CEPT). This hysteresis effect eliminates LOS chattering. Upon LOS detection, the external clock (EXCLK) is automatically inserted for RCLK so that other system devices slaved to the line clock continue to operate. A jitter attenuator underflow/overflow (ESA = 1) Is indicated if the phase jitter exceeds the limits of the jitter attenuator. This signal is asserted until error-free operation resumes. A transmitter monitor Is provided to detect nonfunctioning links and protect the device from damage. If one of the transmitter's line drivers (T2 or R2) is shorted to the power supply or ground or if T2 and R2 are shorted together, a transmitter short-circult (TSC = 1) Is indicated, during which internal circuitry protects the device from damage. After a minimum of 32 clock cycles, the transmitter Is powered up In Its normal operating mode. If the error Is still present, TSC remains set (eliminating TSC chattering), and the transmitter is again buffered for a minimum of 32 clock cycles. This process is continuously repeated until the error has disappeared, thus deactivating TSC. 11AT & T MELEC (I Cc) T7290 DS1/T1/CEPT Line Interface rae SRE AIS (Blue Signal) Generator. An all-1s insertion is provided by the transmitter synchronous with EXCLK. When transmit blue signal is set (TBS=1), a continuous stream of bipolar 1s is sent onto the line. The TPDATA and TNDATA inputs are ignored during this mode. If the LOS output is externally connected to the TBS input, an LOS error initiates a transmit blue signal as long as LOS=1. Also, TBS input is ignored when a remote loopback is selected. Microprocessor Interface. A chip select input (CS) configures the device in either hardware mode or microprocessor mode. The chip-select function applies to the following inputs: MODE1, MODE2, EC1, EC2, EC3, TBS, LOOPA, and LOOPB. Hardware mode is used when no microprocessor is available in the system, and these inputs need not be synchronous with any specific system clock. Any change on these input pins is directly fed into the device. To maintain hardware mode, set CS=0. In microprocessor mode, new digital control inputs are loaded Into the T7290 device during the falling edge of CS and are latched during the rising edge of CS. A timing diagram of this function is shown in Figure 15. In-Circuit Testing. The device has the ability to allow for in-circult testing by activating 3-state mode (TRI = 0). During this mode, all digital output buffers (RCLK, RPDATA, RNDATA, LOS, ESA, and TSC) are 3-stated. Loopbacks. The T7290 device has three independent loopback paths, which are activated according to Table 4. A full local loopback (LP1) connects the transmitter output data to the input of the receiver front-end, producing a loopback which exercises the maximum amount of device circultry. The external input from T1 and R1 Is ignored and LOS Is Indicated if no signal Is looped from the transmitter. Valid transmit output data continues to be sent to the network. A remote loopback (LP2) loops the recovered clock and retimed data from the receive bipolar inputs into the transmitter and back onto the line. The receive front-end, receive PLL1, jitter attenuator (if engaged), and transmit driver circultry are all exercised. The external transmit clock and data and TBS input are ignored. Valid receive output data continues to be sent to RPDATA and RNDATA. This loop can be used to Isolate failures between systems. A digital local loopback (LP3) directly loops the transmit clock and data to the receive clock and data output pins. The blue signal can be transmitted when in this loopback. Table 4, Loopback Control Operation Symbol | LOOPA | LOOPB Normal 0 0 Digital Local Loopback LP3 0 1 Remote Loopback LP2 1 0 Full Local Loopback LP1 1 1 12 25 D M@ 0050026 0003961 0 mi J~75-11-29 eeco ee wee wee - a ee mee EE ele et 7 aen ener ees EE se ee tee AT & T MELEC (I C) eSE D Me 0050026 00039b2 2 MIT~95-1]-24 T7290 DS1/T1/CEPT Line Interface Applications oO - The following figures are applications for the T7290 device. RECEIVE DATA e TH RPDATA |- = 500 0 RECEIVE RNDATA -+ 200 9 $ INPUT 3 500 9 FICLK RI 1:2 Vopp +5 V T7290 = VODA < TRANSMIT DATA GNDo | GNDA 5_710 T2 = TRANSMIT TPDATA je- OUTPUT TNDATA kee 5 R2 TCLK ka 1.14:1 Note: Recommended transformers are the AT&T 2741 and 2745 Series, Figure 10. DS1 Application for Twisted-Pair Interface 13~ eek a ine ee AT & T MELEC (I C) eSE D MM@ 0050026 0003943 4 = T7290 DS1/T1/CEPT Line Interface ice RE, Dae! IS-H-29 RECEIVE DATA 11 RPDATA| > LBO/ RECEIVE RNDATA |} EQUAL. INPUT IZER RCLK |} R1 1:2 Vpop +5 V q VDDA T7290 | 1 pF < TRANSMIT DATA GNDo|~> | 21.50 GNDa 1 55- 9 9 WN, T2 _ 100 2 3 LOAD TRANSMIT TPDATA }# 21.59 TNDATA /*@_ 1.36:1 R2 TCLK - WAVEFORM MEETS FIGURE 3 TEMPLATE AT THIS POINT. Note: Recommended transformers are the AT&T 2741 and 2745 Series. Figure 11. T1 Application Diagram 14 s._ 0050026 0003964 b MIT-75-1/-29 EG ee vat. AT & T MELEC (I C) 2SE D : T7290 DS1/T1/CEPT Line Interface RECEIVE DATA 11 RPDATA > $ = 866 0 RECEIVE RNDATA > 2002 3 INPUT ] 3 866 0 RCLK - 1:2 At Vppp +5 V q VDDA T7290 : D 1 LF NDpb < TRANSMIT DATA } 26.10 GNDa $ 0.0 T2 = 3 TRANSMIT TPDATA 120 9 $ LOAD OUTPUT TNDATA 26.1 0 - L_ RQ TCLK # 1.36:1 Note: Recommended transformers are the AT&T 2741 and 2745 Series. Figure 12. CEPT Application for Twisted-Pair Interface 15AT & T MELEC (I Cc) aes ea eee note tse me sete ae | OOS00eb OOO35bS & mT 95-11-29 T7290 DS1/T1/CEPT Line Intertace ne AP pen RECEIVE DATA _O- + 200 2 3 0 0 76 2 1:2 <@ TRANSMIT DATA 15.4 0 15.4 0 T1 RECEIVE INPUT R1 T7290 T2 TRANSMIT OUTPUT R2 RPDATA |} RNDATA |>- RCLK - Vppp +5 V Vopa 1 GNDb Ty GNDA L TPDATA *_ .. TNDATA -#- TCLK ~ Note: Recommended transformers are the AT&T 2741 and 2745 Series. 16 Figure 13. CEPT Application for Coaxial Interfaceeet So. eee eee ee Mm OOSO02) o003%bb T Mi T~75-I1-229 wee et Pee AT & T MELEC (I C) 25E PD T7290 DS1/T1/CEPT Line Interface Characteristics Electrical Characteristics Operating Conditions -40 C < Ta < +85 C, except as noted. Parameter Symbol | Min | Typ | Max | Unit Supply Voltage Vpp 45 | 50 | 5.5 Vv Power Dissipation PD (without jitter attenuator) T1 125 138 mw psit | 132 | 145 | mw CEPT (75 0) | 126 | 139 | mw CEPT (120 9) | 120 | 182 | mw (with jitter attenuator) T1 | 165 | 182 | mw psit | 172 | 189 | mw CEPT (75 9) | 174 | 191 | mw CEPT (120 9) | 168 | 185 | mw * Conditions with 50% is on the transmit side, Vop = 5 V, Ta = 25C, t Equalizer settings: EC1 = 0, EC2 = 1, EC3 = 1. Maximum Ratings dc Supply Voltage (Vpbp) Range Power Dissipation (PD) .....ssssscsssssscecsssssssseecscsassssecosssssssessussvessvsssssssssscsssensesueseesueesussecssssssssessascsusasssssassssssesesecersenees Perr errr rir rr rr rir rrrrrr reir reer rererrrer rT r yr rer ret eee erry Maximum ratings are the Ilmiting conditions that can be applied under all variations of circuit and environmental conditions without the occurrence of permanent damage. External leads can be soldered safely at temperatures up to 300 C. tee errr ere rire r rr ri rier rrr rer reer rr rete Trey erry ee er Terre ry 17oer :* foe ee emer oT ae AT & T MELEC (I C) T7290 DS1/T1/CEPT Line Interface eSE D Table 5. Logic Interface Characteristics An internal pull-up resistor is provided on the TRi lead. Internal pull-down devices are provided on the following leads: CS, MODE1, MODE2, EC1, EC2, EC3, TBS, LOOPA, and LOOPB. The internal pull-up or pull-down devices require the input to source or sink no more than 20 pA. -40 C < TA < +85 C; VoD =5V+ 10% Parameter Symbol Min Max | Unit Input Voltage: Low VIL GNDp | 08 Vv High VIH 2.0 Vppp Vv Output Voltage: . Low VOL GNDp | 0.4 Vv High VOH 2.4 Vppp | V Input Capacitance Ci _ 20 pF Load Capacitance CL _ 40 pF Source Current lsource 4.9 mA Sink Current Isink _ 4.9 mA All duty cycle and timing relationships for receive and transmit data signals are referenced to a TTL, 1.4 V threshold level. Figure 14 shows this timing. Table 6. Receiver Specifications Parameter Min | Typ | Max | Unit Recelver Sensitivity DS1 0.85 _ _ Vp CEPT 0.7 Vp Analog LOS Level DS1 |048/ | Vp CEPT |028/ | Vp PLL1* 3 dB bandwidth 33 _ kHz Peaking 1.2 2 dB VCO frequency error | +3 % Input Density (1s)" 25] | | % Return Loss:* 51 kHz - 102 kHz 12 dB 102 kHz - 2.048 MHz 18 ~ _ dB 2.048 MHz - 3.072 MHz 14 _ _ dB t t According to CC/TT G.703/RC6367Areturn loss specifications (CEPT only). * Transfer characteristics (1/8 Input), The maximum number of consecutive Os = 15, 18 Mi 005002 0003967 1 mi T-75-11-Q9nee ee a on ne arnewernnestnat wen TR ie ia eG A T & T MELEC (I C) eSE D M@ 0050026 000359b8 3 Mi T~75-1-29 T7290 DS1/T1/CEPT Line Interface Se eee he eee Table 7. Transmitter Specifications . - Parameter Min | Typ | Max | Unit Output Pulse Amplitude: T1 2.7 3.0 3.3 V DS1 (at DSX) 24 | 30 | 36 V CEPT (into 75 9) 2.13 | 2.37 | 2.61 V CEPT (into 120 n) 27 | 30 | 33 V Output Pulse Width: T1 279 324 369 ns DS1 330 350 370 ns CEPT 219 | 244 269 ns Output Power Levels: T1 (8 kHz band at 772 kHz) 12.0 | 165 | 19.0 | dBm T1 (3 kHz band at 1544 kHz) -25 | -39 ~ dB DS1 (2 kHz band at 772 kHz) k 12.6 | 16.5 | 17.9 | dBm DS1 (2 kHz band at 1544 kHz) -29 -39 _ dB Positive/Negative Pulse Imbalance: DSi - - 0.5 dB ceptt - | - | 45 | % CEPT Zero Level! - - 10 % Return Loss:* 51 kHz 102 kHz 8 dB 102 kHz 2.048 MHz 14 _ _ dB 2.048 MHz - 3.072 MHz 10 _ _ dB Below the power at 772 kHz. t Percentage of the pulse amplitude. t According to CH-PTT return loss specifications (CEPT only). 19- er erg ee weg eee og gee po perorpe ten tetg es on tego St a ae neem ee HE ee De AT & T MELEC (I C) eSE D m@ 0050026 0003969 5 me T-75-]]-29 T7290 DS1/T1/CEPT Line Interface Timing Characteristics tTCHITCH2 tTCLTCL TCLK tTCL2TCL1 tTDVTCL TPDATA on e TNDATA tTCLTDX tRCLRDV RCLK tRDVRCH RPDATA on : x RNDATA _s @ tRCHRDX Figure 14. Interface Data Timing Table 8. Interface Data Timing (See Figure 14.) Symbol Parameter Min | Typ | Max | Unit tTCLTCL TCLK Clock Period: P P DS1/T1 647.7 ns CEPT t 488 t ns {TDC TCLK Duty Cycle 40 50 60 % tTDVTCL Transmit Data Setup Time 50 ns tTCLTDX _| Transmit Data Hold Time 40 | ns tTCH1TCH2 | Clock Rise Time (10% 90%) | _ 40 ns tTCL2TCL1 Clock Fail Time (10% 90%) | 40 ns tRDVRCH Receive Data Setup Time 1490 | _ ns tRCHRDX Receive Data Hold Time 180 | _ ns tRCLRDV Receive Propagation Delay 40 ns * A tolerance of + 130 ppm. A tolerance of + 50 ppm. 20=~ AT & T MELEC (I C) ll, SRE ee ee ee ee i, 25 D mm 0050026 0003970 1 mi T=75-11-24 wee RR T7290 DS1/T1/CEPT Line Interface TBS MODE! none Ey EC2 EC3 LOOPA LOOPB (S) tCSL2CSL1 tCSH1CSH2 ORE tSVCSL | coveon _, a tCSHSX Figure 15. Microprocessor Interface Timing Table 9. Microprocessor Interface Timing (See Figure 15.) Symbol Parameter Min | Max | Unit tSVCSL Control Signal Setup Time 50 ns tCSLCSH Control Signal Pulse Width Time 40 ns tCSHSX Control Signal Hold Time 40 ns tCSH1CSH2 | Control Signal Rise Time (10% 90%) | 40 ns tCSL2CSLi Control Signal Rise Time (10% 90%) | 40 ns 21_ fect gees epee eee ene Ug a ate Ee ee masses St avg teen ane : sense her, sama tee 25 D Mm cOSo02 O003971 3 mm T-715-11-29 AT & T MELEC (I) T7290 DS1/T1/CEPT Line Interface Outline Diagrams 28-Pin, Plastic DIP All dimensions are in inches and (millimeters). GZ | 615 (15.62) MAX r ba 165 (4.19) b = = MAX 4 AN A ~- NS A 125 (3.17) SEATING PLANE _/ 015 (.38) MIN MIN if . .010 (.25) 100 (2.54) .600 (15.62) BSC -700 (17.78) MAX 22__" owe ee eT - ae setee temas A T & T MELEC (I C) ~ <a saree Eb 25E D Mm 0050025 0003972 5 mm T-25-11-29 T7290 DS1/T1/CEPT Line Interface 28-Pin, Plastic SOJ All dimensions are in inches and (millimeters). 28 qo == | ,010 (.25) R 020 (.51) R -010 (.25) ) dss) an <= __t MAX MAX oo oo } a 005 (.13) MAX 1 - | .039 (.99) R ENLARGED DETAIL '+_-_---~.708 (17.98) MAX _} perenne SEE ENLARGED DETAIL. 005 (.13) TYP : _ \_ 9 094 (2.38) 140 (3.56) MAX j ) MAX Ty MAX Cf f+ 4, L 041 (1.04) Qe 050 (1.27) e} e.020 (.51) 6a em Ordering Information Code Package Temperature T7290-PL | 28-Pin, Plastic DIP 40 C to +85 C T7290-EL | 28-Pin, Plastic SOU | 40 C to +85 C 23