HM534251B Series 262144-word x 4-bit Multiport CMOS Video RAM Description The HM534251B is a 1-Mbit multiport video RAM equipped with a 256-kword x 4-bit dynamic RAM and a 512-word x 4-bit SAM (serial access memory). Its RAM and SAM operate independently and asynchronously. It can transfer data between RAM and SAM and has write mask function. Features * Multiport organization Asynchronous and simultaneous operation of RAM and SAM capability RAM: 256-kword x 4-bit SAM: 512-word x 4-bit * Access time RAM: 60 ns/70 ns/80 ns/100 ns max SAM: 20 ns/22 ns/25 ns/25 ns max * Cycle time RAM: 125 ns/135 ns/150 ns/180 ns min SAM: 25 ns/25 ns/30 ns/30 ns min * Low power Active RAM: 413 mW max SAM: 275 mW max Standby 38.5 mW max * High-speed page mode capability * Mask write mode capability * Bidirectional data transfer cycle between RAM and SAM capability * Real time read transfer cycle capability * 3 variations of refresh (8 ms/512 cycles) RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible HM534251B Series Ordering Information Type No. Access Time Package HM534251BJ-6 60 ns 400-mil 28-pin plastic SOJ (CP-28D) HM534251BJ-7 70 ns HM534251BJ-8 80 ns HM534251BJ-10 100 ns HM534251BZ-6 60 ns HM534251BZ-7 70 ns HM534251BZ-8 80 ns HM534251BZ-10 100 ns 400-mil 28-pin plastic ZIP (ZP-28) Pin Arrangement HM534251BJ Series SC SI/O0 SI/O1 DT/OE I/O0 I/O1 WE NC RAS A8 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top View) 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 HM534251BZ Series VSS SI/O3 SI/O2 SE I/O3 I/O2 NC CAS NC A0 A1 A2 A3 A7 I/O2 SE SI/O3 SC SI/O1 I/O0 WE RAS A6 A4 A7 A2 A0 CAS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 1 3 5 7 9 11 13 15 17 19 21 23 25 27 (Bottom View) NC I/O3 SI/O2 VSS SI/O0 DT/OE I/O1 NC A8 A5 VCC A3 A1 NC HM534251B Series Pin Description Pin Name Function A0 - A8 Address inputs I/O0 - I/O3 RAM port data inputs/outputs SI/O0 - SI/O3 SAM port data inputs/outputs RAS Row address strobe CAS Column address strobe WE Write enable DT/OE Data transfer/Output enable SC Serial clock SE SAM port enable VCC Power supply VSS Ground NC No connection 3 HM534251B Series Block Diagram A0 - A8 Row Address Buffer Refresh Counter Serial Address Counter Sense Amplifier & I/O Bus SAM I/O Bus Memory Array Data Register Column Decoder Row Decoder Input Data Control Mask Register Serial Output Buffer Serial Input Buffer SI/O0 - SI/O3 Input Buffer Output Buffer Timing Generator RAS CAS DT/OE WE SC SE I/O0 - I/O3 4 SAM Column Decoder Column Address Buffer HM534251B Series Pin Functions RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals determine the operation cycle of the HM534251B. Table 1. Operation Cycles of the HM534251B Input Level At The Falling Edge Of RAS CAS DT/OE WE SE Operation Mode L X X X CBR refresh H L L L Write transfer H L L H Pseudo transfer H L H X Read transfer H H L X Read/mask write H H H X Read/write Note: X : Don't care. CAS (input pin): Column address is fetched into chip at the falling edge of CAS. CAS controls output impedance of I/O in RAM. A0-A8 (input pins): Row address is determined by A0-A8 level at the falling edge of RAS. Column address is determined by A0-A8 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. WE (input pin): WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge of RAS, the HM534251B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (WE level at the falling edge of RAS is don't care in read cycle.) When WE is high at the falling edge of RAS, a normal write cycle is executed. After that, WE switches read/write cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is high, data is transferred from RAM to SAM (data is read from RAM). I/O0 - I/O3 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After that, they function as input/output pins as those of a standard DRAM. DT/OE (input pin): DT/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. 5 HM534251B Series SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because internal pointer is incremented at the rising edge of SC. SI/O0-SI/O3 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was a pseudo transfer cycle or write transfer cycle, SI/O inputs data. Operation of HM534251B RAM Read Cycle (DT/OE high and CAS high at the falling edge of RAS) Row address is entered at the RAS falling edge and column address at the CAS falling edge to the device as in standard DRAM. Then, when WE is high and DT/OE is low while CAS is low, the selected address data outputs through I/O pin. At the falling edge of RAS, DT/OE and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (t AA ) and RAS to column address delay time (tRAD) specifications are added to enable high-speed page mode. RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) (DT/OE high and CAS high at the falling edge of RAS) * Normal Mode Write Cycle (WE high at the falling edge of RAS) When CAS and WE are set low after driving RAS low, a write cycle is executed and I/O data is written in the selected addresses. When all 4 I/Os are written, WE should be high at the falling edge of RAS to distinguish normal mode from mask write mode. If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and I/O becomes in high impedance. Data is entered at the CAS falling edge. If WE is set low after the CAS falling edge, this cycle becomes a delalyed write cycle. Data is input at the WE falling. I/O does not become high impedance in this cycle, so data should be entered with OE in high. If WE is set low after tCWD (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-modifywrite cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving OE high. * Mask Write Mode (WE low at the falling edge of RAS) If WE is set low at the falling edge of RAS, the cycle becomes a mask write mode cycle which writes only to selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of RAS. Then the data is written in high I/O pins and masked in low ones and internal data is retained. This mask data is effective during the RAS cycle. So, in high-speed page mode cycle, the mask data is retained during the page access. 6 HM534251B Series High-Speed Page Mode Cycle (DT/OE high and CAS high at the falling edge of RAS) High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one third of the random read/write cycle. Note that address access time (tAA), RAS to column address delay time (tRAD ), and access time from CAS precharge (t ACP ) are added. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Transfer Operation The HM534251B provides the read transfer cycle, pseudo transfer cycle and write transfer cycle as data transfer cycles. These transfer cycles are set by driving CAS high and DT/OE low at the falling edge of RAS. They have following functions: (1) Transfer data between row address and SAM data register (except for pseudo transfer cycle) Read transfer cycle:RAM to SAM Write transfer cycle:SAM to RAM (2) Determine SI/O state Read transfer cycle:SI/O output Pseudo transfer cycle and write transfer cycle: SI/O input (3) Determine first SAM address to access after transferring at column address (SAM start address). SAM start address must be determined by read transfer cycle or pseudo transfer cycle after power on, and determined for each transfer cycle. Read Transfer Cycle (CAS high, DT/OE low and WE high at the falling edge of RAS) This cycle becomes read transfer cycle by driving DT/OE low and WE high at the falling edge of RAS. The row address data (512 x 4-bit) determined by this cycle is transferred to SAM data register synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs from SAM start address determined by column address. In read transfer cycle, DT/OE must be risen to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and DT/OE rising edge and t SDH (min) specified between the first SAM access and DT/OE rising edge must be satisfied. (See figure 1.). 7 HM534251B Series RAS CAS Xi Address DT/OE Yj L t SDD t SDH SC Yj SI/O SAM Data before Transfer Yj + 1 SAM Data after Transfer Figure 1. Real Time Read Transfer When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before t SZS (min) of the first SAM access to avoid data contention. Pseudo Transfer Cycle (CAS high, DT/OE low, WE low and SE high at the falling edge of RAS) Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM. This cycle starts when CAS is high, D T/OE low, W E low and SE high at the falling edge of RAS. Data should be input to SI/O later than t SID (min) after RAS becomes low to avoid data contention. SAM access becomes enabled after t SRD (min) after RAS becomes high. In this cycle, SAM access is inhibited during RAS low, therefore, SC must not be risen. Write Transfer Cycle (CAS high, DT/OE low, WE low and SE low at the falling edge of RAS) Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after t SRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle can be written to other address of RAM by write transfer cycle. However, the address to write data must be the same MSB of row address (AX8) as that of the read transfer cycle. 8 HM534251B Series SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Serial Write Cycle If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is high, SI/O data isn't fetched into data register. Internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) R AS -only refresh cycle, (2) CAS-before-RAS (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate RAS such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. (1) RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only R AS cycle with CAS fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this cycle from data transfer cycle, DT/OE must be high at the falling edge of RAS. (2) CBR Refresh Cycle: CBR refresh cycle is set by activating CAS before RAS. In this cycle, refresh address need not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits don't operate. (3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS when DT/OE and CAS keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift register and selector), organized as fully static circuitry, require no refresh. 9 HM534251B Series Absolute Maximum Ratings Parameter Symbol Value Unit VT -1.0 to +7.0 V VCC -0.5 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Terminal voltage *1 Power supply voltage Note: *1 1. Relative to VSS . Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter *1 Supply voltage *1 Input high voltage Input low voltage *1 Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V VIH 2.4 -- 6.5 V -- 0.8 V VIL -0.5 *2 Notes: 1. All voltages referred to V SS . 2. -3.0 V for pulse width 10 ns. DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM534251B -6 -7 -8 -10 Test Conditions Parameter Symbol Min Max Min Max Min Max Min Max Unit RAM Port Operating current I CC1 -- 75 I CC7 -- 125 -- Standby current I CC2 -- 7 I CC8 -- 50 10 SAM Port -- 55 mA RAS, CAS cycling SC = VIL, t RC = min SE = VIH 120 -- 100 -- 95 mA SE = VIL, SC cycling t SCC = min -- 7 -- 7 -- 7 mA RAS, CAS = VIH SC = VIL, SE = VIH -- 50 -- 40 -- 40 mA SE = VIL, SC cycling t SCC = min -- 70 -- 60 HM534251B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont) HM534251B -6 -7 -8 -10 Test Conditions Parameter Symbol Min Max Min Max Min Max Min Max Unit RAM Port RAS -only refresh current I CC3 -- 75 I CC9 -- 125 -- I CC4 -- 80 I CC10 -- 130 -- 130 -- 110 -- 105 mA I CC5 -- 50 -- 45 -- 40 -- 35 mA RAS cycling t RC = min SC = VIL, SE = VIH I CC11 -- 100 -- 95 -- 80 -- 75 mA SE = VIL, SC cycling t SCC = min I CC6 -- 80 75 -- 65 -- 60 mA RAS, CAS cycling SC = VIL, t RC = min SE = VIH I CC12 -- 130 -- I LI -10 10 -10 10 -10 10 -10 10 A Output leakage I LO current -10 10 -10 10 -10 10 -10 10 A Output high voltage VOH 2.4 -- 2.4 -- 2.4 -- 2.4 -- V I OH = -2 mA Output low voltage VOL -- 0.4 -- 0.4 -- 0.4 -- 0.4 V I OL = 4.2 mA Page mode current CAS -beforeRAS refresh current Data transfer current Input leakage current -- -- -- SAM Port -- 55 mA RAS cycling CAS = VIH t RC = min SC = VIL, SE = VIH 120 -- 100 -- 95 mA SE = VIL, SC cycling t SCC = min 80 70 65 mA CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH 70 -- -- 125 -- 60 -- 105 -- SE = VIL, SC cycling t SCC = min SE = VIL, SC cycling t SCC = min 100 mA Notes: 1. I CC depends on output loading condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while RAS is low and CAS is high. 11 HM534251B Series Capacitance (Ta = 25C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address = VSS) Parameter Symbol Min Typ Max Unit Address CI1 -- -- 5 pF Clock CI2 -- -- 5 pF I/O, SI/O CI/O -- -- 7 pF AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *16 Test Conditions * * * * * Input rise and fall time: 5 ns Input pulse levels : V SS to 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: See figures I OH = - 2 mA +5V I OH = - 2 mA I OL = 4.2 mA I OL = 4.2 mA I/O *1 100 pF Output Load (A) Note: 1. Including scope & jig. 12 +5V SI / O *1 50 pF Output Load (B) HM534251B Series Common Parameter HM534251B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 125 -- 135 -- 150 -- 180 -- ns RAS precharge time t RP 55 -- 55 60 70 ns RAS pulse width t RAS 60 10000 70 10000 80 10000 100 10000 ns CAS pulse width t CAS 20 -- 20 -- 20 -- 25 -- ns Row address setup time t ASR 0 -- 0 -- 0 -- 0 -- ns Row address hold time t RAH 10 -- 10 -- 10 -- 10 -- ns Column address setup time t ASC 0 -- 0 -- 0 -- 0 -- ns Column address hold time t CAH 15 -- 15 -- 15 -- 15 -- ns RAS to CAS delay time t RCD 20 40 20 50 20 60 20 75 ns RAS hold time referred to CAS t RSH 20 -- 20 -- 20 -- 25 -- ns CAS hold time referred to RAS t CSH 60 -- 70 -- 80 -- 100 -- ns CAS to RAS precharge time t CRP 10 -- 10 -- 10 -- 10 -- ns Transition time (rise to fall) tT 3 50 3 50 3 50 3 50 ns Refresh period t REF -- 8 -- 8 -- 8 -- 8 ms DT to RAS setup time t DTS 0 -- 0 -- 0 -- 0 -- ns DT to RAS hold time t DTH 10 -- 10 -- 10 -- 10 -- ns Data-in to CAS delay time t DZC 0 -- 0 -- 0 -- 0 -- ns 4 Data-in to OE delay time t DZO 0 -- 0 -- 0 -- 0 -- ns 4 Output buffer turn-off delay referred to CAS t OFF1 -- 20 -- 20 -- 20 -- 20 ns 5 Output buffer turn-off delay referred to OE t OFF2 -- 20 -- 20 -- 20 -- 20 ns 5 -- -- -- 2 3 13 HM534251B Series Read Cycle (RAM), Page Mode Read Cycle HM534251B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Access time from RAS t RAC -- 60 -- 70 -- 80 -- 100 ns 6, 7 Access time from CAS t CAC -- 20 -- 20 -- 20 -- 25 ns 7, 8 Access time from OE t OAC -- 20 -- 20 -- 20 -- 25 ns 7 Address access time t AA -- 35 -- 35 -- 40 -- 45 ns 7, 9 Read command setup time t RCS 0 -- 0 -- 0 -- 0 -- ns Read command hold time t RCH 0 -- 0 -- 0 -- 0 -- ns 10 Read command hold time t RRH referred to RAS 10 -- 10 -- 10 -- 10 -- ns 10 RAS to column address delay time t RAD 15 25 15 35 15 40 15 55 ns 2 Column address to RAS lead time t RAL 35 -- 35 -- 40 -- 45 -- ns Column address to CAS lead time t CAL 35 -- 35 -- 40 -- 45 -- ns Page mode cycle time t PC 45 -- 45 -- 50 -- 55 -- ns CAS precharge time t CP 10 -- 10 -- 10 -- 10 -- ns Access time from CAS precharge t ACP -- 40 -- 40 -- 45 -- 50 ns Page mode RAS pulse width t RASP 60 100000 70 14 100000 80 100000 100 100000 ns HM534251B Series Write Cycle (RAM), Page Mode Write Cycle HM534251B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 -- 0 -- 0 -- 0 -- ns Write command hold time t WCH 15 -- 15 -- 15 -- 15 -- ns Write command pulse width t WP 15 -- 15 -- 15 -- 15 -- ns Write command to RAS lead time t RWL 20 -- 20 -- 20 -- 20 -- ns Write command to CAS lead time t CWL 20 -- 20 -- 20 -- 20 -- ns Data-in setup time t DS 0 -- 0 -- 0 -- 0 -- ns 12 Data-in hold time t DH 15 -- 15 -- 15 -- 15 -- ns 12 WE to RAS setup time t WS 0 -- 0 -- 0 -- 0 -- ns WE to RAS hold time t WH 10 -- 10 -- 10 -- 10 -- ns Mask data to RAS setup time t MS 0 -- 0 -- 0 -- 0 -- ns Mask data to RAS hold time t MH 10 -- 10 -- 10 -- 10 -- ns OE hold time referred to WE t OEH 20 -- 20 -- 20 -- 20 -- ns Page mode cycle time t PC 45 -- 45 -- 50 -- 55 -- ns CAS precharge time t CP 10 -- 10 -- 10 -- 10 -- ns CAS to data-in delay time t CDD 20 -- 20 -- 20 -- 20 -- ns Page mode RAS pulse width 60 100000 70 t RASP 100000 80 11 13 100000 100 100000 ns 15 HM534251B Series Read-Modify-Write Cycle HM534251B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 175 -- 185 -- 200 -- 230 -- ns RAS pulse width (read-modify-write cycle) t RWS 110 10000 120 10000 130 10000 150 10000 ns CAS to WE delay time t CWD 45 -- 45 -- 45 -- 50 -- ns 14 Column address to WE delay time t AWD 60 -- 60 -- 65 -- 70 -- ns 14 OE to data-in delay time t ODD 20 -- 20 -- 20 -- 20 -- ns 12 Access time from RAS t RAC -- 60 -- 70 -- 80 -- 100 ns 6, 7 Access time form CAS t CAC -- 20 -- 20 -- 20 -- 25 ns 7, 8 Access time from OE t OAC -- 20 -- 20 -- 20 -- 25 ns 7 Address access time t AA -- 35 -- 35 -- 40 -- 45 ns 7, 9 RAS to column address delay time t RAD 15 25 15 35 15 40 15 55 ns Read command setup time t RCS 0 -- 0 -- 0 -- 0 -- ns Write command to RAS lead time t RWL 20 -- 20 -- 20 -- 20 -- ns Write command to CAS lead time t CWL 20 -- 20 -- 20 -- 20 -- ns Write command pulse width t WP 15 -- 15 -- 15 -- 15 -- ns Data-in setup time t DS 0 -- 0 -- 0 -- 0 -- ns 12 Data-in hold time t DH 15 -- 15 -- 15 -- 15 -- ns 12 OE hold time referred to WE t OEH 20 -- 20 -- 20 -- 20 -- ns 16 HM534251B Series Refresh Cycle HM534251B -6 Parameter Symbol Min -7 -8 -10 Max Min Max Min Max Min Max Unit CAS setup time t CSR (CAS-before-RAS refresh) 10 -- 10 -- 10 -- 10 -- ns CAS hold time t CHR (CAS-before-RAS refresh) 10 -- 10 -- 10 -- 10 -- ns RAS precharge to CAS hold time 10 -- 10 -- 10 -- 10 -- ns t RPC Notes 17 HM534251B Series Read Transfer Cycle HM534251B -6 -7 Max Min -10 Parameter Symbol Min Max DT hold time referred to RAS t RDH 50 10000 60 10000 65 10000 80 10000 ns DT hold time referred to CAS t CDH 20 -- 20 -- 20 -- 25 -- ns DT hold time referred to column address t ADH 25 -- 25 -- 30 -- 30 -- ns DT precharge time t DTP 20 -- 20 -- 20 -- 30 -- ns DT to RAS delay time t DRD 65 -- 65 -- 70 -- 80 -- ns SC to RAS setup time t SRS 25 -- 25 -- 30 -- 30 -- ns 1st SC to RAS hold time t SRH 60 -- 70 -- 80 -- 100 -- ns 1st SC to CAS hold time t SCH 25 -- 25 -- 25 -- 25 -- ns 1st SC to column address hold time t SAH 40 -- 40 -- 45 -- 50 -- ns Last SC to DT delay time t SDD 5 -- 5 -- 5 -- 5 -- ns 1st SC to DT hold time t SDH 10 -- 10 -- 15 -- 15 -- ns Serial data-in to 1st SC delay time t SZS 0 -- 0 -- 0 -- 0 -- ns Serial clock cycle time t SCC 25 -- 25 -- 30 -- 30 -- ns SC pulse width t SC 5 -- 5 -- 10 -- 10 -- ns SC precharge time t SCP 10 -- 10 -- 10 -- 10 -- ns SC access time t SCA -- 20 -- 22 -- 25 -- 25 ns Serial data-out hold time t SOH 5 -- 5 -- 5 -- 5 -- ns Serial data-in setup time t SIS 0 -- 0 -- 0 -- 0 -- ns Serial data-in hold time t SIH 15 -- 15 -- 15 -- 15 -- ns RAS to column address delay time t RAD 15 25 15 35 15 40 15 55 ns Column address to RAS lead time t RAL 35 -- 35 -- 40 -- 45 -- ns DT high hold time from RAS precharge t DTHH 10 -- 10 -- 10 -- 10 -- ns 18 Min -8 Max Min Max Unit Notes 15 HM534251B Series Pseudo Transfer Cycle, Write Transfer Cycle HM534251B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes SE setup time referred to RAS t ES 0 -- 0 -- 0 -- 0 -- ns SE hold time referred to RAS t EH 10 -- 10 -- 10 -- 10 -- ns SC setup time referred to RAS t SRS 25 -- 25 -- 30 -- 30 -- ns RAS to SC delay time t SRD 20 -- 20 -- 25 -- 25 -- ns Serial output buffer turn-off t SRZ time referenced to RAS 10 40 10 40 10 45 10 50 ns RAS to serial data-in delay t SID time 40 -- 40 -- 45 -- 50 -- ns Serial clock cycle time t SCC 25 -- 25 -- 30 -- 30 -- ns SC pulse width t SC 5 -- 5 -- 10 -- 10 -- ns SC precharge time t SCP 10 -- 10 -- 10 -- 10 -- ns SC access time t SCA -- 20 -- 22 -- 25 -- 25 ns 15 SE access time t SEA -- 20 -- 22 -- 25 -- 25 ns 15 Serial data-out hold time t SOH 5 -- 5 -- 5 -- 5 -- ns Serial write enable setup time t SWS 5 -- 5 -- 5 -- 5 -- ns Serial data-in setup time t SIS 0 -- 0 -- 0 -- 0 -- ns Serial data-in hold time t SIH 15 -- 15 -- 15 -- 15 -- ns 19 HM534251B Series Serial Read Cycle, Serial Write Cycle HM534251B -6 -7 -8 -10 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Serial clock cycle time t SCC 25 -- 25 -- 30 -- 30 -- ns SC pulse width t SC 5 -- 5 -- 10 -- 10 -- ns SC precharge width t SCP 10 -- 10 -- 10 -- 10 -- ns Access time from SC t SCA -- 20 -- 22 -- 25 -- 25 ns 15 Access time from SE t SEA -- 20 -- 22 -- 25 -- 25 ns 15 Serial data-out hold time t SOH 5 -- 5 -- 5 -- 5 -- ns Serial output buffer turn-off t SEZ time referred to SE -- 20 -- 20 -- 20 -- 20 ns Serial data-in setup time t SIS 0 -- 0 -- 0 -- 0 -- ns Serial data-in hold time t SIH 15 -- 15 -- 15 -- 15 -- ns Serial write enable setup time t SWS 5 -- 5 -- 5 -- 5 -- ns Serial write enable hold time t SWH 15 -- 15 -- 15 -- 15 -- ns Serial write disable setup time t SWIS 5 -- 5 -- 5 -- 5 -- ns Serial write disable hold time t SWIH 15 -- 15 -- 15 -- 15 -- ns 5 Notes: 1. AC measurements assume t T = 5 ns. 2. When t RCD > tRCD (max) or tRAD > tRAD (max), access time is specified by tCAC or tAA. 3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. 5. t OFF1 (max), tOFF2 (max) and tSEZ (max) are defined as the time at which the output acheives the open circuit condition (V OH -100 mV, VOL +100 mV). 6. Assume that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tCAC . 9. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tAA . 10. If either tRCH of tRRH is satisfied, operation is guaranteed. 11. When t WCS tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of CAS or WE. 13. Either t CDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or OE prior to applying data to the device when output buffer is on. 20 HM534251B Series 14. When t AWD tAWD (min) and tCWD tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. t ODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. 15. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 16. After power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17. XXX: H or L (H: V IH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout Timing Waveforms *17 Read Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t CAS t RCD CAS t RAD t ASR Address t RAL t RAH t ASC Row Column t RCS WE t CAL t CAH t RRH t RCH t CAC t AA I/O (Output) t CDD t OFF1 t RAC Valid Dout t DZC I/O (Input) t OAC t OFF2 t DZO t DTS t DTH DT/OE 21 HM534251B Series Early Write Cycle t RC t RAS t RP RAS t CRP t CSH t RCD CAS t ASR Address t RAH t CAH t ASC Row t WS t RSH t CAS Column t WH t WCS t WCH *1 WE High-Z I/O (Output) t MH t MS I/O (Input) t DS Mask Data t DTS t DTH t DH Valid Din DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Delayed Write Cycle t RC t RAS t RP RAS CAS t CAS t ASR Address t RAH Row t WS I/O (Input) t ASC t CAH Columun t RWL t WH t MS t CWL t WP *1 WE I/O (Output) t CRP t CSH t RSH t RCD t MH Mask Data t DTH t DTS t DS t DZC t OFF2 t ODD t DH Valid Din t OEH DT/OE Note: 22 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. HM534251B Series Read-Modify-Write Cycle t RWC t RP t RWS RAS t CRP t RCD CAS t RAD t ASR Address t RAH Row t WS t ASC t CAH Columun t WH t AWD t CWD t RCS t CAC t AA *1 WE t RWL t CWL t WP t RAC I/O (Output) Valid Dout t MS I/O (Input) t MH Mask Data t DTS t DTH t DS t OAC t DZC Valid Din t OFF2 t ODD t DZO t DH t OEH DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Page Mode Read Cycle t RC t RASP RAS t CSH t RCD t CAS CAS t RAD t ASR Address t RAH t ASC Row WE t PC t CP t CAL t CAH Columun t RCS t ASC Valid Dout t DZC I/O (Input) t DTS t CDD t OAC t OFF2 t CAL t CAH t ASC Columun t RRH t RCH t RCS t RCH t AA t ACP t CAC t OFF1 t AA t ACP t CAC Valid Dout t DZC t OAC t CRP t RAL t CAL t CAH Columun t RCH t RSH t CAS t CP t CAS t RCS t RAC t OFF1 t AA t CAC I/O (Output) t RP t CDD t OFF2 t OFF1 Valid Dout t DZC t OAC t CDD t DZO t DTH DT/OE 23 HM534251B Series Page Mode Write Cycle (Early Write) t RC t RP t RASP RAS t PC t CSH t RCD CAS t ASR Address t CP t CAS t RAH t ASC t CAH t ASC Row Column t WS t WH t WCS t WCH WE t RSH t CAS t CP t CAS t CAH t ASC t CRP t CAH Column Column t WCS t WCH t WCS t WCH *1 High-Z I/O (Output) t MS I/O (Input) t MH t DS Mask Data t DTS t DH t DH t DS Valid Din t DH t DS Valid Din Valid Din t DTH DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Page Mode Write Cycle (Delayed Write) t RC t RASP t RP RAS t CSH t PC t RCD CAS t ASR t RAH t ASC Address Row t WS t CAH Column t ASC t CAH Column t ASC t CRP t CAH Column t RWL t CWL t CWL t WH t RSH t CAS t CP t CAS t WP t CWL t WP t WP *1 WE I/O (Output) t CP t CAS t MH t MS I/O (Input) Mask Data t DTS t DS t DH Valid Din t DS t DH Valid Din t DS t DH Valid Din t OEH DT/OE Note: 24 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. HM534251B Series RAS-Only Refresh Cycle t RC t RP t RAS RAS t RPC t CRP CAS t ASR t RAH Row Address t OFF1 I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTH t DTS DT/OE CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC t CP t RP t RAS t RPC t CSR t CHR t CSR Inhibit Falling Transition CAS Address WE I/O (Output) t OFF1 High-Z DT/OE 25 HM534251B Series Hidden Refresh Cycle t RC t RC t RAS t RAS t RP t RP RAS t RCD CAS t ASR Address t RSH t CRP t CHR t RAD t RAL t RAH t ASC t CAH Row Column t RCS t RRH t CAC WE t AA t RAC I/O (Output) t OFF1 Valid Dout t DZC I/O (Input) t OAC t OFF2 t DZO t DTH t DTS DT/OE Read Transfer Cycle (1) t RC t RP t RAS RAS t CRP t CSH t RCD t RSH t CAS CAS t RAD t RAH t ASR Address Row t WS t RAL t ASC t CAH SAM Start Address t WH WE t DTHH High-Z I/O (Output) t CDH t DTS t DRD t ADH t RDH t DTP DT/OE t SCC t SCC t SDD SC SI/O (Output) SI/O (Input) 26 t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SCC t SDH t SC t SCA t SOH Valid Sout Previous Row t SCC t SCP t SOH Valid Sout New Row HM534251B Series Read Transfer Cycle (2) t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS CAS t ASR Address t RAD t RAH t CAH Sam Start Address Row t WS t RAL t ASC t WH WE t DTHH High-Z I/O (Output) t DTS t DRD t DTP t DTH DT/OE t SCH t SAH t SRS t SDH t SC t SCP t SCP Inhibit Rising Transition SC t SIS t SIH t SCA t SCA t SRH SI/O (Output) SI/O (Input) t SCC t SC t SOH t SZS Valid Sout Valid Sin 27 HM534251B Series Pseudo Transfer Cycle t RC t RAS t RP RAS t CSH t CRP t RSH t RCD t CAS CAS t RAH t ASR t WS t CAH SAM Start Address Row Address t ASC t WH WE High - Z I/O (Output) t DTS t DTH DT/OE t ES t SEZ t EH t SWS SE t SRS t SRD t SCP t SC t SCA t SOH Valid Sout t SRZ Valid Sout t SID SI/O (Input) 28 t SCP Inhibit Rising Transition SC SI/O (Output) t SCC t SC t SIS t SIH Valid Sin t SIS t SIH Valid Sin HM534251B Series Write Transfer Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t RCD t CAS CAS t RAH t ASR Row Address t WS t ASC t CAH SAM Start Address t WH WE High-Z I/O (Output) t DTS t DTH DT/OE t ES t EH t SWS SE t SRS t SRD t SWS t SC SC SI/O (Output) SI/O (Input) t SCP t SCC t SC t SCP Inhibit Rising Transition t SIS t SIH Valid Sin t SIS t SIH Valid Sin t SIS t SIH Valid Sin 29 HM534251B Series Serial Read Cycle SE tSCC SC SI/O (Output) tSCC tSC tSCP tSC tSCA tSOH tSCP tSC tSCA Valid Sout Valid Sout Serial Write Cycle tSWIS tSWH tSWIH tSWS SE tSCC tSC tSCP SC tSIS SI/O (Input) 30 tSIH Valid Sin tSC tSCA tSOH tSEA tSEZ Valid Sout tSCC tSCP tSCC tSC tSCC tSC tSCP tSIS tSC tSCP tSIH Valid Sin tSIS tSIH Valid Sin Valid Sout HM534251B Series Package Dimensions HM534251BJ Series (CP-28D) Unit: mm 18.17 18.54 Max 10.16 0.13 1 1.27 +0.25 -0.17 0.80 3.50 0.26 1.30 Max 0.21 2.40 +- 0.24 14 0.74 0.43 0.10 11.18 0.13 15 28 9.40 0.25 0.10 31 HM534251B Series HM534251BZ Series (ZP-28) Unit: mm 1 28 1.27 0.3 M 32 1.045 Max 2.85 + 0.08 0.50 - 0.12 10.16 Max 2.80 Min 8.71 35.58 36.57 Max 0.10 0.25 +- 0.05 2.54