1 April 21, 2004
UL62H1708B
Preliminary
!131072 x 8 bit static CMOS RAM
!35 and 55 ns Access Time
!Common data inputs and
data outputs
!Three-state outputs
!Typ. operating supply current
35 ns: 45mA
55 ns: 30mA
!Standby current <100µA at 125°C
!Power supply voltage 2.5 V
!Operating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
!QS 9000 Quality Standard
!ESD protection > 2000 V
(MIL STD 883C M3015.7)
!Latch-up immunity >100 mA
!Package: SOP32 (450 mil)
TSOP I 32
sTSOP I 32
The UL62H1708B is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H) each address change
leads to a new Read cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E1
and E2, all inputs consist of NOR
gates, so that no pull-up/pull-down
resistors are required.
Low Voltage Automotive Fast 128K x 8 SRAM
Features Description
Pin Configuration
Top View
Signal Name Signal Description
A0 - A16 Address Inputs
DQ0 - DQ7 Data In/Out
E1 Chip Enable 1
E2 Chip Enable 2
GOutput Enable
WWrite Enable
VCC Power Supply Voltage
VSS Ground
n.c. not connected
Pin Description
1
n.c. VCC32
2A16 A1531
4A12 W
29
5A7 A1328
3A14 E230
6A6 A827
7A5 A926
8A4 A1125
12A0 DQ721
9A3 G
24
10
A2 A1023
11A1 E1
22
13DQ0 DQ620
14DQ1 DQ519
SOP
DQ4
DQ3
DQ2
VSS
18
17
15
16
Top View
1
A11 G32
2A9 A1031
4A13 DQ7
29
5W DQ628
3A8 E1
30
6E2 DQ527
7A15 DQ426
8VCC DQ325
12A12 DQ021
9n.c. VSS
24
10
A16 DQ223
11A14 DQ1
22
13A7 A020
14A6 A119
A2
A3
A5
A4
18
17
15
16
TSOP
sTSOP
2 April 21, 2004
UL62H1708B Preliminary
*H or L
Operating Mode E1 E2 W GDQ0 - DQ7
Standby/not selected
* L * * High-Z
H*** High-Z
Internal Read L H H H High-Z
Read L H H L Data Outputs Low-Z
Write L H L * Data Inputs High-Z
Truth Table
Block Diagram
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC VSS W GE1
Row Address
Inputs
Column Address
Inputs
Address
Change
Detector
Column Decoder Row Decoder
Sense Amplifier/
Write Control Logic
Common Data I/O
Memory Cell
Array
1024 Rows x
128 x 8 Columns
A10
A11
A12
A13
A14
A9
A15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
E2
Clock
Generator
3 April 21, 2004
UL62H1708B
Preliminary
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI,as well as
input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
aStresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
bMaximum voltage is 3.6 V
cNot more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Absolute Maximum Ratings aSymbol Min. Max. Unit
Power Supply Voltage VCC -0.3 3.6 V
Input Voltage VI-0.3 VCC + 0.3 bV
Output Voltage VO-0.3 VCC + 0.3 bV
Power Dissipation PD-1W
Operating Temperature K-Type
A-Type
Ta-40
-40
85
125
°C
Storage Temperature Tstg -65 150 °C
Output Short-Circuit Current
at VCC = 2.5 V and VO = 0 V c| IOS |100mA
Characteristics
d-2 V at Pulse Width 10 ns
Recommended
Operating Conditions Symbol Conditions Min. Max. Unit
Power Supply Voltage VCC 2.3 2.7 V
Input Low Voltage dVIL -0.2 0.6 V
Input High Voltage VIH 2.0 VCC + 0.2 V
4 April 21, 2004
UL62H1708B Preliminary
e This parameter is guaranteed, but not tested.
Electrical Characteristics Symbol Conditions
35 55
Unit
Min. Max. Min. Max.
Supply Current - Operating Mode
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
ICC(OP)
ICC(SB)
ICC(SB)1
VCC
VIL
VIH
tcW
tcW
tcW
VCC
VE1= VE2
K-Type
A-Type
VCC
VE1= VE2
K-Type
A-Type
= 2.7 V
= 0.6 V
=2.0 V
= 35 ns
= 55 ns
= 70 ns
=2.7 V
= VCC - 0.2 V
= 2.7 V
= 2.0 V
25
15 e
12 e
70
100
0.5
1
-
15
12 e
70
100
0.5
1
mA
mA
mA
µA
µA
mA
mA
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 2.3 V
= -0.5 mA
=2.3 V
=0.5 mA
2.0
0.4
2.0
0.4
V
V
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 2.7 V
= 2.7 V
= 2.7 V
= 0 V
-2
2
-2
A
µA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
=2.3 V
= 2.0 V
=2.3 V
=0.4 V
0.5
-0.5
0.5
-0.5 mA
mA
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
=2.7 V
=2.7 V
=2.7 V
=0 V
-2
2
-2
A
µA
5 April 21, 2004
UL62H1708B
Preliminary
Switching Characteristics
Read Cycle
Symbol 35 55
Unit
Alt. IEC Min. Max. Min. Max.
Read Cycle Time tRC tcR 35 55 ns
Address Access Time to Data Valid tAA ta(A) 35 55 ns
Chip Enable Access Time to Data Valid tACE ta(E) 35 55 ns
G LOW to Data Valid tOE ta(G) 15 25 ns
E1 HIGH or E2 LOW to Output in High-Z tHZCE tdis(E) 12 15 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
E1 LOW or E2 HIGH to Output in Low-Z tLZCE ten(E) 55ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
Output Hold Time from Address Change tOH tv(A) 55ns
E1 LOW or E2 HIGH to Power-Up Time tPU 00ns
E1 HIGH or E2 LOW to Power-Down Time tPD 35 55 ns
Switching Characteristics
Write Cycle
Symbol 35 55
Unit
Alt. IEC Min. Max. Min. Max.
Write Cycle Time tWC tcW 35 55 ns
Write Pulse Width tWP tw(W) 20 35 ns
Write Setup Time tWP tsu(W) 20 35 ns
Address Setup Time tAS tsu(A) 00ns
Address Valid to End of Write tAW tsu(A-WH) 20 35 ns
Chip Enable Setup Time tCW tsu(E) 25 40 ns
Pulse Width Chip Enable to End of Write tCW tw(E) 25 40 ns
Data Setup Time tDS tsu(D) 15 25 ns
Data Hold Time tDH th(D) 00ns
Address Hold from End of Write tAH th(A) 00ns
W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
W HIGH to Output in Low-Z tLZWE ten(W) 00ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
6 April 21, 2004
UL62H1708B Preliminary
Data Retention
Characteristics
Symbol
Conditions Min. Typ. Max. Unit
Alt. IEC
Data Retention Supply Voltage VCC(DR) 1.5 2.7 V
Data Retention Supply Current ICC(DR) VCC(DR) = 1.5 V
VE1 =VE2 = VCC(DR) - 0.2 V
30 µA
Data Retention Setup Time tCDR tsu(DR) See Data Retention
Waveforms (below)
0ns
Operating Recovery Time tRtrec tcR ns
Data Retention Mode E1 - controlled
Data Retention
2.3 V
tsu(DR) trec
VCC
E1
VCC(DR) 1.5 V
0 V
2.0 V
2.0 V
Data Retention Mode E2 - controlled
VE2(DR) VCC(DR) - 0.2 V or VE2(DR) 0.2 V
VCC(DR) - 0.2 V VE1(DR) VCC(DR) + 0.2 V
0.8 V
0.8 V
2.3 V
0 V
VCC
VE1(DR) VCC(DR) - 0.2 V or VE1(DR) 0.2 V
VE2(DR) 0.2 V
trec
tDR
VCC(DR) 1.5 V
Data Retention
E2
Data Retention Mode
7 April 21, 2004
UL62H1708B
Preliminary
Capacitance Conditions Symbol Min. Max. Unit
Input Capacitance VCC
VI
f
Ta
= 2.5 V
= VSS
= 1 MHz
= 25 °C
CI7pF
Output Capacitance Co7pF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Test Configuration for Functional Check
VIH
VIL
VSS
VCC
2.5 V
481
255
VO
f In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF.
Input level according to the
relevant test measurement
Simultaneous measure-
ment of all 8 output pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
E1
E2
W
G
All pins not under test must be connected with ground by capacitors.
30 pF f
Date of manufacture
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Leadfree Green Package
Product specification
Assembly location and
trace code
Internal Code
Operating Temperature Range
K = -40 to 85 °C
A = -40 to 125 °C
S35AUL62H1708B
Type
Package
S = SOP32 (450 mil)
T=TSOP I 32
T1 = sTSOP I 32
Ordering Code
Leadfree Option
blank = Standard Package
G1 = Leadfree Green Package g
Access Time
35 = 35 ns
55 = 55 ns
Device Marking (example)
ZMD
UL62H1708BSA
35 C 0425
1 ZZ G1
g on special request
Example
8 April 21, 2004
UL62H1708B Preliminary
Previous Data Valid Output Data Valid
Address Valid
Read Cycle 1: Ai-controlled (during Read Cycle : E1 = G = VIL, W = E2 = VIH)
Read Cycle 2: G-, E1, E2-controlled (during Read Cycle: W = VIH)
ta(A)
tcR
tv(A)
Ai
DQi
Output
tcR
High-Z
Addresses Valid
Ai
E1
E2
G
DQi
Output
tdis(E)
tsu(A) ta(E)
tsu(A)
ten(E)
ten(E)
ten(G)
ta(G)
ta(E) tdis(E)
tdis(G)
Output Data Valid
tPD*
tPU*
ICC(OP)
ICC(SB)
* The same applies to E1
50 % 50 %
Write Cycle1: W-controlled
th(D)
Ai
E1
E2
W
DQi
G
DQi
Output
tcW
tsu(E) th(A)
tw(W)
tsu(A)
tsu(E)
tsu(D)
tdis(W) ten(W)
Addresses Valid
High-Z
Input Input Data Valid
9 April 21, 2004
UL62H1708B
Preliminary
Write Cycle 2: E1-controlled
tsu(A)
th(D)
Ai
E1
E2
W
DQi
Input
G
DQi
Output
tcW
tw(E) th(A)
tsu(W)
tsu(E)
tsu(D)
tdis(W)
ten(E)
Addresses Valid
Input Data Valid
High-Z
tdis(G)
Write Cycle 3 (E2-controlled)
High-Z
Input Data Valid
th(D)
tsu(W)
tw(E)
tsu(D)
tcW
Addresses Valid
tsu(A)
tsu(E) th(A)
ten(E) tdis(W)
Ai
E1
E2
W
DQi
Input
G
DQi
Output tdis(G)
L- to H-level undefined H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 D-01109 Dresden P. O. B. 80 01 34 D-01101 Dresden Germany
Phone: +49 351 8822 306Fax: +49 351 8822 337 Email: memory@zmd.de http://www.zmd.de
April 21, 2004
UL62H1708B
Preliminary
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.