Dual Channel, 128-/256-Position, I2C,
Nonvolatile Digital Potentiometer
Data Sheet
AD5122A/AD5142A
Rev. B Document Feedback
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FEATURES
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package option
Qualified for automotive applications
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
FUNCTIONAL BLOCK DIAGRAM
V
DD
INDEP
V
SS
GND
V
LOGIC
7/8
SERIAL
INTERFACE
POWER-ON
RESET
RDAC1
INPUT
REGISTER 1
RDAC2
INPUT
REGISTER 2
EEPROM
MEMORY
A1
W1
B1
A2
W2
B2
AD5122A/
AD5142A
SCL
SDA
RESET
10939-001
ADDR1
ADDR0
Figure 1.
GENERAL DESCRIPTION
The AD5122A/AD5142A potentiometers provide a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to ±6 mA
current density in the Ax, Bx, and Wx pins.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through RAW and RWB the string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making it suitable
for filter design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin-to-pin connection.
The wiper values can be set through an I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
The AD5122A/AD5142A are available in a compact, 16-lead,
3 mm × 3 mm LFCSP and a 16-lead TSSOP. The parts are
guaranteed to operate over the extended industrial temperature
range of −40°C to +125°C.
Table 1. Family Models
Model Channel Position Interface Package
AD51231 Quad 128 I2C LFCSP
AD5124 Quad 128 SPI/I
2
C LFCSP
AD5124 Quad 128 SPI TSSOP
AD5143
1
Quad 256 I
2
C LFCSP
AD5144 Quad 256 SPI/I2C LFCSP
AD5144 Quad 256 SPI TSSOP
AD5144A Quad 256 I2C TSSOP
AD5122 Dual 128 SPI LFCSP/TSSOP
AD5122A Dual 128 I
2
C LFCSP/TSSOP
AD5142 Dual 256 SPI LFCSP/TSSOP
AD5142A Dual 256 I2C LFCSP/TSSOP
AD5121
Single
SPI/I
2
C
LFCSP
AD5141
Single
SPI/I2C
LFCSP
1 Two potentiometers and two rheostats.
AD5122A/AD5142A Data Sheet
Rev. B | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—AD5122A ....................................... 3
Electrical Characteristics—AD5142A ....................................... 6
Interface Timing Specifications .................................................. 9
Shift Register and Timing Diagrams ....................................... 10
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 14
Test Circuits ..................................................................................... 19
Theory of Operation ...................................................................... 20
RDAC Register and EEPROM .................................................. 20
Input Shift Register .................................................................... 20
I2C Serial Data Interface ............................................................ 20
I2C Address .................................................................................. 20
Advanced Control Modes ......................................................... 22
EEPROM or RDAC Register Protection ................................. 23
INDEP Pin ................................................................................... 23
RDAC Architecture .................................................................... 26
Programming the Variable Resistor ......................................... 26
Programming the Potentiometer Divider ............................... 27
Terminal Voltage Operating Range ......................................... 27
Power-Up Sequence ................................................................... 27
Layout and Power Supply Biasing ............................................ 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 29
Automotive Products ................................................................. 29
REVISION HISTORY
6/2017—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Logic Supply Current Parameter, Table 2 ................. 4
Added Note 12 to Data Retention Parameter, Table 2;
Renumbered Sequentially ................................................................ 5
Changes to Logic Supply Current Parameter, Table 3 ................. 7
Added Note 12 to Data Retention Parameter, Table 3;
Renumbered Sequentially ................................................................ 8
Changes to Table 5 .......................................................................... 11
Changes to Figure 4 and Table 7 ................................................... 12
Changes to Figure 14 ...................................................................... 15
Added Figure 15; Renumbered Sequentially .............................. 15
Changes to Figure 18 ...................................................................... 16
Change to Linear Gain Setting Mode .......................................... 22
Changes to EEPROM or RDAC Register Protection Section ... 23
Changes to RDAC Architecture Section ..................................... 26
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 29
Added Automotive Products Section .......................................... 29
12/2012—Rev. 0 to Rev. A
Changes to Table 9 .......................................................................... 20
10/2012—Revision 0: Initial Version
Data Sheet AD5122A/AD5142A
Rev. B | Page 3 of 32
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5122A
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution N 7 Bits
Resistor Integral Nonlinearity
2
R-INL R
AB
= 10 kΩ
V
DD
≥ 2.7 V −1 ±0.1 +1 LSB
V
DD
< 2.7 V −2.5 ±1 +2.5 LSB
R
AB
= 100 kΩ
V
DD
≥ 2.7 V −0.5 ±0.1 +0.5 LSB
V
DD
< 2.7 V −1 ±0.25 +1 LSB
Resistor Differential Nonlinearity
2
R-DNL −0.5 ±0.1 +0.5 LSB
Nominal Resistor Tolerance ΔR
AB
/R
AB
−8 ±1 +8 %
Resistance Temperature Coefficient3 (ΔR
AB
/R
AB
)/ΔT × 106 Code = full scale 35 ppm/°C
Wiper Resistance
3
RW
Code = zero scale
RAB = 10 kΩ
55
125
Ω
R
AB
= 100 kΩ 130 400 Ω
Bottom Scale or Top Scale R
BS
or R
TS
R
AB
= 10 kΩ 40 80 Ω
R
AB
= 100 kΩ 60 230 Ω
Nominal Resistance Match R
AB1
/R
AB2
Code = 0xFF −1 ±0.2 +1 %
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4 INL
R
AB
= 10 kΩ −0.5 ±0.1 +0.5 LSB
R
AB
= 100 kΩ −0.25 ±0.1 +0.25 LSB
Differential Nonlinearity4 DNL −0.25 ±0.1 +0.25 LSB
Full-Scale Error V
WFSE
R
AB
= 10 kΩ −1.5 −0.1 LSB
R
AB
= 100 kΩ −0.5 ±0.1 +0.5 LSB
Zero-Scale Error V
WZSE
R
AB
= 10 kΩ 1 1.5 LSB
R
AB
= 100 kΩ 0.25 0.5 LSB
Voltage Divider Temperature
Coefficient3
(ΔVW/VW)/ΔT × 106 Code = half scale ±5 ppm/°C
AD5122A/AD5142A Data Sheet
Rev. B | Page 4 of 32
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
RESISTOR TERMINALS
Maximum Continuous Current I
A
, I
B
, and I
W
R
AB
= 10 kΩ −6 +6 mA
R
AB
= 100 kΩ −1.5 +1.5 mA
Terminal Voltage Range5
VSS
VDD
V
Capacitance A, Capacitance B
3
CA, CB f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ 25 pF
R
AB
= 100 kΩ 12 pF
Capacitance W3 CW f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ 12 pF
R
AB
= 100 kΩ 5 pF
Common-Mode Leakage Current3 V
A
= V
W
= V
B
−500 ±15 +500 nA
DIGITAL INPUTS
Input Logic
3
High V
INH
V
LOGIC
= 1.8 V to 2.3 V 0.8 × V
LOGIC
V
V
LOGIC
= 2.3 V to 5.5 V 0.7 × V
LOGIC
V
Low
VINL
0.2 × VLOGIC
V
Input Hysteresis
3
V
HYST
0.1 × V
LOGIC
V
Input Current
3
I
IN
±1 µA
Input Capacitance3 C
IN
5 pF
DIGITAL OUTPUTS
Output High Voltage
3
V
OH
R
PULL-UP
= 2.2 kΩ to V
LOGIC
V
LOGIC
V
Output Low Voltage3 V
OL
I
SINK
= 3 mA 0.4 V
I
SINK
= 6 mA, V
LOGIC
> 2.3 V 0.6 V
Three-State Leakage Current −1 +1 µA
Three-State Output Capacitance 2 pF
POWER SUPPLIES
Single-Supply Power Range V
SS
= GND 2.3 5.5 V
Dual-Supply Power Range ±2.25 ±2.75 V
Logic Supply Range Single supply, V
SS
= GND 1.8 V
DD
V
Dual supply, V
SS
< GND 2.25 V
DD
V
Positive Supply Current I
DD
V
IH
= V
LOGIC
or V
IL
= GND
VDD = 5.5 V
0.7
5.5
µA
V
DD
= 2.3 V 400 nA
Negative Supply Current I
SS
V
IH
= V
LOGIC
or V
IL
= GND −5.5 −0.7 µA
EEPROM Store Current
3, 6
I
DD_EEPROM_STORE
V
IH
= V
LOGIC
or V
IL
= GND 2 mA
EEPROM Read Current3, 7 I
DD_EEPROM_READ
V
IH
= V
LOGIC
or V
IL
= GND 320 µA
Logic Supply Current I
LOGIC
V
IH
= V
LOGIC
or V
IL
= GND 0.05 1.4 µA
Power Dissipation8 P
DISS
V
IH
= V
LOGIC
or V
IL
= GND 3.5 µW
Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = VDD ± 10%,
code = full scale
−66 −60 dB
Data Sheet AD5122A/AD5142A
Rev. B | Page 5 of 32
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS
9
Bandwidth BW −3 dB
R
AB
= 10 kΩ 3 MHz
R
AB
= 100 kΩ 0.43 MHz
Total Harmonic Distortion
THD
V
DD
/V
SS
= ±2.5 V, V
A
= 1 V rms,
V
B
= 0 V, f = 1 kHz
R
AB
= 10 kΩ −80 dB
R
AB
= 100 kΩ −90 dB
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 10 kHz
R
AB
= 10 kΩ 7 nV/√Hz
R
AB
= 100 kΩ 20 nV/√Hz
VW Settling Time tS VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
RAB = 10 kΩ
2
µs
R
AB
= 100 kΩ 12 µs
Crosstalk (C
W1
/C
W2
) C
T
R
AB
= 10 kΩ 10 nV-sec
R
AB
= 100 kΩ 25 nV-sec
Analog Crosstalk C
TA
−90 dB
Endurance10 T
A
= 25°C 1 Mcycles
100 kcycles
Data Retention
11, 12
50 Years
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years.
AD5122A/AD5142A Data Sheet
Rev. B | Page 6 of 32
ELECTRICAL CHARACTERISTICS—AD5142A
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution N 8 Bits
Resistor Integral Nonlinearity2 R-INL R
AB
= 10 kΩ
VDD ≥ 2.7 V
−2
±0.2
+2
LSB
V
DD
< 2.7 V −5 ±1.5 +5 LSB
R
AB
= 100 kΩ
V
DD
≥ 2.7 V −1 ±0.1 +1 LSB
V
DD
< 2.7 V −2 ±0.5 +2 LSB
Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.2 +0.5 LSB
Nominal Resistor Tolerance ΔR
AB
/R
AB
−8 ±1 +8 %
Resistance Temperature Coefficient
3
(ΔR
AB
/R
AB
)/ΔT × 10
6
Code = full scale 35 ppm/°C
Wiper Resistance3 R
W
Code = zero scale
R
AB
= 10 kΩ 55 125 Ω
R
AB
= 100 kΩ 130 400 Ω
Bottom Scale or Top Scale R
BS
or R
TS
R
AB
= 10 kΩ 40 80 Ω
R
AB
= 100 kΩ 60 230 Ω
Nominal Resistance Match R
AB1
/R
AB2
Code = 0xFF −1 ±0.2 +1 %
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4 INL
R
AB
= 10 kΩ −1 ±0.2 +1 LSB
R
AB
= 100 kΩ −0.5 ±0.1 +0.5 LSB
Differential Nonlinearity
4
DNL −0.5 ±0.2 +0.5 LSB
Full-Scale Error V
WFSE
R
AB
= 10 kΩ −2.5 −0.1 LSB
R
AB
= 100 kΩ −1 ±0.2 +1 LSB
Zero-Scale Error V
WZSE
R
AB
= 10 kΩ 1.2 3 LSB
R
AB
= 100 kΩ 0.5 1 LSB
Voltage Divider Temperature
Coefficient3
(ΔVW/VW)/ΔT × 10
6
Code = half scale ±5 ppm/°C
Data Sheet AD5122A/AD5142A
Rev. B | Page 7 of 32
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
RESISTOR TERMINALS
Maximum Continuous Current I
A
, I
B
, and I
W
R
AB
= 10 kΩ −6 +6 mA
R
AB
= 100 kΩ −1.5 +1.5 mA
Terminal Voltage Range5
VSS
VDD
V
Capacitance A, Capacitance B
3
CA, CB f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ 25 pF
R
AB
= 100 kΩ 12 pF
Capacitance W3 CW f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ 12 pF
R
AB
= 100 kΩ 5 pF
Common-Mode Leakage Current3 V
A
= V
W
= V
B
−500 ±15 +500 nA
DIGITAL INPUTS
Input Logic
3
High V
INH
V
LOGIC
= 1.8 V to 2.3 V 0.8 × V
LOGIC
V
V
LOGIC
= 2.3 V to 5.5 V 0.7 × V
LOGIC
V
Low
VINL
0.2 × VLOGIC
V
Input Hysteresis
3
V
HYST
0.1 × V
LOGIC
V
Input Current
3
I
IN
±1 µA
Input Capacitance3 C
IN
5 pF
DIGITAL OUTPUTS
Output High Voltage
3
V
OH
R
PULL-UP
= 2.2 kΩ to V
LOGIC
V
LOGIC
V
Output Low Voltage3 V
OL
I
SINK
= 3 mA 0.4 V
I
SINK
= 6 mA, V
LOGIC
> 2.3 V 0.6 V
Three-State Leakage Current −1 +1 µA
Three-State Output Capacitance 2 pF
POWER SUPPLIES
Single-Supply Power Range V
SS
= GND 2.3 5.5 V
Dual-Supply Power Range ±2.25 ±2.75 V
Logic Supply Range Single supply, V
SS
= GND 1.8 V
DD
V
Dual supply, V
SS
< GND 2.25 V
DD
V
Positive Supply Current I
DD
V
IH
= V
LOGIC
or V
IL
= GND
VDD = 5.5 V
0.7
5.5
µA
V
DD
= 2.3 V 400 nA
Negative Supply Current I
SS
V
IH
= V
LOGIC
or V
IL
= GND −5.5 −0.7 µA
EEPROM Store Current
3, 6
I
DD_EEPROM_STORE
V
IH
= V
LOGIC
or V
IL
= GND 2 mA
EEPROM Read Current3, 7 I
DD_EEPROM_READ
V
IH
= V
LOGIC
or V
IL
= GND 320 µA
Logic Supply Current I
LOGIC
V
IH
= V
LOGIC
or V
IL
= GND 0.05 1.4 µA
Power Dissipation8 P
DISS
V
IH
= V
LOGIC
or V
IL
= GND 3.5 µW
Power Supply Rejection Ratio PSR ∆VDD/∆VSS = VDD ± 10%,
code = full scale
−66 −60 dB
AD5122A/AD5142A Data Sheet
Rev. B | Page 8 of 32
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS
9
Bandwidth BW −3 dB
R
AB
= 10 kΩ 3 MHz
R
AB
= 100 kΩ 0.43 MHz
Total Harmonic Distortion
THD
V
DD
/V
SS
= ±2.5 V, V
A
= 1 V rms,
V
B
= 0 V, f = 1 kHz
R
AB
= 10 kΩ −80 dB
R
AB
= 100 kΩ −90 dB
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 10 kHz
R
AB
= 10 kΩ 7 nV/√Hz
R
AB
= 100 kΩ 20 nV/√Hz
VW Settling Time tS VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
RAB = 10 kΩ
2
µs
R
AB
= 100 kΩ 12 µs
Crosstalk (C
W1
/C
W2
) C
T
R
AB
= 10 kΩ 10 nV-sec
R
AB
= 100 kΩ 25 nV-sec
Analog Crosstalk C
TA
−90 dB
Endurance10 T
A
= 25°C 1 Mcycles
100 kcycles
Data Retention
11, 12
50 Years
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years.
Data Sheet AD5122A/AD5142A
Rev. B | Page 9 of 32
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
1
Test Conditions/Comments Min Typ Max Unit Description
f
SCL2
Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
t
1
Standard mode 4.0 µs SCL high time, t
HIGH
Fast mode 0.6 µs
t
2
Standard mode 4.7 µs SCL low time, t
LOW
Fast mode 1.3 µs
t
3
Standard mode 250 ns Data setup time, t
SU; DAT
Fast mode 100 ns
t
4
Standard mode 0 3.45 µs Data hold time, t
HD; DAT
Fast mode 0 0.9 µs
t
5
Standard mode 4.7 µs Setup time for a repeated start condition, t
SU; STA
Fast mode 0.6 µs
t
6
Standard mode 4 µs Hold time (repeated) for a start condition, t
HD; STA
Fast mode 0.6 µs
t
7
Standard mode 4.7 µs Bus free time between a stop and a start condition, t
BUF
Fast mode
1.3
µs
t
8
Standard mode 4 µs Setup time for a stop condition, t
SU; STO
Fast mode 0.6 µs
t
9
Standard mode 1000 ns Rise time of SDA signal, t
RDA
Fast mode 20 + 0.1 C
L
300 ns
t
10
Standard mode 300 ns Fall time of SDA signal, t
FDA
Fast mode 20 + 0.1 C
L
300 ns
t
11
Standard mode 1000 ns Rise time of SCL signal, t
RCL
Fast mode 20 + 0.1 C
L
300 ns
t11A Standard mode 1000 ns Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, t
RCL1
(not shown in Figure 3)
Fast mode 20 + 0.1 C
L
300 ns
t12
Standard mode
300
ns
Fall time of SCL signal, tFCL
Fast mode 20 + 0.1 C
L
300 ns
t
SP3
Fast mode 0 50 ns Pulse width of suppressed spike (not shown in Figure 3)
tRESET 0.1 10 µs RESET low time (not shown in Figure 3)
t
EEPROM_PROGRAM4
15 50 ms Memory program time (not shown in Figure 3)
t
EEPROM_READBACK
7 30 µs Memory readback time (not shown in Figure 3)
t
POWER_UP
5 75 µs Power-on EEPROM restore time (not shown in Figure 3)
t
RESET
30 µs Reset EEPROM restore time (not shown in Figure 3)
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4 The EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
5 Maximum time after VDD − VSS is equal to 2.3 V.
AD5122A/AD5142A Data Sheet
Rev. B | Page 10 of 32
SHIFT REGISTER AND TIMING DIAGRAMS
DATA BITS
DB8DB15 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS BITS
A0A1
A2C2 C1 C0 A3C3
CONTROL BITS
DB7
10939-002
Figure 2. Input Shift Register Contents
t7
t6
t2
t4
t11 t12 t6
t5t10
t1
SCL
S
DA
PS S P
t3
t8
t
9
10939-003
Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)
Data Sheet AD5122A/AD5142A
Rev. B | Page 11 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
V
DD
to GND −0.3 V to +7.0 V
V
SS
to GND +0.3 V to −7.0 V
V
DD
to V
SS
7 V
VLOGIC to GND −0.3 V to VDD + 0.3 V or
+7.0 V (whichever is less)
VA, VW, VB to GND VSS − 0.3 V, VDD + 0.3 V
+7.0 V (whichever is less)
I
A
, I
W
, I
B
Pulsed
1
Frequency > 10 kHz
R
AW
= 10 kΩ ±6 mA/d2
R
AW
= 100 kΩ ±1.5 mA/d2
Frequency ≤ 10 kHz
R
AW
= 10 kΩ ±6 mA/√d
2
R
AW
= 100 kΩ ±1.5 mA/√d2
Digital Inputs −0.3 V to VLOGIC + 0.3 V or
+7 V (whichever is less)
Operating Temperature Range, T
A
3 −40°C to +125°C
Maximum Junction Temperature,
T
J
Maximum
150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (T
J
max − T
A
)/θ
JA
FICDM 1.5 kV
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 d = pulse duty factor.
3 Includes programming of EEPROM memory.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 6. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
16-Lead LFCSP 89.51 3 °C/W
16-Lead TSSOP 150.41 27.6 °C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
AD5122A/AD5142A Data Sheet
Rev. B | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
10939-004
GND
A1
W1
B1
SCL
SDA
VLOGIC
VDD
RESET
ADDR0
INDEP
ADDR1
V
SS
A2
W2
B2
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
PIN 1
INDICATOR
NOTES
1. EXPOSED PAD. CONNECT T HE EXPOSED PAD TO THE
POTENTIAL OF THE VSS PIN, OR, ALT E RNATIVELY, L EAVE IT
ELE CTRICALLY UNCONNECTED. I T IS RECOMMENDED THAT
THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THER MAL PERF ORMANCE .
AD5122A/
AD5142A
TOP VI EW
(Not to Scale)
Figure 4. 16-Lead LFCSP Pin Configuration
Table 7. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Ground Pin, Logic Ground Reference.
2 A1 Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
3 W1 Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
4 B1 Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
5 VSS Negative Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
6 A2 Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
7 W2 Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
8 B2 Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
9 VDD Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
10 VLOGIC Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
11 SCL Serial Clock Line.
12 SDA Serial Data Input/Output.
13 ADDR1 Programmable Address (ADDR1) for Multiple Package Decoding.
14 ADDR0 Programmable Address (ADDR0) for Multiple Package Decoding.
15 INDEP Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location.
If INDEP is enabled, it cannot be disabled by the software.
16 RESET Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low.
If this pin is not used, tie RESET to VLOGIC.
EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically
unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced
thermal performance.
Data Sheet AD5122A/AD5142A
Rev. B | Page 13 of 32
1
2
3
4
5
6
7
8
INDEP
A1
W1
B1
RESET
A2
V
SS
GND
16
15
14
13
12
11
10
9
ADDR1
SDA
SCL
V
LOGIC
V
DD
W2
B2
AD5122A/
AD5142A
TOP VIEW
(No t t o Scal e)
ADDR0
10939-005
Figure 5. 16-Lead TSSOP Pin Configuration
Table 8. 16-Lead TSSOP Pin Function Descriptions
Pin No. Mnemonic Description
1 INDEP Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location.
If INDEP is enabled, it cannot be disabled by the software.
2 RESET Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low.
If this pin is not used, tie RESET to VLOGIC.
3 GND Ground Pin, Logic Ground Reference.
4 A1 Terminal A of RDAC1. V
SS
≤ V
A
≤ V
DD
.
5 W1 Wiper Terminal of RDAC1. V
SS
≤ V
W
≤ V
DD
.
6 B1 Terminal B of RDAC1. V
SS
≤ V
B
≤ V
DD
.
7 V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
8 A2 Terminal A of RDAC2. V
SS
≤ V
A
≤ V
DD
.
9 W2 Wiper Terminal of RDAC2. V
SS
≤ V
W
≤ V
DD
.
10 B2 Terminal B of RDAC2. V
SS
≤ V
B
≤ V
DD
.
11 V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
12 V
LOGIC
Logic Power Supply; 1.8 V to V
DD
. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
13 SCL Serial Clock Line.
14 SDA Serial Data Input/Output.
15 ADDR1 Programmable Address (ADDR1) for Multiple Package Decoding.
16 ADDR0 Programmable Address (ADDR0) for Multiple Package Decoding.
AD5122A/AD5142A Data Sheet
Rev. B | Page 14 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0100 200
R-INL (LSB)
CODE ( Decimal )
10kΩ, +125°C
10kΩ, + 25°C
10kΩ, –40°C
100kΩ, +125° C
100kΩ, +25° C
100kΩ, –40°C
10939-006
Figure 6. R-INL vs. Code (AD5142A)
R-INL (LSB)
CODE ( Decimal )
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
050 100
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10939-007
Figure 7. R-INL vs. Code (AD5122A)
0100200
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
INL (LSB)
CODE (Decimal)
10939-008
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
Figure 8. INL vs. Code (AD5142A)
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0100 200
R-DNL (LSB)
CODE ( Decimal )
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10939-009
Figure 9. R-DNL vs. Code (AD5142A)
CODE ( Decimal )
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
050 100
R-DNL (LSB)
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10939-010
Figure 10. R-DNL vs. Code (AD5122A)
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
DNL (LSB)
CODE (Decimal)
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10939-011
0100200
Figure 11. DNL vs. Code (AD5142A)
Data Sheet AD5122A/AD5142A
Rev. B | Page 15 of 32
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
050100
INL (LSB)
CODE (Decimal)
10kΩ,–40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ,–40°C
100kΩ, +25°C
100kΩ, +125°C
10939-012
Figure 12. INL vs. Code (AD5122A)
10939-013
AD5122A
AD5142A
CODE (Decimal)
0 50 100 150 200 255
0 255075100127
–50
0
50
100
150
200
250
300
350
400
450
POTENTIOMETER MODE TEMPERATURE
COEFFICIENT (ppm/°C)
100kΩ
10kΩ
Figure 13. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106)
vs. Code
800
0
100
200
300
400
500
600
700
–40 –20 120100806040200
I
DD
(nA)
TEMPERATURE (°C)
10939-014
V
DD
= 2.3V
V
DD
= 3.3V
V
DD
= 5.5V
V
DD
= V
LOGIC
V
SS
= GND
Figure 14. IDD vs. Temperature
1000
900
800
0
100
200
300
400
500
600
700
–40 –20 120100806040200
I
LOGIC
(nA)
TEMPERATURE (°C)
10939-160
V
LOGIC
= 2.3V
V
LOGIC
= 3.3V
V
LOGIC
= 5.5V
V
DD
= V
LOGIC
V
SS
= GND
Figure 15. ILOGIC vs. Temperature
–0.14
–0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
050100
DNL (LSB)
CODE (Decimal)
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10939-015
Figure 16. DNL vs. Code (AD5122A)
–50
0
50
100
150
200
250
300
350
400
450
RHEOSTAT MODE TEMPER
A
TU
R
E
COEFFICIENT (ppm/°C)
10kΩ
100kΩ
10939-016
AD5122A
AD5142A
CODE (Decimal)
050100150200255
0 255075100127
Figure 17. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106)
vs. Code
AD5122A/AD5142A Data Sheet
Rev. B | Page 16 of 32
10939-017
0
0.2
0.4
0.6
0.8
1.0
1.2
012345
I
LOGIC
CURRENT
(
µA)
DIGITAL INPUT VOLTAGE (V)
V
LOGIC
= 1.8V
V
LOGIC
= 2.3V
V
LOGIC
= 3.3V
V
LOGIC
= 5V
V
LOGIC
= 5.5V
Figure 18. ILOGIC Current vs. Digital Input Voltage
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
AD5142A (AD5122A)
0x80, (0x40)
0x40, (0x20)
0x20, (0x10)
0x10, (0x08)
0x8, (0x04)
0x4, (0x02)
0x2, (0x01)
0x1, (0x00)
0x00
10939-018
Figure 19. 10 kΩ Gain vs. Frequency and Code
–100
–90
–80
–70
–60
–50
–
40
20 200 2k 20k 200k
THD + N (dB)
FREQUENCY (Hz)
10k
100k
VDD/VSS =±2.5V
VA=1Vrms
VB= GND
CODE = HALF SCALE
NOISE FILTER = 22kHz
10939-019
Figure 20. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
–100
–80
–60
–40
–20
0
20
10 100 1k 10k 100k 1M 10M
PHASE (Degrees)
FREQUENCY (Hz)
QUARTER SCALE
MIDSCALE
FULL-SCALE
V
DD
/V
SS
= ±2.5V
R
AB
= 10k
10939-020
Figure 21. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
GAIN (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
0x80, (0x40)
0x40, (0x20)
0x20, (0x10)
0x10, (0x08)
0x8, (0x04)
0x4, (0x02)
0x2, (0x01)
0x1, (0x00)
0x00
AD5142A (AD5122A)
10939-021
Figure 22. 100 kΩ Gain vs. Frequency and Code
10k
100k
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.001 0.01 0.1 1
THD + N (dB)
VOLTAGE(Vrms)
V
DD
/V
SS
=±2.5V
f
IN
=1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
10939-022
Figure 23. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
Data Sheet AD5122A/AD5142A
Rev. B | Page 17 of 32
–80
–90
–70
–60
–50
–40
–30
–20
–10
0
10
10 100 1k 10k 100k 1M
PHASE (Degrees)
FREQUENCY (Hz)
QUARTER SCALE
MIDSCALE
FULL-SCALE V
DD
/V
SS
= ±2. 5V
R
AB
= 100kΩ
10939-023
Figure 24. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
0
100
200
300
400
500
600
012345
WIPER ON RESISTANCE (Ω)
VOLTAGE (V)
100kΩ, V
DD
= 2.3V
100kΩ, V
DD
= 2.7V
100kΩ, V
DD
= 3V
100kΩ, V
DD
= 3.6V
100kΩ, V
DD
= 5V
100kΩ, V
DD
= 5.5V
10kΩ, V
DD
= 2.3V
10kΩ, V
DD
= 2.7V
10kΩ, V
DD
= 3V
10kΩ, V
DD
= 3.6V
10kΩ, V
DD
= 5V
10kΩ, V
DD
= 5.5V
10939-024
Figure 25. Incremental Wiper On Resistance vs. VDD
0
1
2
3
4
5
6
7
8
9
10
020 40 60 80 100 120
010 20 30 40 50 60
BANDWIDTH ( M Hz )
CODE ( Decimal )
AD5142A
AD5122A
10kΩ + 0pF
10kΩ + 75pF
10kΩ + 150pF
10kΩ + 250pF
100kΩ + 0p F
100kΩ + 75p F
100kΩ + 150p F
100kΩ + 250p F
10939-025
Figure 26. Maximum Bandwidth vs. Code and Net Capacitance
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0510 15
RELATIVE VOLTAGE (V)
TIME (µs)
0x80 TO 0x7F, 100kΩ
0x80 TO 0x7F, 10kΩ
10939-026
Figure 27. Maximum Transition Glitch
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.0005
0.0010
0.0015
0.0020
0.0025
–400–500–600 –300 –200 –100 0 100 200 300 400 500 600
CUMUL ATIV E P ROBABI LI TY
PROBABILITY DENSITY
RESISTOR DRIFT (ppm)
10939-027
Figure 28. Resistor Lifetime Drift
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
10kΩ
100kΩV
DD
= 5V ±10% AC
V
SS
= GND, V
A
= 4V, V
B
= GND
CODE = MIDSCALE
10939-028
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency
AD5122A/AD5142A Data Sheet
Rev. B | Page 18 of 32
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0500 1000 1500 2000
RELATIVE VOLTAGE (V)
TIME ( ns)
10939-029
Figure 30. Digital Feedthrough
–120
–100
–80
–60
–40
–20
0
10 100 1k 10k 100k 1M 10M
GAI N (dB)
FREQUECNY (Hz)
10kΩ
100kΩ
10939-030
SHUT DO WN MODE E NABLED
Figure 31. Shutdown Isolation vs. Frequency
0
1
2
3
4
5
6
7
050 100 150 200 250
025 50 75 100 125
AD5122A
THEORETICAL I
MAX
(mA)
AD5142A
100kΩ
10kΩ
CODE ( Decimal )
10939-031
Figure 32. Theoretical Maximum Current vs. Code
Data Sheet AD5122A/AD5142A
Rev. B | Page 19 of 32
TEST CIRCUITS
Figure 33 to Figure 37 define the test conditions used in the Specifications section.
AW
B
NC
IW
DUT
VMS
NC = NO CONNECT
10939-032
Figure 33. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
AW
B
DUT
V
MS
V+
V+ = V
DD
1LSB = V + /2
N
10939-033
Figure 34. Potentiometer Divider Nonlinearity Error (INL, DNL)
AW
NC
B
DUTI
W
= V
DD
/R
NOMINAL
V
MS1
V
W
RW= VMS1/IW
NC = NO CONNECT
10939-034
Figure 35. Wiper Resistance
AW
BV
MS
V+ = V
DD
±10%
PSRR (dB) = 20 LO G V
MS
Δ
V
DD
()
~
V
A
V
DD
Δ
V
MS%
Δ
V
DD%
PSS (%/%) =
V+
Δ
10939-035
Figure 36. Power Supply Sensitivity and
Power Supply Rejection Ratio (PSS, PSRR)
+
–
DUT CODE = 0x00
0.1V
V
SS
TO V
DD
R
SW
=0.1V
I
SW
I
SW
W
B
A = NC
10939-036
Figure 37. Incremental On Resistance
AD5122A/AD5142A Data Sheet
Rev. B | Page 20 of 32
THEORY OF OPERATION
The AD5122A/AD5142A digital programmable potentiometers
are designed to operate as true variable resistors for analog signals
within the terminal voltage range of VSS < VTERM < VDD. The resistor
wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input
shift register) can be used to preload the RDAC register data.
The RDAC register can be programmed with any position setting
using the I2C interface. When a desirable wiper position is found,
this value can be stored in the EEPROM memory. Thereafter,
the wiper position is always restored to that position for subsequent
power-ups. The storing of EEPROM data takes approximately
15 ms; during this time, the device is locked and does not
acknowledge any new command, preventing any changes from
taking place.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5142A, 256 taps), the wiper is connected
to half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 10).
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 10). Thereafter, the RDAC register
always sets at that position for any future on-off-on power
supply sequence. It is possible to read back data saved into the
EEPROM with Command 3 (see Table 10).
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 16).
INPUT SHIFT REGISTER
For the AD5122A/AD5142A, the input shift register is 16 bits
wide, as shown in Figure 2. The 16-bit word consists of four
control bits, followed by four address bits and by eight data bits.
If the AD5122A RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 10 and
Table 16.
I2C SERIAL DATA INTERFACE
The AD5122A/AD5142A have 2-wire, I2C-compatible serial
interfaces. The device can be connected to an I2C bus as a slave
device, under the control of a master device. See Figure 3 for a
timing diagram of a typical write sequence.
The AD5122A/AD5142A supports standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for 10-bit
addressing and general call addressing.
The 2-wire serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/W bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
If the R/W bit is set high, the master reads from the slave
device. However, if the R/W bit is set low, the master writes
to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
I2C ADDRESS
The facility to make hardwired changes to ADDR allows the
user to incorporate up to nine of these devices on one bus as
outlined in Table 9.
Table 9. Device Address Selection
ADDR0 Pin ADDR1 Pin 7-Bit I2C Device Address
V
LOGIC
V
LOGIC
0100000
No connect1 V
LOGIC
0100010
GND V
LOGIC
0100011
V
LOGIC
No connect
1
0101000
No connect1 No connect1 0101010
GND No connect1 0101011
VLOGIC
GND
0101100
No connect1
GND
0101110
GND GND 0101111
1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V).
Data Sheet AD5122A/AD5142A
Rev. B | Page 21 of 32
Table 10. Reduced Commands Operation Truth Table
Command
Number
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1 Data Bits[DB7:DB0]1
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing
1 0 0 0 1 0 0 0 A0 D7 D6 D5 D4 D3 D2 D1 D0
Write contents of serial register
data to RDAC
2 0 0 1 0 0 0 0 A0 D7 D6 D5 D4 D3 D2 D1 D0
Write contents of serial register
data to input shift register
3
0
0
1
1
0
0
A1
A0
X
X
X
X
X
X
D1
D0
Read back contents
D1 D0 Data
0 1 EEPROM
1 1 RDAC
9 0 1 1 1 0 0 0 A0 X X X X X X X 1 Copy RDAC register to EEPROM
10
0
1
1
1
0
0
0
A0
X
X
X
X
X
X
X
0
Copy EEPROM into RDAC
14 1 0 1 1 X X X X X X X X X X X X Software reset
15 1 1 0 0 A3 0 0 A0 X X X X X X X D0 Software shutdown
D0
Condition
0 Normal mode
1
Shutdown mode
1 X = don’t care.
Table 11. Reduced Address Bits Table
A3 A2 A1 A0 Channel Stored Channel Memory
1 X1 X1 X1 All channels Not applicable
0 0 0 0 RDAC1 RDAC1
0 0 0 1 RDAC2 Not applicable
0 0 1 0 Not applicable RDAC2
1 X = don’t care.
AD5122A/AD5142A Data Sheet
Rev. B | Page 22 of 32
ADVANCED CONTROL MODES
The AD5122A/AD5142A digital potentiometers include a set
of user programming features to address the wide number of
applications for these universal adjustment devices (see Table 16
and Table 18).
Key programming features include the following:
• Input register
• Linear gain setting mode
• A low wiper resistance feature
• Linear increment and decrement instructions
• ±6 dB increment and decrement instructions
• Burst mode
• Reset
• Shutdown mode
Input Register
The AD5122A/AD5142A include one input register per RDAC
register. These registers allow preloading of the value for the
associated RDAC register. These registers can be written to using
Command 2 and read back from using Command 3 (see Table 16).
This feature allows a synchronous update of one or both RDAC
registers at the same time.
The transfer from the input register to the RDAC register is
done synchronously by Command 8 (see Table 16).
If new data is loaded in an RDAC register, this RDAC register
automatically overwrites the associated input register.
Linear Gain Setting Mode
The proprietary architecture of the AD5122A/AD5142A allows
the independent control of each string resistor, RAW, and RWB. To
enable linear gain setting mode, use Command 16 (see Table 16)
to set Bit D2 of the control register (see Table 18).
This mode of operation can control the potentiometer as two
independent rheostats connected at a single point, W terminal,
as opposed to potentiometer mode where each resistor is
complementary, RAW = RAB − RWB.
This mode enables a second input and an RDAC register per
channel, as shown in Table 16; however, the actual RDAC
contents remain unchanged. The same operations are valid for
potentiometer and linear gain setting mode.
If the INDEP pin is pulled high, the device powers up in linear
gain setting mode and loads the values stored in the associated
memory locations for each channel (see Table 17). The INDEP pin
and the D2 bit are connected internally to a logic OR gate; if one or
both are set to 1, the parts cannot operate in potentiometer mode.
Low Wiper Resistance Feature
The AD5122A/AD5142A include two commands to reduce the
wiper resistance between the terminals when the device achieves
full scale or zero scale. These extra positions are called bottom
scale, BS, and top scale, TS. The resistance between Termina l A
and Terminal W at top scale is specified as RTS. Similarly, the
bottom scale resistance between Terminal B and Terminal W is
specified as RBS.
The contents of the RDAC registers are unchanged by entering
in these positions. There are three ways to exit from top scale
and bottom scale: by using Command 12 or Command 13
(see Table 16); by loading new data in an RDAC register, which
includes increment/decrement operations; or by entering
shutdown mode, Command 15 (see Table 16).
Table 12 and Table 13 show the truth tables for the top scale
position and the bottom scale position, respectively, when
potentiometer or linear gain setting mode is enabled.
Table 12. Top Scale Truth Table
Linear Gain Setting Mode
Potentiometer Mode
R
AW
R
WB
R
AW
R
WB
R
AB
R
AB
R
TS
R
AB
Table 13. Bottom Scale Truth Table
Linear Gain Setting Mode Potentiometer Mode
R
AW
R
WB
R
AW
R
WB
R
TS
R
BS
R
AB
R
BS
Linear Increment and Decrement Instructions
The increment and decrement commands (Command 4 and
Command 5 in Table 16) are useful for linear step adjustment
applications. These commands simplify microcontroller software
coding by allowing the controller to send an increment or
decrement command to the device. The adjustment can be
individual or in a ganged potentiometer arrangement, where
all wiper positions are changed at the same time.
For an increment command, executing Command 4 automatically
moves the wiper to the next RDAC position. This command can
be executed in a single channel or in multiple channels.
Data Sheet AD5122A/AD5142A
Rev. B | Page 23 of 32
±6 dB Increment and Decrement Instructions
Two programming instructions produce logarithmic taper
increment or decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where all RDAC register positions are changed
simultaneously. The +6 dB increment is activated by Command 6,
and the −6 dB decrement is activated by Command 7 (see Table 16).
For example, starting with the zero-scale position and executing
Command 6 ten times moves the wiper in 6 dB steps to the full-
scale position. When the wiper position is near the maximum
setting, the last 6 dB increment instruction causes the wiper to go
to the full-scale position (see Table 14).
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by −6 dB halves the register value. Internally, the
AD5122A/AD5142A use shift registers to shift the bits left and
right to achieve a ±6 dB increment or decrement. These functions
are useful for various audio/video level adjustments, especially for
white LED brightness settings in which human visual responses
are more sensitive to large adjustments than to small adjustments.
Table 14. Detailed Left Shift and Right Shift Functions for
the ±6 dB Step Increment and Decrement
Left Shift (+6 dB/Step) Right Shift (−6 dB/Step)
0000 0000 1111 1111
0000 0001 0111 1111
0000 0010 0011 1111
0000 0100
0001 1111
0000 1000 0000 1111
0001 0000 0000 0111
0010 0000 0000 0011
0100 0000 0000 0001
1000 0000 0000 0000
1111 1111 0000 0000
Burst Mode
By enabling the burst mode, multiple data bytes can be sent to
the part consecutively. After the command byte, the part
interprets the following consecutive bytes as data bytes for the
command.
A new command can be sent by generating a repeat start or by a
stop and start condition.
The burst mode is activated by setting Bit D3 of the control
register (see Table 18).
Reset
The AD5122A/AD5142A can be reset through software by
executing Command 14 (see Table 16) or through hardware on
the low pulse of the RESET pin. The reset command loads the
RDAC registers with the contents of the EEPROM and takes
approximately 30 µs. The EEPROM is preloaded to midscale at
the factory, and initial power-up is, accordingly, at midscale.
Tie RESET to VLOGIC if the RESET pin is not used.
Shutdown Mode
The AD5122A/AD5142A can be placed in shutdown mode by
executing the software shutdown command, Command 15 (see
Table 16), and setting the LSB (D0) to 1. This feature places the
RDAC in a zero power consumption state where the device
operates in potentiometer mode, Terminal A is open-circuited
and the wiper, Terminal W, is connected to Terminal B; however, a
finite wiper resistance of 40 Ω is present. When the device is
configured in linear gain setting mode, the resistor addressed,
RAW or RWB, is internally placed at high impedance. Table 15
shows the truth table depending on the device operating mode.
The contents of the RDAC register are unchanged by entering
shutdown mode. However, all commands listed in Table 16 are
supported while in shutdown mode. Execute Command 15 (see
Table 16) and set the LSB (D0) to 0 to exit shutdown mode.
Table 15. Truth Table for Shutdown Mode
Linear Gain Setting Mode Potentiometer Mode
R
AW
R
WB
R
AW
R
WB
High impedance High impedance High impedance R
BS
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software. If
these registers are protected by software, set Bit D0 and/or Bit D1
(see Table 18), which protects the RDAC and EEPROM registers
independently.
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
INDEP PIN
If the INDEP pin is pulled high at power-up, the part operates
in linear gain setting mode, loading each string resistor, RAWX and
RWBX, with the value stored into the EEPROM (see Table 17). If
the pin is pulled low, the part powers up in potentiometer mode.
The INDEP pin and the D2 bit are connected internally to a logic
OR gate; if one or both are set to 1, the part cannot operate in
potentiometer mode (see Table 18).
AD5122A/AD5142A Data Sheet
Rev. B | Page 24 of 32
Table 16. Advanced Command Operation Truth Table
Command
Number
Command
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1 Data Bits[DB7:DB0]1
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing
1 0 0 0 1 0 A2 0 A0 D7 D6 D5 D4 D3 D2 D1 D0
Write contents of serial
register data to RDAC
2 0 0 1 0 0 A2 0 A0 D7 D6 D5 D4 D3 D2 D1 D0
Write contents of serial
register data to input
register
3 0 0 1 1 X A2 A1 A0 X X X X X X D1 D0 Read back contents
D1 D0 Data
0 0 Input register
0 1 EEPROM
1 0 Control
register
1 1 RDAC
4
0
1
0
0
A3
A2
0
A0
X
X
X
X
X
X
X
1
Linear RDAC increment
5 0 1 0 0 A3 A2 0 A0 X X X X X X X 0 Linear RDAC decrement
6 0 1 0 1 A3 A2 0 A0 X X X X X X X 1 +6 dB RDAC increment
7 0 1 0 1 A3 A2 0 A0 X X X X X X X 0 −6 dB RDAC decrement
8 0 1 1 0 0 A2 0 A0 X X X X X X X X Copy input register to RDAC
(software LRDAC)
9 0 1 1 1 0 A2 0 A0 X X X X X X X 1 Copy RDAC register to
EEPROM
10 0 1 1 1 0 A2 0 A0 X X X X X X X 0 Copy EEPROM into RDAC
11 1 0 0 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Write contents of serial
register data to EEPROM
12
1
0
0
1
A3
A2
0
A0
1
X
X
X
X
X
X
D0
Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
13
1
0
0
1
A3
A2
0
A0
0
X
X
X
X
X
X
D0
Bottom scale
D0 = 1; enter
D0 = 0; exit
14 1 0 1 1 X X X X X X X X X X X X Software reset
15 1 1 0 0 A3 A2 0 A0 X X X X X X X D0 Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in
shutdown mode
16 1 1 0 1 X X X X X X X X D3 D2 D1 D0 Copy serial register data to
control register
1 X = don’t care.
Table 17. Address Bits
A3 A2 A1 A0
Potentiometer Mode Linear Gain Setting Mode Stored Channel
Memory Input Register RDAC Register Input Register RDAC Register
1 X1 X1 X1 All channels All channels All channels All channels Not applicable
0 0 0 0 RDAC1 RDAC1 R
WB1
R
WB1
RDAC1/R
WB1
0 1 0 0 Not applicable Not applicable R
AW1
R
AW1
Not applicable
0 0 0 1 RDAC2 RDAC2 R
WB2
R
WB2
R
AW1
0 1 0 1 Not applicable Not applicable R
AW2
R
AW2
Not applicable
0 0 1 0 Not applicable Not applicable Not applicable Not applicable RDAC2/R
WB2
0 0 1 1 Not applicable Not applicable Not applicable Not applicable R
AW2
1 X = don’t care.
Data Sheet AD5122A/AD5142A
Rev. B | Page 25 of 32
Table 18. Control Register Bit Descriptions
Bit Name Description
D0 RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
D1 EEPROM program enable
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
D2 Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
D3 Burst mode (I2C only)
0 = disabled (default)
1 = enabled (no disable after stop or repeated start condition)
AD5122A/AD5142A Data Sheet
Rev. B | Page 26 of 32
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
proprietary RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5122A/AD5142A employ
a three-stage segmentation approach, as shown in Figure 38.
The AD5122A/AD5142A wiper switch is designed with the
transmission gate CMOS topology and with the gate voltage
derived from VDD and VSS.
7-BIT/8-BIT
ADDRESS
DECODER
R
L
W
R
L
A
R
H
R
H
R
M
R
M
B
R
M
R
M
R
H
R
H
S
TS
S
BS
10939-037
Figure 38. AD5122A/AD5142A Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In addition, the AD5122A/AD5142A include new positions to
reduce the resistance between terminals. These positions are
called bottom scale and top scale. At bottom scale, the typical
wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ).
At top scale, the resistance between Terminal A and Terminal W
is decreased by 1 LSB, and the total resistance is reduced to
60 Ω (RAB = 100 kΩ).
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
The AD5122A/AD5142A operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be floating, or it can be tied to Terminal W, as shown in Figure 39.
A
W
B
A
W
B
A
W
B
10939-038
Figure 39. Rheostat Mode Configuration
The nomi na l re si st anc e be twe en Ter mina l A a n d Te rmin al B,
RAB, is 10 k or 100 k, and has 128/256 tap points accessed by
the wiper terminal. The 7-bit/8-bit data in the RDAC latch is
decoded to select one of the 128/256 possible wiper settings. The
general equations for determining the digitally programmed
output resistance between Terminal W and Terminal B are
AD5122A:
W
AB
WB RR
D
DR
128
)( From 0x00 to 0x7F (1)
AD5142A:
W
AB
WB RR
D
DR
256
)( From 0x00 to 0xFF (2)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
In potentiometer mode, similar to the mechanical potentiometer,
the resistance between Terminal W and Terminal A also
produces a digitally controlled complementary resistance, RWA .
RWA also gives a maximum of 8% absolute resistance error. RWA
starts at the maximum resistance value and decreases as the data
loaded into the latch increases. The general equations for this
operation are
AD5122A:
W
ABAW RR
D
DR
128
128
)( From 0x00 to 0x7F (3)
AD5142A:
W
ABAW RR
D
DR
256
256
)( From 0x00 to 0xFF (4)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
Data Sheet AD5122A/AD5142A
Rev. B | Page 27 of 32
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
AD5122A:
W
ABAW RR
D
DR
128
)( From 0x00 to 0x7F (5)
AD5142A:
W
ABAW RR
D
DR
256
)( From 0x00 to 0xFF (6)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous
current or to the pulse current specified in Table 5. Otherwise,
degradation or possible destruction of the internal switch
contact can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 40.
W
A
B
V
A
V
OUT
V
B
10939-039
Figure 40. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
B
AB
AW
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( (7)
where:
RWB(D) can be obtained from Equation 1 and Equation 2.
RAW(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE
The AD5122A/AD5142A are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
V
DD
A
W
B
V
SS
10939-040
Figure 41. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 41), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and
VA, VB, and VW. The order of powering VA, VB, VW, and digital
inputs is not important as long as they are powered after VSS,
VDD, and VLOGIC. Regardless of the power-up sequence and the
ramp rates of the power supplies, once VDD is powered, the
power-on preset activates, which restores EEPROM values to
the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 42 illustrates the basic supply bypassing configuration
for the AD5122A/AD5142A.
V
DD
V
LOGIC
V
DD
+
V
SS
C1
0.1µF
C3
10µF
+C2
0.1µF
C4
10µF
V
SS
V
LOGIC
+
C5
0.1µF
C6
10µF
AD5122A/
AD5142A
GND
10939-041
Figure 42. Power Supply Bypassing
AD5122A/AD5142A Data Sheet
Rev. B | Page 28 of 32
OUTLINE DIMENSIONS
0.30
0.23
0.18
1.75
1.60 SQ
1.45
3.10
3.00 SQ
2.90
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
0.50
0.40
0.30
0.05 M AX
0.02 NO M
0.20 REF
0.20 M I N
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS M O-220- WEE D- 6.
PKG-005138
SEATING
PLANE
TOP VIEW
EXPOSED
PAD
02-23-2017-E
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FO R P ROPE R CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM P LIANT T O JEDE C S TANDARDS MO-153- AB
Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Data Sheet AD5122A/AD5142A
Rev. B | Page 29 of 32
ORDERING GUIDE
Model1, 2, 3 R
AB
(kΩ) Resolution Interface Temperature Range Package Description
Package
Option Branding
AD5122ABCPZ10-RL7 10 128 I
2
C −40°C to +125°C 16-Lead LFCSP CP-16-22 DHA
AD5122ABCPZ100-RL7 100 128 I2C −40°C to +125°C 16-Lead LFCSP CP-16-22 DHG
AD5122AWBCPZ10-RL7 10 128 I2C −40°C to +125°C 16-Lead LFCSP CP-16-22 DN1
AD5122ABRUZ10
10
128
I
2
C
−40°C to +125°C
16-lead TSSOP
RU-16
AD5122ABRUZ100
100
128
I2C
−40°C to +125°C
16-lead TSSOP
RU-16
AD5122ABRUZ10-RL7 10 128 I
2
C −40°C to +125°C 16-lead TSSOP RU-16
AD5122ABRUZ100-RL7 100 128 I
2
C −40°C to +125°C 16-lead TSSOP RU-16
AD5142ABCPZ10-RL7 10 256 I
2
C −40°C to +125°C 16-Lead LFCSP CP-16-22 DH7
AD5142ABCPZ100-RL7 100 256 I
2
C −40°C to +125°C 16-Lead LFCSP CP-16-22 DH4
AD5142AWBCPZ10-RL7 10 256 I
2
C −40°C to +125°C 16-Lead LFCSP CP-16-22 DMZ
AD5142ABRUZ10 10 256 I2C −40°C to +125°C 16-lead TSSOP RU-16
AD5142ABRUZ100 100 256 I2C −40°C to +125°C 16-lead TSSOP RU-16
AD5142ABRUZ10-RL7
10
256
I2C
−40°C to +125°C
16-lead TSSOP
RU-16
AD5142ABRUZ100-RL7 100 256 I
2
C −40°C to +125°C 16-lead TSSOP RU-16
EVAL-AD5142ADBZ
Evaluation Board
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options.
3 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD5122AW/AD5142AW models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
AD5122A/AD5142A Data Sheet
Rev. B | Page 30 of 32
NOTES
Data Sheet AD5122A/AD5142A
Rev. B | Page 31 of 32
NOTES
AD5122A/AD5142A Data Sheet
Rev. B | Page 32 of 32
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
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