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FEATURES
DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
S0
1DE
S1
2A
2B
GND
VCC
VCC
1Y
1Z
2DE
2Z
2Y
GND
logic diagram (positive logic)
_
+
_
+
1A 1Y
1B
1DE
2DE
S0
S1
2A
2B
1Z
2Y
2Z
0
1
0
1
2
1
4
12
3
5
6
7
14
13
10
11
S1
0
0
1
1
S0
0
1
0
1
1Y/1Z
1A/1B
2A/2B
1A/1B
2A/2B
2Y/2Z
1A/1B
2A/2B
2A/2B
1A/1B
Splitter
Splitter
Router
Router
INPUT OUTPUT FUNCTION
MUX TRUTH TABLE
SN65LVDS22D and SN65LVDS22PW (Marked as LVDS22)
SN65LVDM22D and SN65LVDM22PW (Marked as LVDM22)
(TOP VIEW)
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
DUAL MULTIPLEXED LVDS REPEATERS
•Meets or Exceeds the Requirements of ANSITIA/EIA-644-1995 Standard•Designed for Clock Rates up to 200 MHz(400 Mbps)•Designed for Data Rates up to 250 Mbps•Pin Compatible With SN65LVDS122 andSN65LVDT122, 1.5 Gbps 2x2 CrosspointSwitch From TI•ESD Protection Exceeds 12 kV on Bus Pins•Operates From a Single 3.3-V Supply•Low-Voltage Differential Signaling WithOutput Voltages of 350 mV Into:– 100- ΩLoad (SN65LVDS22)
– 50- ΩLoad (SN65LVDM22)•Propagation Delay Time; 4 ns Typ•Power Dissipation at 400 Mbps of 150 mW•Bus Pins Are High Impedance When Disabledor With V
CC
Less Than 1.5 V•LVTTL Levels Are 5 V Tolerant•Open-Circuit Fail Safe Receiver
The SN65LVDS22 and SN65LVDM22 are differentialline drivers and receivers that use low-voltagedifferential signaling (LVDS) to achieve signalingrates as high as 400 Mbps. The receiver outputs canbe switched to either or both drivers through themultiplexer control signals S0 and S1. This allows theflexibility to perform splitter or signal routing functionswith a single device.
The TIA/EIA-644 standard compliant electricalinterface provides a minimum differential outputvoltage magnitude of 247 mV into a 100- Ωload andreceipt of 100 mV signals with up to 1 V of groundpotential difference between a transmitter andreceiver. The SN65LVDM22 doubles the output drivecurrent to achieve LVDS levels with a 50- Ωload.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2002, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
The intended application of these devices and signaling technique is for both point-to-point baseband (singletermination) and multipoint (double termination) data transmissions over controlled impedance media. Thetransmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate anddistance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to theenvironment, and other application specific characteristics).
The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40°C to 85°C.
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
S0, S1
Input
50 Ω
300 kΩ
7 V
VCC
1DE, 2DE
Input
50 Ω
300 kΩ
7 V
VCC
300 kΩ300 kΩ
7 V7 V
A Input B Input
VCC
7 V
Y or Z
Output
5 Ω
10 kΩ
ABSOLUTE MAXIMUM RATINGS
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage range, V
CC
(see Note
(2)
) –0.5 V to 4 V(DE, S0, S1) –0.5 V to 6 VVoltage range
(Y, Z, A, and B) –0.5 V to 4 VA, B, Y, Z and GND (see Note
(3)
) Class 3, A:12 kV, B:600 VElectrostatic discharge
All pins Class 3, A:5 kV, B:500 VContinuous power dissipation See Dissipation Rating TableStorage temperature range –65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7.
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DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
2.4–VID
2
VID
2
TIMING REQUIREMENTS
1
00 0.1 0.2 0.3
1.5
2.5
2
0.5
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
– Common-Mode Input Voltage – VVIC
VID – Differential Input Voltage – V
0.4 0.5 0.6
Min
MAX at VCC = 3 V
MAX at VCC > 3.15 V
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
T
A
≤25°C DERATING FACTOR
(1)
T
A
= 85°CPACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
D 1110 mW 8.9 mW/°C 577 mWPW 839 mW 6.7 mW/°C 437 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage S0, S1, 1DE, 2DE 2 VV
IL
Low-level input voltage S0, S1, 1DE, 2DE 0.8 V|V
ID
| Magnitude of differential input voltage 0.1 0.6 V
VV
IC
Common-mode input voltage (see Figure 1 )
V
CC
–0.8 VT
A
Operating free-air temperature 40 85 °C
PARAMETER MIN NOM MAX UNIT
t
su
Input to select setup time 1.6 nst
h
Input to select hold time See Figure 6 1 nst
switch
Select to switch output 3.2 5 ns
Figure 1. Common-Mode Input Voltage vs Differential Input Voltage
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RECEIVER ELECTRICAL CHARACTERISTICS
RECEIVER/DRIVER ELECTRICAL CHARACTERISTICS
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IT+
Positive-going differential input voltage threshold 100 mVV
IT–
Negative-going differential input voltage threshold 100 mVV
I
= 0 V 2 20I
I
Input current (A or B inputs) µAV
I
= 2.4 V 1.2I
I(OFF
Power-off input current (A or B inputs) V
CC
= 0 V 20 µA)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
OD
Differential output voltage magnitude 247 340 454 mVSee Figure 2Change in differential output voltage magnitude∆V
OD
–50 50 mVbetween logic states
R
L
= 100 Ω('LVDS22), 1.37V
OC(SS)
Steady-state common-mode output voltage 1.125 VR
L
= 50 Ω('LVDM22) 5Change in steady-state common-mode output See Figure 3∆V
OC(SS)
–50 3 50 mVvoltage between logic statesV
OC(PP)
Peak-to-peak common-mode output voltage 150 mVNo Load 8 12R
L
= 100 Ω('LVDS22) 13 20I
CC
Supply current mAR
L
= 50 Ω('LVDM22) 21 27Disabled 3 6DE –10I
IH
High-level input current V
IH
= 5 V µAS0, S1 20DE –10I
IL
Low-level input current V
IL
= 0.8 V µAS0, S1 10
–10V
OY
or V
OZ
= 0 V, V
OD
= 0 V ('LVDS22)
–10I
OS
Short-circuit output current mA–10V
OY
or V
OZ
= 0 V, V
OD
= 0 V ('LVDM22)
–10V
OD
= 600 mV 0.015 ±1I
OZ
High-impedance output current µAV
O
= 0 V or V
CC
0.015 ±1I
O(OFF)
Power-off output current V
CC
= 0 V, V
O
= 3.6 V 0.015 ±1 µAC
IN
Input capacitance 3 pF
(1) All typical values are at 25°C and with a 3.3-V supply.
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DIFFERENTIAL RECEIVER TO DRIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
Y
ZVOD
Input
(see Note A) CL = 10 pF
(2 Places)
(see Note C)
RL (see Note B)
100%
80%
20%
0%
VOD
0
tftr
VI(B)
VI(A)
1.4 V
1 V
A
Pulse
Generator B
DE
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Differential propagation delay time, low-to-high 4 6 nst
PHL
Differential propagation delay time, high-to-low 4 6 nst
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) 0.2 nst
r
Transition time, low-to-high SN65LVDS22 C
L
= 10 pF, See Figure 4 1 1.5 nst
r
Transition time, low-to-high SN65LVDM22 0.8 1.3 nst
f
Transition time, high-to-low SN65LVDS22 1 1.5 nst
f
Transition time, high-to-low SN65LVDM22 0.8 1.3 nst
PHZ
Propagation delay time, high-level-to-high-impedance output 4 10 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 5 10 nsSee Figure 5t
PZH
Propagation delay time, high-impedance-to-high-level output 5 10 nst
PZL
Propagation delay time, high-impedance-to-low-level output 6 10 nst
PHL_R1_Dx
0.2t
PLH_R1_Dx
0.2Channel-to-channel skew, receiver to driver
(2)
nst
PHL_R2_Dx
0.2t
PLH_R2_Dx
0.2f
max
Maximum operating frequency All channels switching 200 MHz
(1) All typical values are at 25°C and with a 3.3-V supply.(2) These parametric values are measured over supply voltage and temperature ranges recommended for the device.
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns.B. R
L
= 100 Ωor 50 Ω±1%C. C
L
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 2. Test Circuit and Voltage Definitions for the Differential Output Signal
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10 pF
Pulse
Generator
80%
20%
0-V Differential
VOY – VOZ
VIB
VIA
1.4 V
1 V
tPLH tPHL
trtf
A
B
R D
10 pF
VOZ
VOY
1.4 V
1 V
0-V Differential
0-V Differential
1.2-V CM
1.2-V CM
DE
RL (see Note A)
Y
Z
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns.B. R
L
= 100 Ωor 50 Ω±1%C. C
L
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.D. The measurement of V
OC(PP)
is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A. R
L
= 100 Ωor 50 Ω±1%B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 50Mpps, pulse width = 10 ±0.2 ns.
Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time Waveforms
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A
B
R D
DE
1.2 V
RL/2
(see Note A)
RL/2
(see Note A)
2 V
1.4 V
0.8 V
1.2 V
1.15 V
≈1 V
≈1.4 V
1.25 V
1.2 V
tPZH tPHZ
tPZL tPLZ
DE
1.2 V
1 V or 1.4 V
VOY or VOZ
VOY or VOZ
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION (continued)
A. R
L
= 100 Ωor 50 Ω±1%B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 0.5Mpps, pulse width = 500 ±10 ns.
Figure 5. Enable and Disable Timing Circuit
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tsu th
1A/B
Out 1 or 2 Out 1 or 2
tsu
2A/B
S0/1
Outputs
DE
NOTE: tsu and th times specify that data must be in a stable state before and after MUX control switches.
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Input-to-Select for Both Rising and Falling Edge Setup and Hold Times
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TYPICAL CHARACTERISTICS
IOH − High-Level Output Current − mA
1
.5
0−2 −1
3
−4
1.5
VCC = 3.3 V
TA = 25°C
2
2.5
0−3
VOH− High-Level Ouptut V oltage − V
3.5
IOL − Low-Level Output Current − mA
1
040
2
VCC = 3.3 V
TA = 25°C
3
62
VOL− Low-Level Output Voltage − V
4
IOH − High-Level Output Current − mA
1
.5
0−4 −2
3
−8
1.5
VCC = 3.3 V
TA = 25°C
2
2.5
0−6
VOH− High-Level Output V oltage − V
3.5
IOL − Low-Level Output Current − mA
1
080
2
VCC = 3.3 V
TA = 25°C
3
124
VOL− Low-Level Output V oltage − V
4
6 102
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
SN65LVDS22 SN65LVDS22HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 7. Figure 8.
SN65LVDM22 SN65LVDM22HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 9. Figure 10.
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APPLICATION INFORMATION
FAIL SAFE
Rt = 100 Ω (Typ)
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
BY
SN65LVDS22
SN65LVDM22
SLLS315C – DECEMBER 1998 – REVISED JUNE 2002
One of the most common problems with differential signaling applications is how the system responds when nodifferential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in thatits output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mVand within its recommended input common-mode voltage range. However, TI's LVDS receiver is different in howit handles the open-input circuit situation.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverpulls each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 11 . The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force theoutput to a high-level regardless of the differential input voltage.
Figure 11. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100 mV differential inputvoltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as itis connected as shown in Figure 11 . Other termination circuits may allow a dc current to ground that could defeatthe pullup currents from the receiver and the fail-safe feature.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDM22D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM22DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM22PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM22PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS22PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Aug-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Aug-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS22DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS22PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS22DR SOIC D 16 2500 346.0 346.0 33.0
SN65LVDS22PWR TSSOP PW 16 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Sep-2009
Pack Materials-Page 2
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