1
©1999 Integrated Device Technology, Inc.
DECEMBER 1999
DSC-3822/03
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
IDT71V547
Pin Description Summary
The IDT71V547 contains address, data-in and control signal registers.
The outputs are flow-through (no output data register). Output enable is
the only asynchronous signal and can be used to disable the outputs at
any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst in progress is stopped. However, any pending data transfers (reads
or writes) will be completed. The data bus will tri-state one cycle after the
chip was deselected or write initiated.
The IDT71V547 has an on-chip burst counter. In the burst mode, the
IDT71V547 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the LBO input
pin. The LBO pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V547 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
Features
◆◆
◆◆
◆128K x 36 memory configuration, flow-through outputs
◆◆
◆◆
◆Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized signal eliminates the need to
control OEOE
OEOE
OE
◆◆
◆◆
◆Single R/WW
WW
W (READ/WRITE) control pin
◆◆
◆◆
◆4-word burst capability (Interleaved or linear)
◆◆
◆◆
◆Individual byte write (BWBW
BWBW
BW1 - BWBW
BWBW
BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆Single 3.3V power supply (±5%)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin TQFP package
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus
Turn-around.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle, its associated data cycle occurs, be it
read or write.
128K X 36, 3.3V Synchronous
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
A0 - A16 Address Inp uts Input Sy nchronous
CE1, CE2, CE2Three Chip Enab les Input Sy nchronous
OE Out put Enable Input Asy nchronous
R/WRead/ Write S ignal Input Sy nchronous
CEN Clock Enable Input Sy nchronous
BW1, BW2, BW3, BW4Ind ividual By te Write Selects Input Sy nchronous
CLK Clock Input N/A
ADV/LD Ad vance B urst A ddress / Load New Address Input Sy nchronous
LBO Linear / Int erleaved Burst Order Input St atic
I/O0 - I /O 31, I/OP1 -
I/OP4 Data Input /Out put I/O Sy nchronous
VDD 3.3V Pow er Supply Static
VSS Ground Supply Static
3822 t bl 01
2
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A0 - A16 Address Inputs I N/A Sy nchronous Address inputs. The address register is triggered by a com bination
of the rising edge of CLK , ADV/LD Low, CEN Low and t rue chip enables.
ADV/LD Address/Load I N/A ADV/LD is a synchronous input that is used to load the in ternal registers with new
addre ss and control w hen it is sam pled low at t he risin g edge of clock w ith t he
ch ip select ed. Wh en ADV /LD is low w ith the chip deselected, any burst in
progress is term inat ed. When ADV/LD is sampled high then t he internal burst
counte r is advanced f or any burst t hat w as in progress. The ext ernal addresses
are ignored w hen ADV/ LD is sample d high .
R/WRead/Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle
init iated is a Read or Writ e access to t he m em ory array. The data bus ac tiv it y for
the current cy cle takes pla ce one clock cy cle later.
CEN Clock Enable I LOW Sy nchronous Clo ck Enable Input. When CEN is sam pled high, all other
sy nchronous inputs, including clock are ignored and out put s rem ain unchanged.
The effect of CEN sam pled high on the dev ice outputs is as if the low to high
clock transition did not occu r. For norm al operat ion, CEN m ust be sam pled low at
rising edge of clock.
BW1 - BW4I ndividual Byt e
Writ e Enables I LOW Sy nch ronous by te w rite enables. E nable 9-bit by te has its ow n act iv e low byt e
w rit e enable. On loa d w rit e cycles (When R/W and ADV/ LD are sam pled low ) t he
appro priate byt e w rit e signal (BW1 - BW4) must be v alid. The by te w rite signal
m ust a lso be v alid on each cy cle of a burst w rite. Byt e Write signals are ignored
w hen R/ W is sam pled high. The appropriate by te(s) of data are w ritten into t he
dev ice one cy cle later. BW1 - BW4 can all be tied low if alw ays doing w rit e to the
en tire 36-b it w ord .
CE1, CE2Chip Enables I LOW Sy nchronous act iv e low chip enable. CE1 and CE2 are used w ith CE 2 to
e nable the IDT71V547. (CE1 or CE2 sam pled high or CE2 sa m ple d lo w ) and
ADV/LD low at the rising edge of clock, initiates a deselec t cy cle. This device has
a one cycle deselect, i. e., the dat a bus w ill tri-state one c lock cycle af ter deselect
is i nit iat ed .
CE2 Chip Enable I HI GH Sy nchronout act iv e high chip enable. CE2 is used w ith CE1 and CE2 to enable
the chip. CE2 has inv erted polarity b ut ot herw ise ident ical to CE1 and CE2.
CLK Clock I N /A This is the clock input to t he I DT71V547. Except for OE, all tim ing references for
th e device are m ade w ith respect to t he rising edge of CLK.
I/O0 - I /O 31
I/OP1 - I/OP4 Dat a Input /Output I/ O N/ A Dat a input /output (I/O) pins. The dat a input path is registered, triggered by the
rising edge of CLK. The dat a output path is flow -thro ugh (no out put register).
LBO Linear Burst
Order I LO W Burst orde r selection input. When LBO is high the I nterl eaved burst sequence is
selected. When LBO is low t he Linear burs t sequence is select ed. LBO is a stat ic
DC input .
OE Outpu t Enable I LOW Asy nc hronous output enable. OE m ust be low t o read data from the 71V547.
When OE is high the I/O pins are in a high-im pedance st ate. OE does not need
to be act iv ely controlled for read and w rite cy cles. In norm al operat ion, OE can be
tied low.
VDD Pow er Supply N/A N/A 3 .3V pow er supply input.
VSS Ground N/ A N/ A Ground pin.
3822 tbl 02
6.42
3
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
Input Register
3822 drw 01
Clock
Data I/O [0:31], I/O P[1:4]
Mux Sel
Gate
OE
CE1,CE2CE2
R/W
CEN
ADV/LD
BWx
LBO 128K x 36 BIT
MEMORY ARRAY
,
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
Grade Temperature VSS VDD
Commercial 0
O
C to + 70
O
C0V 3.3V±5%
Industrial -40
O
C to + 85
C0V 3.3V±5%
3 822 t bl 03
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD Sup p ly Vo ltag e 3.135 3.3 3.465 V
VSS Ground 0 0 0 V
VIH Inp ut Hi g h Vo l tag e - Inp uts 2. 0 ____ 4.6 V
VIH In put H igh Volta ge - I/O 2.0 ____ VDD+0.3(2) V
VIL Inp ut Lo w Vo l tag e -0. 5(1) ____ 0.8 V
3 822 t bl 04
4
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configuration
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
NOTES:
1. Pin 14 does not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively.
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
VDD
VSS
VSS
VDD
I/O27
I/O26
VSS
VDD
I/O25
I/O24
VDD
VSS
VSS
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
VSS
I/O23
I/O22
VSS
VDD
I/O21
I/O20
VSS
VDD
I/O11
I/O10
VDD
VSS
I/O9
I/O8
I/O7
I/O6
VSS
VDD
I/O5
I/O4
PK100-1
3822 drw 02
VSS(1)
VDD
A
15
A
16
I/O12
I/O28
VSS
VSS
BW
4
BW
3
I/OP2
I/O14
I/O15
I/O13
I/O2
I/O3
I/OP1
I/O0
I/O1
I/OP4
I/O30
I/O31
I/O29
I/O19
I/O18
I/OP3
I/O16
I/O17
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDD and Input terminals only.
3. I/O terminals.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Value
Unit
V
TERM
(2)
Supply Voltage on VDD with
Re sp e c t to GND –0.5 to +3.6 V
V
TERM
(3)
DC In p ut Vo ltag e
(5)
–0.5 to V
DDQ
+0.5 V
V
TERM
(4)
DC Voltage Applied to Outputs in
Hig h-Z State
(5)
–0.5 to V
DDQ
+0.5 V
T
A
Operating Temperature 0°C to 70°C °C
T
BIAS
Ambient Temperature with Power
Applied (Temperature Under
Bias)
–55 to +125 °C
T
STG
Storage Temperature –65 to +150 °C
I
OUT
Current into Outp uts (Lo w) 20 m A
V
ESD
Static Discharge Voltage
(per MIL-STD-883, Method 3015) >2001 V
I
LU
Latch-Up Current >200 mA
5284 t b l 05
Symbol Parameter
(1)
Conditions Max. Unit
CIN I nput C apacit ance VIN = 3dV 5 pF
CI/O I/ O Capacitance VOUT = 3dV 7 pF
3822 t bl 06
Top View
TQFP
6.42
5
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Partial Truth Table for Writes(1)
Synchronous Truth Table(1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature
of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus
will tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if either one of thechip enable is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
CEN
R/
W
Chip
(5)
Enable
ADV/
LD BW
x
ADDRESS
USED
PREVIOUIS CYCLE
CURRENT CYCLE
I/O
(1 cycle later)
L L Select L Valid External X LOAD WRI TE D(7)
L H Select L X External X LOAD READ Q(7)
L X X H Valid I nternal LOAD WRI TE/
BURST WRITE BURST WRITE
(Advance Burst Counter)(2) D(7)
L X X H X Int ernal LO AD READ/
BURST READ BURST READ
(Advance Burst Counter)(2) Q(7)
L X Deselect L X X X DESELECT or STOP(3) HiZ
L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUSPEND(4) Previous Value
3822 t bl 07
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Operation
R/
WBW
1
BW
2
BW
3
BW
4
READ HXXXX
WRITE ALL BYTES L L L L L
WRITE BY TE 1 (I/O [0:7], I/O P1)(2) LLHHH
WRITE BYTE 2 (I/O [8:15], I/OP2)(2) LHLHH
WRITE B YTE 3 (I/ O [16:23], I/ OP3)(2) LHHLH
WRITE B YTE 4 (I/ O [24:31], I/ OP4)(2) LHHHL
NO WRITE LHHHH
3822 tbl 08
6
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Timing Diagram(1)
NOTE:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
n+29
A29
C29
D/Q28
ADDRESS
(A0 - A16)
CONTROL
(R/W,ADV/LD,BWx)
DATA
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q29
n+31
A31
C31
D/Q30
n+32
A32
C32
D/Q31
n+33
A33
C33
D/Q32
n+34
A34
C34
D/Q33
n+35
A35
C35
D/Q34
n+36
A36
C36
D/Q35
(2)
(2)
(2)
3822 drw 03
A37
C37
D/Q36
n+37
.,
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address000110 11
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 10 01 00
3822 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11 00 01 10
3822 tbl 10
6.42
7
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
NOTE:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
Cycle
Address
R/
W
ADV/
LD CE
(1)
CEN BW
x
OE
I/O
Comments
nA0HLLLXXD1Load read
n+1 X X H XLXLQ0Burst read
n+2 A1 H L L L X L Q0+1 Load re ad
n+3 X X L H L X L Q1 Dese lect or STOP
n+4 X X H X L X X Z NOOP
n+5 A2 H L L L X X Z Lo ad re ad
n+6 X X H XLXLQ2Burst read
n+7 X X L H L X L Q2+1 Deselect or STOP
n+8 A3 L L L L L X Z Load write
n+9 X X H X L L X D3 Burs t write
n+10 A4 L L L L L X D3+1 Lo ad write
n+11 X X L H L X X D4 Deselect or STOP
n+12 X X H X L X X Z NOOP
n+13 A5 L L L L L X Z Load write
n+14 A6 H L L L X X D5 Lo ad re ad
n+15 A7 L L L L L L Q6 Lo ad write
n+16 X X H X L L X D7 Burs t write
n+17 A8 H L L L X X D7+1 Lo ad re ad
n+18 X X H X L X L Q8 Burs t re ad
n+19 A9 L L L L L L Q8+1 Load write
3822 tbl 11
8
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Read Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X X X X X L Q0 Contents of Address A0 Read Out
3822 tbl 12
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control m eet setup
n+1
X
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+2
X
X
H
X
L
X
L
Q
0+1
Address A
0+1
Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q
0+2
Address A
0+2
Read Out, Inc. Count
n+4
X
X
H
X
L
X
L
Q
0+3
Address A
0+3
Read Out, Load A1
n+5
A1
H
L
L
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+6
X
X
H
X
L
X
L
Q1
Address A1 Read Out, Inc. Count
n+7
A2
H
L
L
L
X
L
Q
1+1
Address A
1+1
Read Out, Load A2
3822 t bl 13
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X X X L X X D0 Write to Address A0
3822 tbl 14
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X H X L L X D0 Address A0 Write, Inc. Count
n+2 X X H X L L X D0+1 Address A0+1 Write, Inc. Count
n+3 X X H X L L X D0+2 Address A0+2 Write, Inc. Count
n+4 X X H X L L X D0+3 Address A0+3 Write , Lo ad A1
n+5 A1 L L L L L X D0 Address A0 Write, Inc. Count
n+6 X X H X L L X D1 Address A1 Write, Inc. Count
n+7 A2 L L L L L X D1+1 Address A1+1 Write , Lo ad A2
3822 tbl 15
6.42
9
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Read Operation With Clock Enable Used(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation With Clock Enable Used(1)
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control m eet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored
n+2
A1
H
L
L
L
X
L
Q0
Address A0 Read out, Load A1
n+3
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus
n+4
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus
n+5
A2
H
L
L
L
X
L
Q1
Address A1 Read out, Load A2
n+6
A3
H
L
L
L
X
L
Q2
Address A2 Read out, Load A3
n+7
A4
H
L
L
L
X
L
Q3
Address A3 Read out, Load A4
3822 t bl 16
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X X X H X X X Clo ck n+1 Ig nore d
n+2 A1 L L L L L X D0 Write d ata D0, Lo ad A1
n+3 X X X XHXXXClock Ignored
n+4 X X X XHXXXClock Ignored
n+5 A2 L L L L L X D1 Write data D1, Lo ad A2
n+6 A3 L L L L L X D2 Write d ata D2, Lo ad A3
n+7 A4 L L L L L X D3 Write d ata D3, Lo ad A4
3822 tbl 17
10
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Read Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Chip Enable Used(1)
Cycle
Address
R/
W
ADV/
LD CE
(1)
CEN BW
x
OE
I/O
(3)
Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X Z Deselected
n+2 A0 H L L L X X Z Address A0 and Control meet setup
n+3 X X L H L X L Q0 Address A0 read out. Deselected
n+4 A1 H L L L X X Z Address A1 and Control meet setup
n+5 X X L H L X L Q1 Address A1 Read out. Deselected
n+6 X X L H L X X Z Deselected
n+7 A2 H L L L X X Z Address A2 and Control meet setup
n+8 X X L H L X L Q2 Address A2 read out. Deselected
n+9 X X L H L X X Z Deselected
3822 tbl 18
Cycle
Address
R/
W
ADV/
LD CE
(1)
CEN BW
x
OE
I/O
Comments
n
X
X
L
H
L
X
X
?
Deselected
n+1
X
X
L
H
L
X
X
Z
Deselected
n+2
A0
L
L
L
L
L
X
Z
Address A0 and Control m eet setup
n+3
X
X
L
H
L
X
X
D0
Address D0 Write In. Deselected
n+4
A1
L
L
L
L
L
X
Z
Address A1 and Control m eet setup
n+5
X
X
L
H
L
X
X
D1
Address D1 Write In. Deselected
n+6
X
X
L
H
L
X
X
Z
Deselected
n+7
A2
L
L
L
L
L
X
Z
Address A2 and Control m eet setup
n+8
X
X
L
H
L
X
X
D2
Address D2 Write In. Deselected
n+9
X
X
L
H
L
X
X
Z
Deselected
3822 t bl 19
6.42
11
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Symbol
Parameter
Test Conditions
S80
S85
S90
S100
Unit
Com'l
Ind
Com'l
Ind
Com'l
Ind
Com'l
Ind
IDD Operating Power
Sup ply Curre nt Device Selected, Outputs Open, ADV/LD = X,
VDD = Max., VIN > VIH or < VIL, f = fMAX(2) 250 260 225 235 225 235 200 210 mA
ISB1 CMOS Stand by Po wer
Sup ply Curre nt Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD, f = 0(2) 40 45 40 45 40 45 40 45 mA
ISB2 Cl o ck Running P o we r
Sup ply Curre nt Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD, f = fMAX(2) 100 110 95 105 95 105 90 100 mA
ISB3 Id l e P o we r
Sup ply Curre nt Device Selected, Outputs Open, CEN > VIH
VDD = Max., VIN > VHD or < VLD, f = fMAX(2) 40 45 40 45 40 45 40 45 mA
3822 tbl 21
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads AC Test Conditions
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range(1) (VDD = 3.3V +/-5%, VHD = VDD0.2V, VLD = 0.2V)
1.5V
50Ω
I/O Z0=50Ω
3822 drw 04
+
,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
3822 drw 05 .
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI| Input Leakag e Current VDD = Max., VIN = 0V to VDD ___ 5µA
|ILI|LBO Input Le akag e Curre nt(1) VDD = Max., VIN = 0V to VDD ___ 30 µA
|ILO|Outp ut Le akag e Curre nt CE > VIH or OE > VIH, VOUT = 0V toVDD, VDD = Max. ___ 5µA
VOL Outp ut Low Voltag e IOL = 5mA, VDD = Min. ___ 0.4 V
VOH Outp ut Hig h Vo ltag e IOH = -5mA, VDD = Min. 2.4 ___ V
3822 tbl 20
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
Inp ut P ul s e Le v e l s
Inp ut Ris e / Fal l Tim e s
Inp ut Timing Re fere nce Le v el s
Outp ut Timing Re fe rence Lev els
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
3 822 t bl 22
12
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V). .
Symbol
Parameter
71V547S80
71V547S85
71V547S90
71V547S100
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Clock Parameters
tCYC Clock Cycle Time 10.5
____
11
____
12
____
15
____
ns
tCH(2) Clock High Pulse Width 3
____
3.9
____
4
____
5
____
ns
tCL(2) Clock Low Pulse Width 3
____
3.9
____
4
____
5
____
ns
Output Parameters
tCD Clock High to Valid Data
____
8
____
8.5
____
9
____
10 ns
tCDC Clo ck Hi gh to Data Chang e 2
____
2
____
2
____
2
____
ns
tCLZ(3,4,5) Cl o ck Hi g h to Outp u t Ac ti ve 4
____
4
____
4
____
4
____
ns
tCHZ(3,4,5) Cl o ck Hi g h to Da ta High-Z
____
5
____
5
____
5
____
5ns
tOE Output Enable Access Time
____
5
____
5
____
5
____
5ns
tOLZ(3,4) O u tput En a ble L ow to D a ta Active 0
____
0
____
0
____
0
____
ns
tOHZ(3.4) Ou tpu t E n able Hi gh to Data Hi gh -Z
____
5
____
5
____
5
____
5ns
Setup Times
tSE Clo ck Enab le S e tup Ti me 2. 0
____
2.0
____
2.0
____
2.5
____
ns
tSA Address Setup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
tSD Data in S etup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
tSW Re ad /Write (R/ W) Se tup Ti me 2. 0
____
2.0
____
2.0
____
2.5
____
ns
tSADV Ad vanc e/ Load (ADV/ LD) S e tup Time 2. 0
____
2.0
____
2.0
____
2.5
____
ns
tSC Chip Enable/Select Setup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
tSB B yte Write Enab le (BWx) Setup Time 2.0
____
2.0
____
2.0
____
2.5
____
ns
Ho ld Ti m es
tHE Clo ck Enab le Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
tHA Address Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
tHD Data in Ho ld Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
tHW Re ad /Write (R/ W) Ho l d Time 0. 5
____
0.5
____
0.5
____
0.5
____
ns
tHADV Ad vanc e/ Load (ADV/ LD) Ho l d Tim e 0. 5
____
0.5
____
0.5
____
0.5
____
ns
tHC Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
tHB B yte Write Enab le (BWx) Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
3822 tbl 23
6.42
13
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1, 2, 3, 4)
NOTES:
1 . Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the
burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/ W signal when new address
and control are loaded into the SRAM.
(CENhigh, eliminates
current L-H clock edge)
Q(A2+1)
tCD
Read
tCLZ tCHZ
tCD
tCDC
Q(A2+2)
Q(A1) Q(A2) Q(A2+3)Q(A2+3)Q(A2)
Burst Read
Read
DATAOut
(Burst Wraps around
to initial state)
tCDC
tHADV
3822 drw 06
R/W
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2
(
2)
BW
1
-BW
4
OE
tHE
tSE
A1A2
tCH
tCL
tCYC
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
,
14
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base
address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATAIn D(A1) D(A2)
tHD
tSD(CENhigh, eliminates
current L-H clock edge)
D(A2+1)D(A2+2)D(A2+3)D(A2)
Burst Write
Write Write
(Burst Wraps around
to initial state)
tHD
tSD
tCHtCL
tCYC
tHADV
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
tHB
tSB
3822 drw 07
B(A1) B(A2) B(A2+1)B(A2+2)B(A2+3)B(A2)
.
6.42
15
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2
(2)
BW
1
-BW
4
OE
DATAOut Q(A3)
Q(A1) Q(A6) Q(A7)
tCD
Read Read
Read Read
tCHZ
3822 drw 08
Write
tCLZ
D(A2) D(A4)
tCDC
D(A5)
Write
tCHtCL
tCYC
tHW
tSW
tHA
tSA
A4
A3
tHC
tSC
tSDtHD
tHADV
tSADV
A6A7A8
A5A9
DATAIn
tHB
tSB
Write
D(A8)
Write
B(A2) B(A4) B(A5) B(A8)
,
16
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH..
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition
did not occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATAOut Q(A1)
tCDC
Q(A3)
tCD
tCLZ
Q(A1) Q(A4)
tCDtCDC
tCHZD(A2)
tSDtHD
tCHtCL
tCYC
tHC
tSC
A4A5
tHADV
tSADV
tHW
tSW
tHA
tSA
A3
tHB
tSB
DATAIn
3822 drw 09
B(A2)
,
6.42
17
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3 . When either one of the Chip enables ( CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation
of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in one cycle before the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
CE
1
,CE
2(2)
OE
DATAOut Q(A1) Q(A2) Q(A4)
tCLZ
Q(A4)
tCDtCHZ
tCDC
D(A3)
tSDtHD
tCHtCL
tCYC
tHC
tSC
A5
A3
tSB
DATAIn
tHE
tSE
A2
tHA
tSA
A4
tHW
tSW
tHB
CEN
tHADV
tSADV
3822 drw 10
BW
1
-BW
4B(A3)
.
18
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA Out
tOHZ tOLZ
tOE
QQ .
3822 drw 11
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
S
Power
XX
Speed
PF
Package
PF
IDT 71V547
80
85
90
100 Access time (tCD) in tenths of nanoseconds
3822 drw 12
Device
Type
PART NUMBER tCD PARAMETER
71V547S80PF
71V547S85PF
71V547S90PF
71V547S100PF
95 MHz
90 MHz
83 MHz
66 MHz
8ns
8.5 ns
9ns
10 ns
10.5 ns
11 ns
12ns
15 ns
SPEED IN MEGAHERTZ CLOCK CYCLE TIME
X
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
6.42
19
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT
Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
6/15/99 Updated to new format
9/13/99 Pg. 11 Corrected ISB3 conditions
Pg. 19 Added Datasheet Document History
12/31/99 Pp. 3, 11, 12, 18 Added Industrial Temperature range offerings
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775 800-345-7015 or
www.idt.com 408/284-4555