CY7C1011DV33
2-Mbit (128 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05609 Rev. *E Revised December 1, 2010
2-Mbit (128 K × 16) Static RAM
Features
■Pin-and function-compatible with CY7C1011CV33
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 90 mA @ 10 ns (Industrial)
■Low CMOS standby power
❐ISB2 = 10 mA
■Data Retention at 2.0 V
■Automatic power-down when deselected
■Independent control of upper and lower bits
■Easy memory expansion with CE and OE features
■Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA
Functional Description
The CY7C1011DV33[1] is a high-performance CMOS Static
RAM organized as 128 K words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011DV33 is available in standard Pb-free 44-pin
TSOP II with center power and ground pinout, as well as
48-ball very fine-pitch ball grid array (VFBGA) packages.
14
15
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
128K X 16
A0
A11
A13
A12
A
A
A16
A9
A10
I/O0–I/O7
OE
I/O8–I/O15
CE
WE
BLE
BHE
Logic Block Diagram
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com
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Document Number: 38-05609 Rev. *E Page 2 of 14
Contents
Selection Guide ................................................................3
Pin Configurations ...........................................................3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics ..........................................4
Capacitance ...................................................................... 4
Thermal Resistance ..........................................................4
AC Test Loads and Waveforms ....................................... 5
AC Switching Characteristics .........................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Waveforms ...................................................... 7
Read Cycle No. 1 ........................................................7
Read Cycle No. 2 (OE Controlled) .............................. 7
Write Cycle No. 1 (CE Controlled) ............................... 8
Write Cycle No. 3 (WE Controlled,
OE HIGH During Write) ...................................................... 9
Write Cycle No. 4 (WE Controlled, OE LOW) ............. 9
Truth Table ...................................................................... 10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History ........................................................... 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
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Document Number: 38-05609 Rev. *E Page 3 of 14
Pin Configurations
Selection Guide
–10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 90 mA
Maximum CMOS Standby Current 10 mA
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II
12
13
41
44
43
42
16
15
29
30
VCC
A15
A14
A13
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21
23
24
NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A16
WE
V
CC
A
11
A9
NC
A6
A
0
A
3CE
I/O
10
I/O
8
I/O
9
A4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A8
A7
OE
V
SS
NC
I/O
0
BHE
NC
A10
A2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5I/O
6
I/O
7
A15
A14
A13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
48-ball VFBGA
(Top View)
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CY7C1011DV33
Document Number: 38-05609 Rev. *E Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ........................................... –55 C to +125 C
Supply voltage on VCC to relative GND[3].....–0.3 V to +4.6 V
DC voltage applied to outputs
in high Z State[3] .................................. –0.3 V to VCC + 0.3 V
DC input voltage[3] ...............................–0.3 V to VCC + 0.3 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage............ ...............................> 2001 V
(per MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
Range Ambient
Temperature VCC
Industrial –40 C to +85 C 3.3 V 0.3 V
Notes
2. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions –10 Unit
Min Max
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 8.0 mA – 0.4 V
VIH Input HIGH voltage 2.0 VCC + 0.3 V
VIL Input LOW voltage[2] –0.3 0.8 V
IIX Input leakage current GND < VI < VCC –1 +1 A
IOZ Output leakage current GND < VOUT < VCC, Output Disabled –1 +1 A
ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 mA
83 MHz – 80
66 MHz – 70
40 MHz – 60
ISB1 Automatic CE Power-down
Current — TTL Inputs
Max VCC, CE > V IH, VIN > VIH or VIN < VIL,
f = fMAX
–20mA
ISB2 Automatic CE Power-down
Current — CMOS Inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–10mA
Capacitance[3]
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT I/O capacitance 8 pF
Thermal Resistance[3]
Parameter Description Test Conditions TSOP II VFBGA Unit
JA Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
50.66 27.89 C/W
JC Thermal Resistance
(Junction to Case)
17.17 14.74 C/W
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Document Number: 38-05609 Rev. *E Page 5 of 14
Notes
4. AC characteristics (except high Z) are tested using the load conditions shown in (a). High Z characteristics are tested for all speeds using the test load shown in (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
7. tHZOE, tHZCE, tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a
high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any
given device.
AC Test Loads and Waveforms[4]
AC Switching Characteristics
Over the Operating Range[5]
Parameter Description –10 Unit
Min Max
Read Cycle
tpower[6] VCC(typical) to the first access 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE LOW to data valid – 10 ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z 0 – ns
tHZOE OE HIGH to high Z[7, 8] –5 ns
tLZCE CE LOW to low Z[8] 3– ns
tHZCE CE HIGH to high Z[7, 8] –5 ns
tPU CE LOW to power-up 0 – ns
tPD CE HIGH to power-down – 10 ns
tDBE Byte enable to data valid – 5 ns
tLZBE Byte enable to low Z 0 – ns
tHZBE Byte disable to high Z – 6 ns
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5 V
(c)
(a)
3.3 V
OUTPUT
5 pF
R 317
R2
351
High Z characteristics:
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Document Number: 38-05609 Rev. *E Page 6 of 14
Write Cycle[9, 10]
tWC Write cycle time 10 – ns
tSCE CE LOW to write end 7 – ns
tAW Address set-up to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address set-up to write start 0 – ns
tPWE WE pulse width 7 – ns
tSD Data set-up to write end 5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z[12] 3– ns
tHZWE WE LOW to high Z[11, 12] –5 ns
tBW Byte enable to end of write 7 – ns
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions[13] Min Max Unit
VDR VCC for data retention 2.0 – V
ICCDR Data retention current
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
–10mA
tCDR[14] Chip deselect to data retention time 0 – ns
tR[15] Operation recovery time tRC –ns
Data Retention Waveform
AC Switching Characteristics
Over the Operating Range[5] (continued)
Parameter Description –10 Unit
Min Max
3.0 V3.0 V
tCDR
VDR > 2 V
DATA RETENTION MODE
tR
CE
VCC
Notes
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. tHZOE, tHZCE, tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a
high impedance state.
12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for
any given device.
13. No input may exceed VCC + 0.3 V.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
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Document Number: 38-05609 Rev. *E Page 7 of 14
Switching Waveforms
Read Cycle No. 1[16, 17]
Read Cycle No. 2 (OE Controlled)[17, 18]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
CURRENT
ICC
ISB
Notes
16. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE transition LOW.
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CY7C1011DV33
Document Number: 38-05609 Rev. *E Page 8 of 14
Write Cycle No. 1 (CE Controlled)[19, 20]
Write Cycle No. 2 (BLE or BHE Controlled)
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATAI/O
ADDRESS
CE
WE
BHE, BLE
t
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA I/O
ADDRESS
BHE,BLE
WE
CE
Notes
19. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1011DV33
Document Number: 38-05609 Rev. *E Page 9 of 14
Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[21, 22]
Write Cycle No. 4 (WE Controlled, OE LOW)
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
t
HZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 23
BHE,BLE
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
NOTE 23
BHE,BLE
Notes
21. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
23. During this period the I/Os are in the output state and input signals should not be applied.
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Document Number: 38-05609 Rev. *E Page 10 of 14
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High Z High Z Power-down Standby (ISB)
L L H L L Data Out Data Out Read all bits Active (ICC)
L L H L H Data Out High Z Read lower bits only Active (ICC)
L L H H L High Z Data Out Read upper bits only Active (ICC)
L X L L L Data In Data In Write all bits Active (ICC)
L X L L H Data In High Z Write lower bits only Active (ICC)
L X L H L High Z Data In Write upper bits only Active (ICC)
L H H X X High Z High Z Selected, outputs disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
10 CY7C1011DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free) Industrial
CY7C1011DV33-10BVI 51-85150 48-ball VFBGA
CY7C1011DV33-10BVXI 48-ball VFBGA (Pb-free)
Ordering Code Definitions
Please contact your local Cypress sales representative for availability of these parts
Temperature Range:
I = Industrial
Package Type: xxx = ZSX or BV or BVX
ZSX = 44-pin TSOP II (Pb-free)
BV = 48-ball VFBGA
BVX = 48-ball VFBGA (Pb-free)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
1 = Data width × 16-bits
01 = 2-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 V33 - 10 xxx701 1 D I
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Document Number: 38-05609 Rev. *E Page 12 of 14
Acronyms Document Conventions
Units of Measure
Acronym Description
CMOS complementary metal oxide semiconductor
CE chip enable
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small-outline package
TTL transistor-transistor logic
VFBGA very fine-pitch ball grid array
WE write enable
Symbol Unit of Measure
ns nano seconds
VVolts
µs micro seconds
µA micro Amperes
mA milli Amperes
MHz Mega Hertz
pF pico Farad
°C degree Celcius
WWatts
% percent
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Document Number: 38-05609 Rev. *E Page 13 of 14
Document History
Document Title: CY7C1011DV33 2-Mbit (128 K × 16) Static RAM
Document Number: 38-05609
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 250650 See ECN RKF New Data Sheet
*A 399070 See ECN NXR Changed from Advance to Preliminary
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed TQFP Package from product offering
Removed –15 speed bin
Corrected DC voltage limits in maximum ratings section from –0.5 to –0.3V
and VCC +0.5V to VCC +0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80 and 70 mA to 90, 80 and 75 mA for 8, 10
and 12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 70 mA to 90 and 85 mA for 10 and 12ns
speed bins respectively
Modified Note# 4 on AC Test Loads
Added Static Discharge Voltage and latch-up current spec
Added VIH(max) spec in Note# 2
Changed reference voltage level for measurement of Hi-Z parameters from
500 mV to 200 mV
Added Data Retention Characteristics Table and footnote on tR
Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram
Changed package name for 44-pin TSOP II from Z to ZS
Added 8 ns parts in the Ordering Information table
Shaded Ordering Information Table
*B 459073 See ECN NXR Converted Preliminary to Final.
Removed –8 and –12 Speed bins
Removed Commercial Operating Range from product offering.
Changed the description of IIX from “Input Load Current” to “Input Leakage
Current”
Updated the Thermal Resistance table.
Changed tHZBE from 5 ns to 6 ns.
Updated footnote #7 on High-Z parameter measurement
Added footnote #12.
Updated the Ordering Information and replaced Package Name column with
Package Diagram in the Ordering Information table.
*C 480177 See ECN VKN Added -10BVI product ordering code in the Ordering Information table.
*D 3059162 10/14/2010 PRAS Added Ordering Code Definitions.
Updated Package Diagrams.
*E 3098812 12/01/2010 PRAS Added Acronyms and Units of Measure.
Minor edits and updated in new template.
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Document Number: 38-05609 Rev. *E Revised December 1, 2010 Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1011DV33
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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