SEMICONDUCTOR
1
July 1997
HS-1840ARH
Rad-Hard 16 Channel CMOS Analog
Multiplexer with High-Z Analog Input Protection
Description
• Pin-to-Pin for Harris’ HS-1840RH and HS-1840/883S
• MIL-PRF-38535 Screened to DSCC SMD 5962F95630
• Improved Radiation Performance
- Gamma Dose (γ) 3x 105 RAD(Si)
• Improved rDS(ON) Linearity
• Improved Access Time 1.5µs (Max) Over Temp and Post
Rad
• High Analog Input Impedance 500MΩDuring Power
Loss (Open)
•±35V Input Over Voltage Protection (Power On or Off)
• Dielectrically Isolated Device Islands
• Excellent in Hi-Rel Redundant Systems
• Break-Before-Make Switching
• No Latch-Up
Description
The HS-1840ARH is a radiation hardened, monolithic 16
channel multiplexer constructed with the Harris Rad-Hard
Silicon Gate, bonded wafer, Dielectric Isolation process. It is
designed to provide a high input impedance to the analog
source if device power fails (open), or the analog signal volt-
age inadvertently exceeds the supply by up to ±35V, regard-
less of whether the device is powered on or off. Excellent for
use in redundant applications, since the secondary device
can be operated in a standby unpowered mode affording no
additional power drain. More significantly, a very high imped-
ance exists between the active and inactive devices prevent-
ing any interaction. One of sixteen channel selection is
controlled by a 4-bit binary address plus an Enable-Inhibit
input which conveniently controls the ON/OFF operation of
several multiplexers in a system. All inputs have electrostatic
discharge protection.
The HS-1840ARH is processed and screened in full
compliance with MIL-PRF-38535 and QML standards. The
device is available in a 28 lead SBDIP and a 28 lead
Ceramic Flatpack.
Detailed Electrical Specifications are contained in DSCC
SMD Number 5962-95630.
Pinouts
Ordering Information
PART
NUMBER CLASS TEMP.
RANGE (oC) PACKAGE PKG.
NO.
5962F9563002VXC V -55 to 125 28 Ld SBDIP D28.6
5962F9563002QXC Q -55 to 125 28 Ld SBDIP D28.6
HS1-1840ARH/Proto -55 to 125 28 Ld SBDIP D28.6
HS1-1840ARH/Sample 25 28 Ld SBDIP D28.6
5962F9563002VYC V -55 to 125 28 Ld Ceramic
Flatpack K28.A
5962F9563002QYC Q -55 to 125 28 Ld Ceramic
Flatpack K28.A
HS9-1840ARH/Proto -55 to 125 28 Ld Ceramic
Flatpack K28.A
HS9-1840ARH/Sample 25 28 Ld Ceramic
Flatpack K28.A
HS1-1840RH (SBDIP) CASE OUTLINE CDIP2-T28,
COMPLIANT TO MIL-STD-1835 PACKAGE
TOP VIEW
HS9-1840RH (CERAMIC FLATPACK) OUTLINE CDFP3-F28,
COMPLIANT TO MIL-STD-1835 PACKAGE
TOP VIEW
+VS
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
(+5VS) VREF
ADDR A3
OUT
IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
ENABLE
ADDR A0
ADDR A1
ADDR A2
-VS
IN 4
IN 2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+VS
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
(+5VS)V
REF
ADDR A3
OUT
-VS
IN 8
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
ENABLE
ADDR A0
ADDR A1
ADDR A2
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 File Number 4355
2
Functional Diagram
TRUTH TABLE
A3 A2 A1 A0 EN “ON” CHANNEL
XXXXH None
LLLLL 1
LLLHL 2
LLHLL 3
LLHHL 4
LHLLL 5
LHLHL 6
LHHLL 7
LHHHL 8
HLLLL 9
HLLHL 10
HLHLL 11
HLHHL 12
HHLLL 13
HHLHL 14
HHHLL 15
HHHHL 16
P
EN
IN 1
OUT
IN 16
DIGITAL
ADDRESS
DECODERSADDRESS INPUT
BUFFER AND
LEVEL SHIFTER
MULTIPLEX
SWITCHES
A0
A1
A2
P
A3
1
16
HS-1840ARH
3
Burn-In/Life Test Circuits
NOTES:
VS+ = +15.5V ±0.5V, VS- = -15.5V ±0.5V.
R = 1kΩ±5%.
C1 = C2 = 0.01µF±10%, 1 each per socket, minimum.
D1 = D2 = 1N4002, 1 each per board, minimum.
Input Signals: square wave, 50% duty cycle, 0V to 15V peak ±10%.
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
NOTES:
R = 1kΩ±5%, 1/4W.
C1 = C2 = 0.01µF minimum, 1 each per socket, minimum.
VS+ = 15.5V ±0.5V, VS- = -15.5V ±0.5V, VR = 15.5 ±0.5V.
FIGURE 2. STATIC BURN-IN TEST CIRCUIT
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
Irradiation Circuit
HS-1840ARH
NOTE: All irradiation testing is performed in the 28 lead CERDIP package.
R
R
GND
+VS
R
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F4 F3
F1 F5
F2
-VS
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
R
R
R
GND
VR
+VS
R-VS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1kΩ
+15V
+1V
+5V
NC
NC
-15V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HS-1840ARH
4
Die Characteristics
DIE DIMENSIONS:
(2820µm x 4080µm x 483µm± 25.4µm)
111 x 161 x 19mils ±1mil
METALLIZATION:
Type: Al Si Cu
Thickness: 16.0kű2kÅ
SUBSTRATE POTENTIAL:
Unbiased (DI)
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2)
Nitride Thickness: 4.0kű 0.5kÅ
Silox Thickness: 12.0kű 1.3kÅ
WORST CASE CURRENT DENSITY:
Modified SEM
TRANSISTOR COUNT:
407
PROCESS:
Radiation Hardened Silicon Gate,
Bonded Wafer, Dielectric Isolation
Metallization Mask Layout
HS-1840ARH
IN7
IN6
IN5
IN4
IN3
IN2
IN1
ENABLE
A0
A1
A2
A3
VREF
GND
IN8
-V
OUT
+V
IN16
IN15
IN14
IN13
IN12
IN11
IN10
IN9
HS-1840ARH
5
HS-1840ARH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, a n dN/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
S S
-D-
-A-
-C-
eA
-B-
aaa C A - B
MD
S S
ccc C A - B
MD
S S
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
S2
M
A
D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C)
28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.232 - 5.92 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 1.490 - 37.85 -
E 0.500 0.610 12.70 15.49 -
e 0.100 BSC 2.54 BSC -
eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 5
S1 0.005 - 0.13 - 6
S2 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2
N28 288
Rev. 0 5/18/94
6
HS-1840ARH
Ceramic Metal Seal Flatpack Packages (Flatpack)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows f or off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness . The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-br azed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (be y ond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maxim um when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
-D-
-C-
0.004 H A - B
MD
S S
-A- -B-
0.036 H A - B
MD
S S
e
E
A
Q
L
D
A
E1
SEATING AND
LE2
E3 E3
BASE PLANE
-H-
b
C
S1
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
PIN NO. 1
ID AREA
A
M
K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)
28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.045 0.115 1.14 2.92 -
b 0.015 0.022 0.38 0.56 -
b1 0.015 0.019 0.38 0.48 -
c 0.004 0.009 0.10 0.23 -
c1 0.004 0.006 0.10 0.15 -
D - 0.740 - 18.80 3
E 0.460 0.520 11.68 13.21 -
E1 - 0.550 - 13.97 3
E2 0.180 - 4.57 - -
E3 0.030 - 0.76 - 7
e 0.050 BSC 1.27 BSC -
k 0.008 0.015 0.20 0.38 2
L 0.250 0.370 6.35 9.40 -
Q 0.026 0.045 0.66 1.14 8
S1 0.00 - 0.00 - 6
M - 0.0015 - 0.04 -
N28 28-
Rev. 0 5/18/94
