16-Bit, 200 MSPS/500 MSPS TxDAC+® with
2×/4×/8× Interpolation and Signal Processing
AD9786
Rev. B
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FEATURES
16-bit resolution, 200 MSPS input data rate
IMD 90 dBc @10 MHz
Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.3 LSB
INL = ±0.6 LSB
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single- or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
3.3 V-compatible digital interface
On-chip 1.2 V reference
80-lead, thermally enhanced, TQFP_EP package
APPLICATIONS
Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA,
IS136, TETRA
Instrumentation
RF signal generators, arbitrary waveform generators
HDTV transmitters
Broadband wireless systems
Digital radio links
Satellite systems
PRODUCT HIGHLIGHTS
1. 16-bit, high speed, interpolating TxDAC+.
2. 2×/4×/8× user-selectable interpolating filter. The filter
eases data rate and output signal reconstruction filter
requirements.
3. 200 MSPS input data rate.
4. Ultra high speed, 500 MSPS DAC conversion rate.
5. Flexible clock with single-ended or differential input.
CMOS, 1 V p-p sine wave, and LVPECL capability.
6. Complete CMOS DAC function. It operates from a 3.1 V
to 3.5 V single analog (AVDD) supply, 2.5 V digital supply,
and a 3.3 V digital (DRVDD) supply. The DAC full-scale
current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.
7. On-chip voltage reference. The AD9786 includes a
1.20 V temperature-compensated band gap voltage
reference.
8. Multichip synchronization. Multiple AD9786 DACs can
be synchronized to a single master AD9786 to ease timing
design requirements and optimize image reject transmit
performance.
FUNCTIONAL BLOCK DIAGRAM
16-BIT DAC
REFERENCE
CIRCUITS
CALIBRATION
SPI
ZERO
STUFF
HILBERT
Δt
090
090
Re()/Im()
2×2×2×
LATCH
Q
DATA
ASSEMBLER
DATA PORT
SYNCHRONIZER
fDAC/2
fDAC/4
fDAC/8
×1
CLOCK DISTRIBUTION AND CONTROL
CLK+
CLK–
DATACLK
P2B[15:0]
P1B[15:0]
FSADJ
REFIO
IOUTA
IOUTB
SDIO
SDO
CSB
SCLK
RESET
03152-001
090
2×2×2×
LATCH
I
Figure 1.
AD9786
Rev. B | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description......................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Dynamic Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Clock .............................................................................................. 9
Analog.......................................................................................... 10
Data .............................................................................................. 10
Serial Interface ............................................................................ 11
Terminology .................................................................................... 12
Typical Performance Characteristics ........................................... 14
Serial Control Interface.................................................................. 20
General Operation of the Serial Interface............................... 20
Serial Interface Port Pin Descriptions..................................... 20
MSB/LSB Transfers .................................................................... 21
Notes on Serial Port Operation ................................................ 21
Mode Control (via Serial Port)..................................................... 22
Digital Filter Specifications ........................................................... 26
Digital Interpolation Filter Coefficients.................................. 26
Clock/Data Timing .................................................................... 27
Real and Complex Signals......................................................... 32
Modulation Modes..................................................................... 33
Power Dissipation....................................................................... 38
Hilbert Transform Implementation......................................... 40
Operating the AD9786 Rev. F Evaluation Board ....................... 44
Power Supplies............................................................................ 44
PECL Clock Driver .................................................................... 44
Data Inputs.................................................................................. 45
Serial Port.................................................................................... 45
Analog Output............................................................................ 45
Outline Dimensions ....................................................................... 55
Ordering Guide .......................................................................... 55
AD9786
Rev. B | Page 3 of 56
REVISION HISTORY
10/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 1...........................................................................1
Changes to Table 2 ............................................................................6
Changes to Table 3 ............................................................................7
Changes to External Sync Mode Section .....................................31
Updated Outline Dimensions........................................................58
Changes to Ordering Guide...........................................................58
2/05—Rev. 0 to Rev. A
Changed DRVDD Supply Range...................................... Universal
Changes to DC Specifications .........................................................4
Changes to Dynamic Specifications ...............................................5
Changes to Digital Specifications....................................................6
Changes to Absolute Maximum Ratings........................................7
Change to Figure 2 ............................................................................8
Replaced Figure 13..........................................................................14
Replaced Figure 14..........................................................................14
Replaced Figure 16..........................................................................15
Replaced Figure 21..........................................................................16
Replaced Figure 22..........................................................................16
Replaced Figure 26..........................................................................16
Replaced Figure 27..........................................................................17
Changes to Table 15 ........................................................................22
Change to Figure 44........................................................................26
Replaced Figure 45..........................................................................26
Change to Figure 47........................................................................27
Change to Figure 48........................................................................27
Change to Figure 51........................................................................29
Change to Figure 52........................................................................29
Change to Figure 53........................................................................30
Change to DATAADJUST Synchronization Section..................31
Changes to Power Dissipation Section.........................................40
Changes to Table 37 ........................................................................42
Changes to Data Inputs Section ....................................................46
Change to Figure 88........................................................................49
Replaced Figure 95..........................................................................55
Updated Outline Dimensions........................................................60
Changes to Ordering Guide...........................................................60
7/04—Revision 0: Initial Version
AD9786
Rev. B | Page 4 of 56
GENERAL DESCRIPTION
The AD9786 is a 16-bit, high speed, CMOS DAC with
2×/4×/8× interpolation and signal processing features tuned
for communications applications. It offers state-of-the-art
distortion and noise performance. The AD9786 was developed
to meet the demanding performance requirements of multicarrier
and third-generation base stations. The selectable interpolation
filters simplify interfacing to a variety of input data rates while
also taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
The AD9786 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9786 is
manufactured on an advanced, low cost, 0.25 μm CMOS process.
AD9786
Rev. B | Page 5 of 56
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 16 Bits
DC Accuracy1
Integral Nonlinearity ±0.6 LSB
Differential Nonlinearity ±0.3 LSB
ANALOG OUTPUT
Offset Error ±0.015 ±0.0175 % of FSR
Gain Error (with Internal Reference) ±1.5 % of FSR
Full-Scale Output Current2 10 20 mA
Output Compliance Range –1.0 +1.0 V
Output Resistance 10 MΩ
REFERENCE OUTPUT
Reference Voltage 1.15 1.23 1.30 V
Reference Output Current3 1 μA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference Mode) 10 MΩ
Small Signal Bandwith 200 kHz
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift 0 ppm of FSR/°C
Gain Drift (with Internal Reference) ±4 ppm of FSR/°C
Reference Voltage Drift ±30 ppm/°C
POWER SUPPLY
AVDD1, AVDD2
Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (IAVDD1 + IAVDD2) 50 mA
IAVDD1 + IAVDD2 in Sleep Mode 18 mA
ACVDD, ADVDD
Voltage Range 2.35 2.5 2.65 V
Analog Supply Current (IACVDD + IADVDD) 2.5 mA
CLKVDD
Voltage Range 2.35 2.5 2.65 V
Clock Supply Current (ICLKVDD) 12 mA
DVDD
Voltage Range 2.35 2.5 2.65 V
Digital Supply Current (IDVDD) 52.5 mA
DRVDD
Voltage Range 3.1 3.3 3.5 V
Digital Supply Current (IDRVDD) 5.3 μA
Nominal Power Dissipation4 1.25 W
OPERATING RANGE –40 +85 °C
1 Measured at IOUTA driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32× the IREF current.
3 Use an external amplifier to drive any external load.
4 Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4× interpolation, fDAC/4 modulation, Hilbert off.
AD9786
Rev. B | Page 6 of 56
DYNAMIC SPECIFICATIONS
TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer
coupled output; 50 Ω doubly terminated, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Minimum DAC Output Update Rate 20 MHz
Maximum DAC Output Update Rate (fDAC) 500 MSPS
AC LINEARITY/BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS)
fDATA = 100 MSPS; fOUT = 5 MHz, 4×, 2× Interpolation 93 dBc
fDATA = 200 MSPS; fOUT = 10 MHz 85 dBc
fDATA = 200 MSPS; fOUT = 25 MHz 78 dBc
fDATA = 200 MSPS; fOUT = 50 MHz 78 dBc
Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS)
fDATA = 200 MSPS; fOUT1 = 5 MHz; fOUT2 = 6 MHz 85 dBc
fDATA = 200 MSPS; fOUT1 = 15 MHz; fOUT2 = 16 MHz 85 dBc
fDATA = 200 MSPS; fOUT1 = 25 MHz; fOUT2 = 26 MHz 84 dBc
fDATA = 200 MSPS; fOUT1 = 45 MHz; fOUT2 = 46 MHz 80 dBc
fDATA = 200 MSPS; fOUT1 = 65 MHz; fOUT2 = 66 MHz 78 dBc
fDATA = 200 MSPS; fOUT1 = 85 MHz; fOUT2 = 86 MHz 75 dBc
Noise Power Spectral Density (NPSD)
fDATA = 156 MSPS; fOUT = 10 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz −164 dBm/Hz
fDATA = 156 MSPS; fOUT = 50 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz −161 dBm/Hz
Adjacent Channel Power Ratio (ACLR)
WCDMA ACLR with 3.84 MHz BW, Single Carrier
IF = 21 MHz, fDATA = 122.88 MSPS, 4× Interpolation 80 dB
IF = 224.76 MHz, fDATA = 122.88 MSPS, 4× Interpolation, High-Pass Interpolation Filter Mode 72 dB
AD9786
Rev. B | Page 7 of 56
DIGITAL SPECIFICATIONS
TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 1.6 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current –10 +10 μA
Logic 0 Current –10 +10 μA
Input Capacitance 5 pF
CLOCK INPUTS1
Input Voltage Range 0 2.65 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
Latch Pulse Width (tLPW) 5 ns
Data Setup Time to DACCLK Out in Master Mode (tS) −0.5 ns
Data Hold Time to DACCLK Out in Master Mode (tH) 2.9 ns
1 See the Clock/Data Timing section for setup and hold times in various timing modes.
AD9786
Rev. B | Page 8 of 56
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter With Respect to Rating
AVDD1, AVDD2,
DRVDD
AGND1, AGND2,
ACGND, ADGND,
CLKGND, DGND
−0.3 V to +3.6 V
ACVDD, ADVDD,
CLKVDD, DVDD
AGND1, AGND2,
ACGND, ADGND,
CLKGND, DGND
−0.3 V to +2.8 V
AGND1, AGND2,
ACGND, ADGND,
CLKGND, DGND
AGND1, AGND2,
ACGND, ADGND,
CLKGND, DGND
−0.3 V to +0.3 V
REFIO, FSADJ AGND1 −0.3 to AVDD1 + 0.3
IOUTA, IOUTB AGND1 −1.0 to AVDD1 +0.3
P1B15 to P1B0,
P2B15 to P2B0, RESET
DGND −0.3 to DRVDD + 0.3
DATACLK DGND −0.3 to DRVDD + 0.3
CLK+, CLK− CLKGND −0.3 to CLKVDD + 0.3
CSB, SCLK,
SDIO, SDO
DGND −0.3 to DRVDD + 0.3
Junction
Temperature Range
−65°C to +125°C
Storage
Temperature
150°C
Lead Temperature
(10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type1 θ
JA Unit
80-lead TQFP_EP (Thermally Enhanced) 23.5 °C/W
`
1 With thermal pad soldered to PCB.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
AD9786
Rev. B | Page 9 of 56
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61
16
1
2
3
4
5
6
7
8
9
10
11
13
14
15
12
17
18
20
19
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PIN 1
IDENTIFIER
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DNC = DO NOT CONNECT
DNC
ADVDD
ADGND
ACVDD
ACGND
AVDD2
AGND2
AVDD1
AGND1
IOUTA
IOUTB
AGND1
AVDD1
AGND2
AVDD2
ACGND
ACVDD
ADGND
ADVDD
DNC
CLKVDD
DNC
CLKVDD
CLKGND
CLK+
CLK–
CLKGND
DGND
DVDD
P1B15
P1B14
P1B13
P1B12
P1B11
P1B10
DGND
DVDD
P1B9
P1B8
P1B7
FSADJ
REFIO
RESET
CSB
SCLK
SDIO
SDO
DGND
DVDD
P2B0
P2B1
P2B2
P2B3
P2B4
P2B5
DGND
P1B6
P1B5
P1B4
P1B3
DGND
DVDD
P1B2
P1B1
P1B0
DRVDD
IQSEL/P2B15
ONEPORTCLOCK/P2B14
P2B13
DGND
DVDD
DATACLK
AD9786
TOP VIEW
(Not to Scale)
DVDD
P2B6
P2B7
P2B8
P2B12
P2B11
P2B10
P2B9
03152-002
Figure 2. Pin Configuration
CLOCK
Table 6. Clock Pin Function Descriptions
Pin
No. Mnemonic Direction Description
5, 6 CLK+, CLK– I Differential Clock Input.
2 DNC Do Not Connect.
DCLKEXT
0x02[3] Mode
0 Pin configured for input of channel data rate or synchronizer clock. Internal clock
synchronizer can be turned on or off with DCLKCRC (0x02[2]).
31 DATACLK I/O
1 Pin configured for output of channel data rate or synchronizer clock.
1, 3 CLKVDD Clock Domain 2.5 V.
4, 7 CLKGND Clock Domain 0 V.
AD9786
Rev. B | Page 10 of 56
ANALOG
Table 7. Analog Pin Function Descriptions
Pin No. Mnemonic Direction Description
59 REFIO A Reference.
60 FSADJ A Full-Scale Adjust.
70, 71 IOUTB, IOUTA A Differential DAC Output Currents.
61 DNC Do Not Connect.
62, 79 ADVDD Analog Domain Digital Content 2.5 V.
63, 78 ADGND Analog Domain Digital Content 0 V.
64, 77 ACVDD Analog Domain Clock Content 2.5 V.
65, 76 ACGND Analog Domain Clock Content 0 V.
66, 75 AVDD2 Analog Domain Clock Switching 3.3 V.
67, 74 AGND2 Analog Domain Switching 0 V.
68, 73 AVDD1 Analog Domain Quiet 3.3 V.
69, 72 AGND1 Analog Domain Quiet 0 V.
80 DNC Do Not Connect.
DATA
Table 8. Data Pin Function Descriptions
Pin No. Mnemonic Direction Description
Input Data Port 1.
ONEPORT
0x02[6] Mode
0 Latched data routed for I channel processing.
10 to 15, 18 to
24, 27 to 29
P1B15 to P1B0 I
1 Latched data demultiplexed by IQSEL and routed for
interleaved I/Q processing.
ONEPORT
0x02[6]
IQPOL
0x02[1]
IQSEL/
P2B15 Mode (IQPOL = 0)
0 X X
Latched data routed to Q channel Bit 15
(MSB) processing.
1 0 0
Latched data on Data Port 1 routed to Q
channel processing.
1 0 1
Latched data on Data Port 1 routed to I
channel processing.
1 1 0
Latched data on Data Port 1 routed to I
channel processing.
32 IQSEL/P2B15 I
1 1 1
Latched data on Data Port 1 routed to Q
channel processing.
ONEPORT
0x02[6]
0 Latched data routed for Q channel Bit 14 processing.
33 ONEPORTCLOCK/P2B14 I/O
1 Pin configured for output of clock at twice the channel
data route.
34, 37 to 43,
46 to 51
P2B13 to P2B0 I Input Data Port 2, Bit 13 to Bit 0.
30 DRVDD Digital Output Pin Supply, 3.3 V.
9, 17, 26,
36, 44, 52
DVDD Digital Domain, 2.5 V.
8, 16, 25,
35, 45, 53
DGND Digital Domain, 0 V.
AD9786
Rev. B | Page 11 of 56
SERIAL INTERFACE
Table 9. Serial Interface Pin Function Descriptions
Pin No. Mnemonic Direction Description
CSB
SDIODIR
0x00[7] Mode
1 X High impedance.
0 0 Serial data output.
54 SDO O
0 1 High impedance.
CSB
SDIODIR
0x00[7] Mode
1 X High impedance.
0 0 Serial data output.
55 SDIO I/O
0 1 Serial data input/output depending on Bit 7 of the serial instruction byte.
56 SCLK I Serial Interface Clock.
57 CSB I Serial Interface Chip Select.
58 RESET I Resets entire chip to default state.
AD9786
Rev. B | Page 12 of 56
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normal-
ized to full scale, associated with a 1 LSB change in digital
input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1, minus the output when all inputs are set to 0.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temper ature Dri ft
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-sec.
Spurious-Free Dynamic Range (SFDR)
The difference between the rms amplitude of the output signal
and the amplitude of the peak spurious signal over the specified
bandwidth. The units are often in dBc (dB with respect to the
carrier).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that has
a sharp transition band near fDATA/2. Images that would typically
appear around fDAC (output data rate) can be greatly suppressed.
Pass Band
Frequency band in which any input applied therein passes
unattenuated to the DAC output.
Stop-Band Rejection
The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.
AD9786
Rev. B | Page 13 of 56
Group Delay
Number of input clocks between an impulse applied at the
device input and peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range
Impulse Response
Response of the device to an impulse applied to the input.
Adjacent Channel Leakage Ratio (ACLR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Complex Modulation
The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = ejwt =
coswt + jsinwt) and realizing real and imaginary components
on the modulator output.
Hilbert Transform
A function with unity gain over all frequencies, but with a phase
shift of 90° for negative frequencies and a phase shift of –90° for
positive frequencies. Although this function cannot be imple-
mented ideally, it can be approximated with a short FIR filter
with enough accuracy to be very useful in single sideband radio
architectures.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex modulator
in series with the first complex modulator, either the upper or
lower frequency image near the second IF can be rejected.
AD9786
Rev. B | Page 14 of 56
TYPICAL PERFORMANCE CHARACTERISTICS
TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer
coupled output; 50 Ω doubly terminated, unless otherwise noted.
03152-003
FREQUENCY (MHz) 800 10203040506070
SFDR (dBc)
0
120
100
80
60
40
20
0dBFS
–6dBFS –3dBFS
Figure 3. SFDR vs. Frequency, fDATA = 200 MSPS, 1× Interpolation
03152-004
FREQUENCY (MHz) 450 5 10 15 20 25 30 35 40
SFDR (dBc)
0
120
100
80
60
40
20
0dBFS
–6dBFS
–3dBFS
Figure 4. SFDR vs. Frequency, fDATA = 100 MSPS, 4× Interpolation
03152-005
FREQUENCY (MHz) 250 5 10 15 20
SFDR (dBc)
0
120
100
80
60
40
20
0dBFS
–6dBFS
–3dBFS
Figure 5. SFDR vs. Frequency, fDATA = 50 MSPS, 8× Interpolation
03152-006
FREQUENCY (MHz) 800 10203040506070
SFDR (dBc)
0
120
100
80
60
40
20
0dBFS
–6dBFS –3dBFS
Figure 6. SFDR vs. Frequency, fDATA = 200 MSPS, 2× Interpolation
03152-007
FREQUENCY (MHz) 600 1020304050
SFDR (dBc)
0
120
100
80
60
40
20
0dBFS
–6dBFS
–3dBFS
Figure 7. SFDR vs. Frequency, fDATA = 125 MSPS, 4× Interpolation
03152-008
FREQUENCY (MHz) 300 5 10 15 20 25
SFDR (dBc)
0
120
100
80
60
40
20
0dBFS
–6dBFS
–3dBFS
Figure 8. SFDR vs. Frequency, fDATA = 62.5 MSPS, 8× Interpolation
AD9786
Rev. B | Page 15 of 56
03152-009
FOUT (MHz) 800 102030 607040 50
SFDR (dBc)
50
90
80
85
75
70
65
60
55
0dBFS
–3dBFS
–6dBFS
Figure 9. Out-of-Band SFDR, fDATA = 200 MSPS, 2× Interpolation
03152-010
FOUT (MHz) 260200 220 2400 20 40 60 120 140 160 18080 100
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
0dBFS
–6dBFS
–3dBFS
Figure 10. Out-of-Band SFDR, fDATA = 125 MSPS, 4× Interpolation
03152-011
F
OUT
(MHz) 2600 20 40 60 120 140 160 180 200 220 24080 100
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
–6dBFS
0dBFS
–3dBFS
Figure 11. Out-of-Band SFDR, fDATA = 62.5 MSPS, 8× Interpolation
03152-012
ANALOG OUTPUT FREQUENCY (MHz)
010 304020
OUT OF BAND SFDR (dBc)
50
90
80
85
75
70
65
60
55
–6dBFS
–3dBFS
0dBFS
Figure 12. Out-of-Band SFDR, fDATA = 100 MSPS, 4× Interpolation
03152-013
ANALOG OUTPUT FREQUENCY (MHz) 250 5 10 15 20
OUT OF BAND SFDR (dBc)
90
80
75
85
70
65
60
55
50
0dBFS
–3dBFS
–6dBFS
Figure 13. Out-of-Band SFDR, fDATA = 50 MSPS, 8× Interpolation
03152-014
F
OUT
(MHz) 800 204060
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
–3dBFS
0dBFS
–6dBFS
Figure 14. Third-Order IMD vs. Frequency, fDATA = 160 MSPS, 1× Interpolation
AD9786
Rev. B | Page 16 of 56
03152-015
F
OUT
(MHz) 1600 20 40 60 120 14080 100
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
–6dBFS
0dBFS
–3dBFS
Figure 15. Third-Order IMD vs. Frequency, fDATA = 160 MSPS, 2× Interpolation
03152-016
F
OUT
(MHz) 2000 20 40 60 120 140 160 18080 100
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
0dBFS
–6dBFS
–3dBFS
Figure 16. Third-Order IMD vs. Frequency, fDATA = 200 MSPS, 2× Interpolation
03152-017
F
OUT
(MHz) 260200 220 2400 20 40 60 120 140 160 18080 100
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
0dBFS
–6dBFS
–3dBFS
Figure 17. Third-Order IMD vs. Frequency, fDATA = 125 MSPS, 4× Interpolation
03152-018
F
OUT
(MHz) 10002040 8060
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
–6dBFS
0dBFS
–3dBFS
Figure 18. Third-Order IMD vs. Frequency, fDATA = 200 MSPS,1x Interpolation
03152-019
F
OUT
(MHz) 2000 20 40 60 120 140 160 18080 100
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
0dBFS
–6dBFS
–3dBFS
Figure 19. Third-Order IMD vs. Frequency, fDATA = 100 MSPS, 4× Interpolation
03152-020
F
OUT
(MHz) 2000 20 40 60 120 140 160 18080 100
IMD (dBc)
50
100
90
95
85
80
75
70
65
60
55
0dBFS
–6dBFS
–3dBFS
Figure 20. Third-Order IMD vs. Frequency, fDATA = 50 MSPS, 8× Interpolation
AD9786
Rev. B | Page 17 of 56
03152-021
F
OUT
(MHz) 2600 204060 12010080 160140 180 200 220 240
IMD (dBc)
100
85
90
95
70
75
80
55
60
65
50
–6dBFS
0dBFS
–3dBFS
Figure 21. Third-Order IMD vs. Frequency, fDATA = 62.5 MSPS, 8× Interpolation
03152-022
CODE 655360 8192 16384 24576 49152 5734432768 40960
INL (LSBs)
–0.50
1.25
0.75
1.00
0.50
0.25
0
–0.25
Figure 22. Typical INL
03152-023
ANALOG OUTPUT FREQUENCY (MHz) 1600 20 40 60 120 14080 100
NOISE SPECTRAL DENSITY(dBm/Hz)
–180
–140
–150
–145
–155
–160
–165
–170
–175
F
DATA
= 156MSPS, 1× INTERPOLATION
F
DATA
= 156MSPS, 2× INTERPOLATION
Figure 23. Noise Spectral Density vs. Analog
Input Frequency, fDATA = 156 MSPS
03152-024
CODE 655360 8192 16384 24576 49152 5734432768 40960
DNL (LSBs)
–0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
Figure 24. Typical DNL
03152-025
ANALOG OUTPUT FREQUENCY (MHz) 800 102030 607040 50
NOISE SPECTRAL DENSITY(dBm/Hz)
–180
–140
–150
–145
–155
–160
–165
–170
–175
F
DATA
= 78MSPS, 1× INTERPOLATION
F
DATA
= 78MSPS, 2× INTERPOLATION
Figure 25. Noise Spectral Density vs. Analog
Input Frequency, fDATA = 78 MSPS
03152-026
ANALOG OUTPUT FREQUENCY (MHz) 800 10203040506070
NOISE SPECTRAL DENSITY (dBm/Hz)
–150
–158
–156
–154
–152
–164
–162
–160
–168
–166
–170
A
IN
= 0DBFS A
IN
= –3DBFS
A
IN
= –6DBFS
Figure 26. Noise Spectral Density vs. Analog Input Frequency,
fDATA = 78 MSPS, 2x Interpolation
AD9786
Rev. B | Page 18 of 56
03152-027
ANALOG OUTPUT FREQUENCY (MHz) 1600 20 40 60 80 100 120 140
NOISE SPECTRAL DENSITY (dBm/Hz)
–150
–158
–156
–154
–152
–164
–162
–160
–168
–166
–170
A
IN
= 0dBFS
A
IN
= –3dBFS
A
IN
= –6dBFS
Figure 27. Noise Spectral Density vs. Analog Input Frequency,
fDATA = 156 MSPS, 2x Interpolation
03152-028
F
OUT
(MHz) 1500 25 50 75 100 125
ACLR (dBc)
–90
–60
–65
–70
–75
–80
–85
–6dBFS
0dBFS –3dBFS
Figure 28. ACLR for First Adjacent Band vs. Frequency,
fDATA = 61.44 MSPS, 4× Interpolation
03152-029
F
OUT
(MHz) 2000 20 40 60 80 100 120 140 160 180
ACLR (dBc)
–90
–60
–65
–70
–75
–80
–85
–3dBFS
0dBFS
–6dBFS
Figure 29. ACLR for First Adjacent Band vs. Frequency,
fDATA = 76.8 MSPS, 4× Interpolation
Ref Lv1
10 dBm
Marker 1 [T1]
–87.73 dBm
9.71442886 MHz
RBW
VBW
SWT
10 kHz
10 kHz
5 s
RF Att
Unit
20 dB
dBm
A
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100
–110 START 100 kHz STOP 200 MHz19.9 MHz/
1MA
1
1AVG
Figure 30. Two Tones Around 23 MHz, fDATA = 200 MSPS,
2× Interpolation, Low-Pass Digital Filter Mode
03152-031
Ref Lv1
10 dBm
Marker 1 [T1]
–87.95 dBm
11.71743487 MHz
RBW
VBW
SWT
10 kHz
10 kHz
5 s
RF Att
Unit
20 dB
dBm
A
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110 START 100 kHz STOP 200 MHz19.9 MHz/
1MA
1
1AVG
Figure 31. Two Tones Around 177 MHz, fDATA = 200 MSPS,
2× Interpolation, High-Pass Digital Filter Mode
03152-032
SPAN 43.84MHz
SWEEP 142.2ms (601 pts)VBW 300kHz
CENTER 51.44MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–17.41dBm/
3.84MHz
FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz
20.000MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
3.840MHz
dBc
0.15
–74.24
–75.73
–75.67
dBm
–17.26
–91.65
–93.14
–93.08
LOWER dBc
–74.63
–75.67
–76.38
–75.75
dBm
–92.05
–93.08
–93.79
–93.17
UPPER
REF –29.82dBm
*AVG
Log
10dB/
PAVG
22
W1 S2
*ATTEN 6dB
AVERAGE
103
Figure 32. ACLR for Two WCDMA Carriers @ 51.44 MHz,
fDATA = 61.44 MSPS, 4× Interpolation
AD9786
Rev. B | Page 19 of 56
03152-033
SPAN 33.84MHz
SWEEP 109.8ms (601 pts)VBW 300kHz
CENTER 20.00MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–10.38dBm/
3.84 MHz
FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
dBc
–79.00
–80.78
–79.71
dBm
–89.38
–91.16
–90.09
LOWER dBc
–79.63
–81.77
–81.45
dBm
–90.01
–92.15
–91.83
UPPER
REF –22.76dBm
*AVG
Log
10dB/
PAVG
22
W1 S2
*ATTEN 8dB
AC-COUPLED
AVERAGE
22
Figure 33. ACLR for Single WCDMA Carrier @ 20 MHz,
fDATA = 61.44 MSPS, 4× Interpolation
03152-034
SPAN 33.84MHz
SWEEP 109.8ms (601 pts)VBW 300kHz
CENTER 142.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–15.30dBm/
3.84MHz
FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
dBc
–72.33
–72.41
–72.67
dBm
–87.64
–87.71
–87.97
LOWER dBc
–72.13
–73.02
–73.50
dBm
–87.43
–88.32
–88.88
UPPER
REF –28.2dBm
*AVG
Log
10dB/
PAVG
22
W1 S2
*ATTEN 6dB
AVERAGE
22
Figure 34. ACLR for Single WCDMA Carrier @ 142.88 MHz,
fDATA = 61.44 MSPS, 4× Interpolation
03152-035
SPAN 53.84MHz
SWEEP 174.6ms (601 pts)VBW 300kHz
CENTER 46.40MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–20.32dBm/
3.84MHz
FREQ OFFSET
5.000MHz
10.000MHz
15.000MHz
20.000MHz
25.000MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
dBc
0.22
–0.60
–72.68
–72.74
–73.05
dBm
–20.11
–20.92
–93.00
–93.06
–93.37
LOWER dBc
–0.16
–72.05
–72.85
–72.55
–72.02
dBm
–20.48
–92.37
–93.18
–92.88
–92.35
UPPER
REF –33.3dBm
*AVG
Log
10dB/
PAVG
104
W1 S2
*ATTEN 6dB
AVERAGE
104
AC-COUPLED
Figure 35. ACLR for Four WCDMA Carriers Near 50 MHz,
fDATA = 61.44 MSPS, 4× Interpolation
AD9786
Rev. B | Page 20 of 56
SERIAL CONTROL INTERFACE
AD9786 SPI
PORT INTERFACE
SDO (PIN 54)
SDIO (PIN 55)
S
CLK (PIN 56)
CSB (PIN 57)
03152-036
Figure 36. AD9786 SPI Port Interface
The AD9786 serial port is a flexible, synchronous serial commu-
nications port, allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI® and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9786. Single-
or multiple-byte transfers are supported, as well as MSB-first or
LSB-first transfer formats. The AD9786 serial interface port can
be configured as a single pin I/O (SDIO), or as two unidirectional
pins for input/output (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9786.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9786, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9786
serial port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines whether the upcoming data transfer is a
read or a write, the number of bytes in the data transfer, and the
starting register address for the first byte of the data transfer. The
first eight SCLK rising edges of each communication cycle are
used to write the instruction byte into the AD9786.
A logic high on the CSB pin, followed by a logic low, resets the
SPI port timing to the initial state of the instruction cycle. This
is true regardless of the present state of the internal registers or
the other signal levels present at the inputs to the SPI port. If the
SPI port is in the midst of an instruction cycle or a data transfer
cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9786
and the system controller. Phase 2 of the communication cycle
is a transfer of 1, 2, 3, or 4 data bytes, as determined by the instruc-
tion byte. Using one multibyte transfer is the preferred method.
Single-byte data transfers are useful to reduce CPU overhead
when register access requires one byte only. Registers change
immediately upon writing to the last bit of each transfer byte.
Instruction Byte
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation; Logic 0 indicates a write
operation. N1 and N0, Bit 6 and Bit 5 of the instruction byte,
determine the number of bytes to be transferred during the data
transfer cycle (see Table 10).
Table 10. Bytes Transferred During Data Transfer Cycle
N1 N2 Description
0 0 Transfer 1 byte
0 1 Transfer 2 bytes
1 0 Transfer 3 bytes
1 1 Transfer 4 bytes
The bit decodes are shown as follows:
MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0
R/W N1 N0 A4 A3 A2 A1 A0
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0) of
the instruction byte determine which register is accessed during
the data transfer portion of the communication cycle. For multibyte
transfers, this address is the starting byte address. The remaining
register addresses are generated by the AD9786.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock. The serial clock pin is used to
synchronize data to and from the AD9786 and to run the
internal state machines. The maximum frequency of SCLK
is 20 MHz. All data input to the AD9786 is registered on the
rising edge of SCLK. All data is driven out of the AD9786
on the falling edge of SCLK.
CSB—Chip Select. Active low input starts and gates a communi-
cation cycle. It allows more than one device to be used on the
same serial communication lines. The SDO and SDIO pins go
to a high impedance state when this input is high. Chip select
should stay low during the entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the
AD9786 on this pin. However, this pin can be used as a
bidirectional data line. The configuration of this pin is
controlled by Bit 7 of Register Address 0x00. The default is
Logic 0, which configures the SDIO pin as unidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9786 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
AD9786
Rev. B | Page 21 of 56
MSB/LSB TRANSFERS
The AD9786 serial port can support both MSB-first or LSB-first
data formats. This functionality is controlled by register address
DATADIR (0x00[6]). The default is MSB first. When this bit is
set active high, the AD9786 serial port is in LSB-first format.
That is, if the AD9786 is in LSB-first mode, the instruction byte
must be written from least significant bit to most significant bit.
Multibyte data transfers in MSB-first format can be completed
by writing an instruction byte that includes the register address
of the most significant byte. In MSB-first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB-first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB-first mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.
The AD9786 serial port controller address increments from 0x1F
to 0x00 for multibyte I/O operations if the MSB-first mode is
active. The serial port controller address decrements from 0x00 to
0x1F for multibyte I/O operations if the LSB-first mode is active.
NOTES ON SERIAL PORT OPERATION
The AD9786 serial port configuration bits reside in Bit 6 and
Bit 7 of Register Address 0x00. Note that the configuration
changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register might occur
during the middle of a communication cycle. Care must be
taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
The same considerations apply to setting the software reset
SWRST (0x00[5]) bit. All other registers are set to their default
values, but the software reset does not affect the bits in Register
Address 0x00 and Register Address 0x04.
It is recommended to use only single-byte transfers when
changing serial port configurations or initiating a software
reset.
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
03152-037
Figure 37. Serial Register Interface Timing MSB First
A0 A1 A2 A3 A4 N0 N1 R/W D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
03152-038
Figure 38. Serial Register Interface Timing LSB First
INSTRUCTION BIT 6INSTRUCTION BIT 7
CSB
SCLK
SDIO
t
DS
t
DS
t
DH
t
PWH
t
PWL
t
SCLK
03152-039
Figure 39. Timing Diagram for Register Write
DATA BIT n–1DATA BIT n
CSB
SCLK
SDIO
SDO
03152-040
t
DV
Figure 40. Timing Diagram for Register Read
AD9786
Rev. B | Page 22 of 56
MODE CONTROL (VIA SERIAL PORT)
Table 11.
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
COMMS 00 SDIODIR DATADIR SWRST SLEEP PDN EXREF
FILTER 01 INTERP[1] INTERP[0] ZSTUFF HPFX8 HPFX4 HPFX2
DATA 02 DATAFMT ONEPORT DCLKSTR DCLKPOL DCLKEXT DCLKCRC IQPOL CRAYDIN
MODULATE 03 CHANNEL HILBERT MODDUAL SIDEBAND MOD[1] MOD[0]
RESERVED 04 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
DCLKCRC 05 DATAADJ[3] DATAADJ[2] DATAADJ[1] DATAADJ[0] MODSYNC MODADJ[2] MODADJ[1] MODADJ[0]
06 Reserved
07 Reserved
08 Reserved
09 Reserved
0A Reserved
0B Reserved
0C Reserved
0D Reserved
CALMEMCK 0E CALMEM[1] CALMEN[0] CALCKDIV[2] CALCKDIV[2] CALCKDIV[2]
MEMRDWR 0F CALSTAT CALEN XFERSTAT XFEREN SMEMWR SMEMRD FMEMRD UNCAL
MEMADDR 10 MEMADDR[7] MEMADDR[6] MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]
MEMDATA 11 MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]
DCRCSTAT 12 DCRCSTAT[2] DCRCSTAT[1] DCRCSTAT[0]
Table 12.
COMMS(00) Bit Direction Default Description
SDIODIR 7 I 0 0: SDIO pin configured for input only during data transfer
1: SDIO configured for input or output during data transfer
DATADIR 6 I 0 0: Serial data uses MSB-first format
1: Serial data uses LSB-first format
SWRST 5 I 0 1: Default all serial register bits, except Address 0x00 and Address 0x04
SLEEP 4 I 0 1: DAC output current off
PDN 3 I 0 1: All analog and digital circuitry, except serial interface, off
EXREF 0 I 0 0: Internal band gap reference
1: External reference
Table 13.
FILTER(01) Bit Direction Default Description
INTERP[1:0] [7:6] I 00 00: No interpolation
01: Interpolation 2×
10: Interpolation 4×
11: Interpolation 8×
ZSTUFF 3 I 0 1: Zero stuffing on
HPFX8 2 I 0 0: ×8 interpolation filter configured for low-pass
1: ×8 interpolation filter configured for high-pass
HPFX4 1 I 0 0: ×4 interpolation filter configured for low-pass
1: ×4 interpolation filter configured for high-pass
HPFX2 0 I 0 0: ×2 interpolation filter configured for low-pass
1: ×2 interpolation filter configured for high-pass
AD9786
Rev. B | Page 23 of 56
Table 14.
DATA(02) Bit Direction Default Description
DATAFMT 7 I 0 0: Twos complement data format
1: Unsigned binary input data format
ONEPORT 6 I 0 0: I and Q input data onto Port 1 and Port 2, respectively
1: I and Q input data interleaved onto Port 1
DCLKSTR 5 I 0 0: DATACLK pin, 12 mA drive strength
1: DATACLK pin, 24 mA drive strength
DCLKPOL 4 I 0 0: Input data latched on DATACLK/DACCLK rising edge (dependent on mode)
1: Input data latched on DATACLK/DACCLK falling edge (dependent on mode)
DCLKEXT 3 I 0 0: DATACLK pin inputs channel data rate or modulator synchronizer clock
1: DATACLK pin outputs channel data rate or modulator synchronizer clock
DCLKCRC 2 I 0 0: With DATACLK pin as input, DATACLK clock recovery off
1: With DATACLK pin as input, DATACLK clock recovery on
IQPOL 1 I 0
0: In one-port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data
into Q channel
1: In one-port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data
into Q channel
GRAYDIN 0 I 0 0: Gray decoder off
1: Gray decoder on
Table 15.
MODULATE(03) Bit Direction Default Description
MODDUAL
0x03[5]
CHANNEL
0x03[7]
0 0 I channel processing routed to DAC
0 1 Q channel processing routed to DAC
1 0 Modulator real output routed to DAC
CHANNEL 7 I 0
1 1 Modulator imaginary output routed to DAC
HILBERT 6 I 0 1: With MODDUAL on, Hilbert transform on
MODDUAL 5 I 0 0: Modulator uses a single channel
1: Modulator uses both I and Q channels
SIDEBAND 4 I 0 0: With MODDUAL on, upper sideband rejected
1: With MODDUAL on, lower sideband rejected
MOD[1:0] [3:2] I 00 00: No modulation
01: fS/2 modulation
10: fS/4 modulation
11: fS/8 modulation
AD9786
Rev. B | Page 24 of 56
Table 16.
DCLKCRC(05) Bit Direction Default Description
DATAADJ[3:0] [7:4] I 0000
DATACLK offset (twos complement representation)
0111: +7
:
0000: 0
:
1000: −8
MODSYNC 3 I 00 0: Channel data rate clock synchronizer mode
1: State machine clock synchronizer mode
fS/8 fS/4 fS/2
000 1 1 1
001 +1/√2 0 –1
010 0 –1 1
011 –1/√2 0 –1
100 –1 +1 +1
101 –1/√2 0 –1
110 0 –1 +1
MODADJ[2:0] [2:0] I 000
111 +1/√2 0 –1
Modulator coefficient offset
Table 17.
VERSION(0D) Bit Direction Default Description
VERSION[3:0] [3:0] O Hardware version identifier
Table 18.
CALMEMCK(OE) Bit Direction Default Description
CALMEM [5:4] O 00 Calibration memory
00: Uncalibrated
01: Self-calibration
10: Factory calibration
11: User input
CALCKDIV[2:0] [2:0] I 00 Calibration clock divide ratio from channel data rate
000: /32
001: /64
:
110: /2048
111: /4096
Table 19.
MEMRDWR(OF) Bit Direction Default Description
CALSTAT 7 O 0 0: Self-calibration cycle not complete
1: Self-calibration cycle complete
CALEN 6 I 0 1: Self-calibration in progress
XFERSTAT 5 O 0 0: Factory memory transfer not complete
1: Factory memory transfer complete
XFEREN 4 I 0 1: Factory memory transfer in progress
SMEMWR 3 I 0 1: Write static memory data from external port
SMEMRD 2 I 0 1: Read static memory to external port
FMEMRD 1 I 0 1: Read factory memory data to external port
UNCAL 0 I 0 1: Use uncalibrated
AD9786
Rev. B | Page 25 of 56
Table 20.
MEMADDR(10) Bit Direction Default Description
MEMADDR [7:0] [7:0] I/O 00000000 Address of factory or static memory to be accessed
Table 21.
MEMDATA(11) Bit Direction Default Description
MEMDATA [5:0] [5:0] I/O 000000 Data or factory or static memory access
Table 22.
DCRCSTAT(12) Bit Direction Default Description
DCRCSTAT (2) 2 O 0 0: With DATACLK CRC on, lock has never been achieved
1: With DATACLK CRC on, lock has been achieved at least once
DCRCSTAT(1) 1 O 0 0: With DATACLK CRC on, system is currently not locked
1: With DATACLK CRC on, system is currently locked
DCRCSTAT(0) 0 O 0 0: With DATACLK CRC on, system is currently locked
1: With DATACLK CRC on, system lost lock due to jitter
AD9786
Rev. B | Page 26 of 56
DIGITAL FILTER SPECIFICATIONS
DIGITAL INTERPOLATION FILTER COEFFICIENTS
Table 23. Stage 1 Interpolation Filter Coefficients
Lower Coefficient Upper Coefficient Integer Value
H(1) H(43) 9
H(2) H(42) 0
H(3) H(41) –27
H(4) H(40) 0
H(5) H(39) 65
H(6) H(38) 0
H(7) H(37) –131
H(8) H(36) 0
H(9) H(35) 239
H(10) H(34) 0
H(11) H(33) –407
H(12) H(32) 0
H(13) H(31) 665
H(14) H(30) 0
H(15) H(29) –1070
H(16) H(28) 0
H(17) H(27) 1764
H(18) H(26) 0
H(19) H(25) –3273
H(20) H(24) 0
H(21) H(23) 10358
H(22) 16384
Table 24. Stage 2 Interpolation Filter Coefficients
Lower Coefficient Upper Coefficient Integer Value
H(1) H(19) 19
H(2) H(18) 0
H(3) H(17) –120
H(4) H(16) 0
H(5) H(15) 436
H(6) H(14) 0
H(7) H(13) –1284
H(8) H(12) 0
H(9) H(11) 5045
H(10) 8192
Table 25. Stage 3 Interpolation Filter Coefficients
Lower Coefficient Upper Coefficient Integer Value
H(1) H(11) 7
H(2) H(10) 0
H(3) H(9) –53
H(4) H(8) 0
H(5) H(7) 302
H(6) 512
03152-041
0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4
–
140
0
–20
–40
–60
–80
–
100
–
120
Figure 41. 2× Interpolation Filter Response
03152-042
0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4
–
140
0
–20
–40
–60
–80
–
100
–
120
Figure 42. 4× Interpolation Filter Response
03152-043
0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4
–
140
0
–20
–40
–60
–80
–
100
–
120
Figure 43. 8× Interpolation Filter Response
AD9786
Rev. B | Page 27 of 56
CLOCK/DATA TIMING
Table 26. Data Port Synchronization
DCLKEXT
0x02, Bit 3
MODSYNC
0x05, Bit 3
DCLKCRC
0x02, Bit 2 Mode Function
1 0 X DATACLK Master Channel data rate clock output
1 1 X Modulator Master
Modulator synchronization
DATACLK output
0 0 0 External Sync Mode DATACLK inactive, DACCLK
synchronous with external data
0 0 1 DATACLK Slave
DATACLK input, data rate clock,
data recovery on
0 1 0 Low Setup/Hold DATACLK input, input data
synchronous with DATACLK
0 1 1 Modulator Slave
Input modulator synchronizer
DATACLK input
Two-Port Data Input Mode (DATACLK Master)
With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same frequency.
Note that DACCLK refers to the differential clock inputs applied
at Pin 5 and Pin 6. As Figure 44 and Figure 45 show, there is a
constant delay between the edges of DACCLK and DATACLK.
The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be
latched into the AD9786 upon either the rising or falling edge
of DACCLK. With DCLKPOL = 0, the data is latched in upon
the falling edge of DACCLK, as shown in Figure 44. With
DCLKPOL = 1, as shown in Figure 45, data is latched in upon
the rising edge of DACCLK. The setup and hold times are
always with respect to the latching edge of DACCLK.
03152-044
DACCLK
IN
DATACLK
OUT
DATA
t
12
t
D
= 6ns TYP
t
H
= 2.9ns MIN
t
S
= –0.5ns MIN
Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0
03152-045
DACCLK
IN
DATACLK
OUT
DATA
tD
= 5.5ns TYP
tH
= 2.9ns MIN
tS
= –0.5ns MIN
Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1
With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the digital
inputs of the AD9786 upon every other rising edge of DACCLK,
as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as
shown in Figure 47, the latching edge of DACCLK is the rising
edge that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is
the rising edge of DACCLK that occurs just before the rising edge
of DATACLK. The setup and hold time values are identical to
those in Figure 44 and Figure 45.
Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 46 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.
With the interpolation set to 4× or 8×, the DACCLK input
runs at 4× or 8× the speed of the DATACLK output. The data
is latched in upon a rising edge of DACCLK, similar to the
2× interpolation mode.
However, the latching edge is every fourth edge in 4× inter-
polation mode and every eighth edge in the 8× interpolation
mode. Similar to operation in the 2× interpolation mode, with
DCLKPOL = 0, the latching edge of DACCLK is the rising edge
that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, the latching edge of DACCLK is the rising
edge that occurs just before the rising edge of DATACLK.
The setup and hold time values are identical to those in 1×
and 2× interpolation.
AD9786
Rev. B | Page 28 of 56
03152-046
Figure 46. DATACLK Duty Cycle
03152-047
t
D
= 6ns TYP
t
H
= 2.9ns MIN
t
S
= –0.5ns MIN
DACCLK
IN
DATACLK
OUT
DATA
Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0
t
D
= 5ns TYP
t
S
= –0.5ns MIN
t
H
= 2.9ns MIN
DACCLK
IN
DATACLK
OUT
DATA
03152-048
Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1
DATACLK Slave Mode (Data Recovery On)
DATACLK (Pin 31) can be used as an input to synchronize
multiple AD9786s. A clock generated by an AD9786 operating
in master mode, or a clock from an external source, can be used
to drive DATACLK.
In this mode, two clocks are required to be applied to the
AD9786. A clock running at the DAC sample rate, referred to as
DACCLK, must be applied to the differential inputs (Pin 5 and
Pin 6) of the AD9786. As described previously, a clock at the
input sample rate must also be applied to Pin 31 (DATACLK).
An internal DLL synchronizes the two applied clocks. The
timing relationships between the input data, DATACLK, and
DACCLK are given in Figure 49 and Figure 50.
Note that DCLKPOL (Register 0x02, Bit 4) can be used to select
the edge of DACCLK upon which the input data is latched.
There is a defined setup-and-hold window with respect to input
data and the latching edge of DACCLK. There is also a required
timing relationship between DATACLK and DACCLK. This is
referred to in Figure 49 and Figure 50 as tST and tHT (setup and
hold for transition). For example, with DCLKPOL set to Logic 0,
the input data latches upon the first rising edge of DACCLK
that occurs more than 1.5 ns before the falling edge of DATACLK.
DACCLK should not be given a rising edge in the window of
500 ps to 1.5 ns before the latching edge (falling edge when
DCLKPOL = 0, rising edge when DCLKPOL = 1) of DATACLK.
Failure to account for this timing relationship could result in
corrupt data.
There are three status bits available for a read that allow the user
to verify DLL lock. These are Bit 0, Bit 1, and Bit 2 (DCRCSTAT) in
Register 0x12.
03152-049
DACCLK
IN
DATACLK
IN
DATA
t
HT
= 1.5ns MIN
t
S
= 0.0ns MIN
t
ST
= –500ps MIN
t
H
= 3.2ns MIN
Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0
03152-050
DACCLKIN
DATACLKIN
DATA
tHT = 2.0ns MIN
tS = 0.0ns MIN
tST = –1.0ns MIN
tH = 3.2ns MIN
Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1
AD9786
Rev. B | Page 29 of 56
Low Setup/Hold Mode
(DATACLK Input, Data Recovery Off)
Some applications might require that digital input data be
synchronized with the DATACLK input, rather than DACCLK.
For these applications, the AD9786 can be programmed for low
setup/hold mode by entering the values in Table 26 into the SPI
registers. With data recovery off and the MODSYNC bit set to
Logic 1, the AD9786 latches data in upon the rising or falling
edge of DATACLK input, depending on the state of DCLKPOL.
03152-051
t
HT
= 0.0ns MIN
t
S
= –1.1ns MIN
t
H
= 2.8ns MIN
DACCLK
IN
DATACLK
IN
DATA
t
ST
= 3.0ns MIN
Figure 51. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 0
03152-052
DACCLK
IN
DATACLK
IN
DATA
t
S
= –1.8ns MIN t
H
= 3.1ns MIN
t
HT
= 1.0ns MIN
t
ST
= 2.0ns MIN
Figure 52. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 1
External Sync Mode
In the external sync mode, the DATACLK is programmed as an
input but is not used. Applying a DATACLK input while in this
mode has no effect. The digital input data is synchronized solely
to the DACCLK input. With 1× interpolation, the data input is
latched upon every rising edge of DACCLK. The challenge is
that the user has no way of knowing exactly which edge is the
latching edge when the interpolating filters are in use. In 2×, 4×,
and 8× interpolation modes, the latching edge of DACCLK is
every 2nd, 4th, or 8th edge, respectively.
With the 2 ns keep-out window, shown in Figure 53, there is a
strong possibility of violating setup and hold times, especially at
high speeds. It is recommended that users sense the DAC output
noise floor for setup and hold violations. If setup and hold is violated,
DCLKPOL can be switched. The effect of switching the state of
DCLKPOL is that the latching edge is moved by one, two, or four
DACCLK cycles if the AD9786 is in 2×, 4×, or 8× interpolation
modes, respectively. Note that in this mode, the DATAADJ bits
have no effect.
03152-053
tS = –300ps MIN tH = 2.9ns MIN
DACCLKIN
DATA
Figure 53. External Sync Mode with 2× Interpolation
Note that when using the AD9786 in external sync mode with
1× interpolation, that functionality is identical to master mode,
except that DATACLK out is not available. That is, with
DATACLKPOL = 0, data is latched on the falling edge of DACCLK,
and with DATACLKPOL = 1, data is latched on the rising edge
of DACCLK.
DATAADJUST Synchronization
When designing the digital interface for high speed DACs, care
must be taken to ensure that the DAC input data meets setup
and hold requirements. Often, compensation must be used in
the clock delay path to the digital engine driving the DAC. The
AD9786 has the on-chip capability to vary the latching edge of
DACCLK. With the interpolation function enabled, this allows
the user the choice of multiple edges upon which to latch the
data. For instance, if the AD9786 is using 8× interpolation, the
user can latch from one of eight edges before the rising edge of
DATACLK, or seven edges after this rising edge. The specific
edge upon which data is latched is controlled by SPI Register
0x05, Bits 7:4. Table 27 shows the relationship of the latching
edge of DACCLK and DATACLK with the various settings of
the DATAADJ bits.
Table 27. DATAADJ Values for Latching Edge Sync
SPI Register 0x05
Bit 7 Bit 6 Bit 5 Bit 4 Latching Edge Write DATACLK
0 0 0 0 0
0 0 0 1 +1
0 0 1 0 +2
0 0 1 1 +3
0 1 0 0 +4
0 1 0 1 +5
0 1 1 0 +6
0 1 1 1 +7
1 0 0 0 –8
1 0 0 1 –7
1 0 1 0 –6
1 0 1 1 –5
1 1 0 0 –4
1 1 0 1 –3
1 1 1 0 –2
1 1 1 1 –1
AD9786
Rev. B | Page 30 of 56
Note that the data in Figure 44 to Figure 53 was taken with the
DATAADJ default of 0000. Changing the DATAADJ values allows
the user to select the specific edge of DACCLK upon which the
input data is latched. This can be done in master mode, but it
is most useful in slave mode. For more information on using
DATAADJ and MODADJ to synchronize multiple AD9786s,
see Analog Devices Application Note 747. Table 27 lists the values
available for 8× interpolation, which, in turn, provides a choice of
16 edges to sync data. With 4× interpolation, there is
a choice of eight edges, and the relevant values from Table 27
are 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These
options allow latching edge placement from +3 cycles to −4 cycles.
In 2× interpolation, four edges are available, and the relevant
values from Table 27 are 0000, 0100, 1000, and 1100. The
choices for DATAADJ are diminished to +1 cycle to –2 cycles.
Figure 54, Figure 55, and Figure 56 show the alignment for the
latching edge of DACCLK with 4× interpolation and different
settings for DATAADJ. In Figure 54, the AD9786 is in
DATACLK master mode. DATAADJ is set to 0000, with
DCLKPOL set to 0 so that the latching edge of DACCLK is
immediately before the rising edge of DATACLK. The data
transitions shown in Figure 54 are synchronous with the
DACCLK, so that DACCLK and input data are constant with
respect to each other.
The only visible change when DATAADJ is altered is that
DATACLK moves, indicating the latching edge has moved as
well. Note that in DATACLK master mode, when DATAADJ is
altered, the latching edge with respect to DATACLK remains
the same.
03152-054
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 54. DATAADJ = 0000
Figure 55 shows the same conditions, but with DATAADJ set to
1111. This moves DATACLK to the left in the plot, indicating that
it occurs one DACCLK cycle before it did in Figure 54; therefore,
the latching edge of DACCLK also occurs one cycle earlier.
03152-055
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 55. DATAADJ = 1111
Figure 56 shows the same conditions, with DATAADJ set
to 0001; therefore, DATACLK moves to the right in the plot.
This indicates that it occurs one DACCLK cycle after it did in
Figure 54; therefore, the latching edge of DACCLK also occurs
one cycle later.
03152-056
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 56. DATAADJ = 0001
AD9786
Rev. B | Page 31 of 56
Interpolation Modes
Table 28. Interpolation Modes
INTERP[1] INTERP[0] Mode
0 0 No interpolation
0 1 ×2 interpolation
1 0 ×4 interpolation
1 1 ×8 interpolation
Interpolation is the process of increasing the number of points
in a time domain waveform by approximating points between
the input data points on a uniform time grid. This produces
a higher output data rate. Applied to an interpolation DAC,
a digital interpolation filter is used to approximate the interpolated
points, having an output data rate increased by the interpolation
factor. Interpolation filter responses are achieved by cascading
individual digital filter banks, whose filter coefficients are given in
Table 23, Table 24, and Table 25. Filter responses are shown in
Figure 57, which shows the interpolation filters of the AD9786
under different interpolation rates, normalized to the input data
rate, fSIN.
The digital filter’s frequency domain response exhibits symmetry
about half the output data rate and dc. It causes images of the
input data to be shaped by the interpolation filter’s frequency
response. This has the advantage of causing input data images
that fall in the stop band of the digital filter to be rejected by
the stop-band attenuation of the interpolation filter, while input
data images falling in the interpolation filter pass band are passed.
In band-limited applications, the images at the output |of the
DAC must be limited by an analog reconstruction filter. The
complexity of the analog reconstruction filter is determined by
the proximity of the closest image to the required signal band.
Higher interpolation rates yield larger stop-band regions,
suppressing more input images and resulting in a much relaxed
analog reconstruction filter.
A DAC shapes its output with a sinc function, having a null at
the sampling frequency of the DAC. The higher the DAC sam-
pling rate compared to the input signal bandwidth, the less the
DAC sinc function shapes the output. The higher the
interpolation rate, the more input data images fall in the
interpolation filter stop band and are rejected; the bandwidth
between passed images is larger with higher interpolation
factors. The sinc function shaping is also reduced with a higher
interpolation factor.
Table 29. Sinc Shaping at Band Edge of Interpolation Filters
Mode
Sinc Shaping
@ 0.43 fSIN (dB) Bandwidth to First Image
No interpolation –2.8241 fSIN
×2 interpolation –0.6708 2 fSIN
×4 interpolation –0.1657 4 fSIN
×8 interpolation –0.0413 8 fSIN
–8 –6 –4 –2 –0 2468
–
150
–
100
–50
0
–8 –6 –4 –2 02468
–
150
–
100
–50
0
–8 –6 –4 –2 0 2 468
–
150
–
100
–50
0
–8 –6 –4 –2 02468
–
150
–
100
–50
0
NO INTERPOLATION
×4INTERPOLATION
×2INTERPOLATION
×8INTERPOLATION
SINCRESPONSE
f
SIN
f
SIN
f
SIN
f
SIN
INTERP[1] = 1
INTERP[0] = 1
INTERP[1] = 1
INTERP[0] = 0
INTERP[1] = 0
INTERP[0] = 1
INTERP[1] = 0
INTERP[0] = 0
03152-057
Figure 57. Interpolation Modes
AD9786
Rev. B | Page 32 of 56
REAL AND COMPLEX SIGNALS
A complex signal contains both magnitude and phase
information. Given two signals at the same frequency, if the
leading signal in phase is cosinusoidal and the lagging signal is
sinusoidal, information pertaining to the magnitude and phase of
a combination of the two signals can be derived; the combination
of the two signals can be considered a complex signal. The cosine
and sine can be represented as a series of exponentials, recalling
that a multiplication by j is a counterclockwise rotation about
the Re/Im plane. The phasor representation of a complex signal
with Frequency f is shown in Figure 58.
Im
Re
CRe
Im
A/2
A/2
A/2
A/2
FREQUENCY
0+f
–f
A
2πft
C = Ae
2πft
= Acos(2πft) + jAsin(2πft)
Acos(2πft) = A =
[
e
+j2πft
+ e
–j2πft
]
e
+j2πft
+ e
–j2πft
2A
2
Asin(2πft) = A =
[
je
+j2πft
+ e
–j2πft
]
e
+j2πft
+ e
–j2πft
2j A
2
03152-058
Figure 58. Complex Phasor Representation
The cosine term—referred to as the real in-phase, or I component,
of a complex signal—represents a signal on the real plane with
mirror symmetry about dc. The sine term—referred to as the
imaginary quadrature, or Q complex signal component—
represents a signal on the imaginary plane with mirror
asymmetry about dc.
The AD9786 has two channels of interpolation filters, allowing
both I and Q components to be shaped by the same filter transfer
function. The interpolation filter’s frequency response is a real
transfer function. Two DACs are required to represent a complex
signal. A single DAC can only synthesize a real signal. When a
DAC synthesizes a real signal, negative frequency components
fold onto the positive frequency axis. If the input to the DAC is
mirrored symmetrically about dc, the negative frequency
components fold directly onto the positive frequency compo-
nents in phase-producing, constructive signal summation. If
the input to the DAC is not mirrored symmetrically about dc,
negative frequency components might not be in phase with
positive frequency components, causing destructive signal
summation. Different applications might benefit from either
type of signal summation.
AD9786
Rev. B | Page 33 of 56
MODULATION MODES
Table 30. Single-Channel Modulation
MODDUAL CHANNEL MOD[1] MOD[0] Mode
0 0 0 0 I channel, no modulation
0 0 0 1 I channel, modulation by fDAC/2
0 0 1 0 I channel, modulation by fDAC/4
0 0 1 1 I channel, modulation by fDAC/8
0 1 0 0 Q channel, no modulation
0 1 0 1 Q channel, modulation by fDAC/2
0 1 1 0 Q channel, modulation by fDAC/4
0 1 1 1 Q channel, modulation by fDAC/8
Either channel of the AD9786 interpolation filter channels can
be routed to the DAC and modulated. In single-channel
operation, the input data can be modulated by a real sinusoid;
the input data and the modulating sinusoid contain both
positive and negative frequency components. A double side-
band output results when modulating two real signals. At the
DAC output, the positive and negative frequency components
add in phase, resulting in constructive signal summation.
As the modulating sinusoidal frequency becomes a larger
fraction of the DAC update rate, fDAC, the sinc function of the
DAC shapes the modulated signal bandwidth more, and the
first image moves closer.
Because the AD9786 interpolation filter pass band represents a
large portion of the input data Nyquist band, it is possible for
modulated signal bands to touch or overlap images if sufficient
interpolation is not used under certain modulation and
interpolation modes.
Figure 59 shows the effects of fDAC/8 modulation when using 8×
interpolation. Figure 60 to Figure 62 show the effects of real
modulation under all interpolation modes. The sinc shaping at
the corners of the modulated signal band and the bandwidth to
the first image for those cases whose pass bands do not touch or
overlap are tabulated.
Table 31. Synthesis Bandwidth vs. Interpolation Modes
Interpolation
Modulation None ×2 ×4 ×8
None fSIN 2 fSIN 4 fSIN 8 fSIN
fDAC/2 fSIN 2 fSIN 4 fSIN 8 fSIN
fDAC/4 Overlap Touching 2 fSIN 4 fSIN
fDAC/8 Overlap Overlap Touching 6 fSIN
Table 32. Modulated Pass-Band Edges Sinc Shaping
(Lower/Upper)
Interpolation
Modulation None ×2 ×4 ×8
None 0 0 0 0
–2.8241 –0.6708 –0.1657 –0.0413
fDAC/2 –0.0701 –1.1932 –2.3248 –3.0590
–22.5378 –9.1824 –6.1190 –4.9337
fDAC/4 Overlap Touching –0.2921 –0.5974
–1.9096 –1.3607
fDAC/8 Overlap Overlap Touching –0.0727
–0.4614
AD9786
Rev. B | Page 34 of 56
0
–fDAC
–7fDAC/8
–3fDAC/4
–5fDAC/8
–fDAC/2
–3fDAC/8
–fDAC/4
–fDAC/8
fDAC/8
fDAC/4
3fDAC/8
fDAC/2
5fDAC/8
3fDAC/4
7fDAC/8
fDAC
FILTERED INTERPOLATION IMAGES
fS/8 MODULATION
–fDAC
–7fDAC/8
–3fDAC/4
–5fDAC/8
–fDAC/2
–3fDAC/8
–fDAC/4
–fDAC/8
fDAC/8
fDAC/4
3fDAC/8
fDAC/2
5fDAC/8
3fDAC/4
7fDAC/8
fDAC
03152-059
Figure 59. Double Sideband Modulation
–8 –6 –4 –2 02468
–
150
–
100
–50
0NO INTERPOLATION
×2INTERPOLATION
f
SIN
f
SIN
×4 INTERPOLATION
f
SIN
×8 INTERPOLATION
f
SIN
INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1
INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1
INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1
INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1
–8–6–4–202468
–
150
–
100
–50
0
–8–6–4–202468
–
150
–
100
–50
0
–8 –6 –4 –202468
–
150
–
100
–50
0
03152-060
Figure 60. Real Modulation by fDAC/2 Under All Interpolation Modes
AD9786
Rev. B | Page 35 of 56
–8 –6 –4 –2 02468
–150
–100
–50
0NO INTERPOLATION
×2 INTERPOLATION
fSIN
×4 INTERPOLATION
×8 INTERPOLATION
INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0
–8 –6 –4 –2 0 2 468
–150
–100
–50
fSIN
INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0
–8 –6 –4 –2 0 2 4 6 8
–150
–100
–50
fSIN
INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0
–8 –6 –4 –2 0 2 4 6 8
–150
–100
–50
fSIN
INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0
03215-061
0
0
0
Figure 61. Real Modulation by fDAC/4 Under All Interpolation Modes
–8 –6 –4 –2 0 2 4 6 8
–150
–100
–50
0NO INTERPOLATION
×2 INTERPOLATION fSIN
fSIN
×4 INTERPOLATION
fSIN
×8 INTERPOLATION
fSIN
INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0
INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0
INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0
INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0
–8 –6 –4 –2 0 2468
–150
–100
–50
0
–8 –6 –4 –2 0 2468
–150
–100
–50
0
8– –6 –4 –2 02468
–150
–100
–50
0
03152-062
Figure 62. Real Modulation by fDAC/8 Under All Interpolation Modes
AD9786
Rev. B | Page 36 of 56
Table 33. Dual-Channel Complex Modulation
MODDUAL CHANNEL MOD[1] MOD[0] Mode
0 0 0 0 Real output, no modulation
0 0 0 1 Real output, modulation by fDAC/2
0 0 1 0 Real output, modulation fDAC/4
0 0 1 1 Real output, modulation fDAC/8
0 1 0 0 Image output, no modulation
0 1 0 1 Image output, modulation by fDAC/2
0 1 1 0 Image output, modulation by fDAC/4
0 1 1 1 Image output, modulation by fDAC/8
In dual-channel mode, the two channels can be modulated by
a complex signal, with either the real or imaginary modulation
result directed to the DAC. Assume initially, as in Figure 63,
that the complex modulating signal is defined for a positive
frequency only. This causes the output spectrum to be trans-
lated in frequency by the modulation factor only. No additional
sidebands are created as a result of the modulation process;
therefore, the bandwidth to the first image from the baseband
bandwidth is the same as the output of the interpolation filters.
Furthermore, pass bands do not overlap or touch. The sinc
shaping at the corners of the modulated signal band is tabulated
in Table 34. Figure 64, Figure 65, and Figure 66 show the effects
of complex modulation with varying interpolation rates.
Table 34. Complex Modulated Pass-Band Edges Sinc Shaping
(Lower/Upper)
Interpolation
Modulation None ×2 ×4 ×8
None 0 0 0 0
–2.8241 –0.6708 –0.1657 –0.0413
fDAC/2 –0.0701 –1.1932 –2.3248 –3.0590
–22.5378 –9.1824 –6.1190 –4.9337
fDAC/4 –0.4680 –0.0175 –0.2921 –0.5974
–6.0630 –3.3447 –1.9096 –1.3607
fDAC/8 –1.3723 –0.1160 –0.0044 –0.0727
–4.9592 –1.7195 –0.7866 –0.4614
–
f
DAC
–7
f
DAC
/8
–3
f
DAC
/4
–5
f
DAC
/8
–
f
DAC
/2
–3
f
DAC
/8
–
f
DAC
/4
–
f
DAC
/8
0
f
DAC
/8
f
DAC
/4
3f
DAC
/8
f
DAC
/2
5f
DAC
/8
3f
DAC
/4
7f
DAC
/8
f
DAC
FILTERED INTERPOLATION IMAGES
f
S
/8 MODULATION NO NEGATIVE
SIDEBAND
–
f
DAC
–7
f
DAC
/8
–3
f
DAC
/4
–5
f
DAC
/8
–
f
DAC
/2
–3
f
DAC
/8
–
f
DAC
/4
–
f
DAC
/8
0
f
DAC
/8
f
DAC
/4
3f
DAC
/8
f
DAC
/2
5f
DAC
/8
3f
DAC
/4
7f
DAC
/8
f
DAC
03152-063
Figure 63. Complex Modulation
AD9786
Rev. B | Page 37 of 56
03152-064
–8 –6 –4 –2 02468
–
150
–
100
–50
0
0
0
×2INTERPOLATION
×4INTERPOLATION
×8INTERPOLATION
f
SIN
–8 –6 –4 –2 0 2 468
–
150
–
100
–50
f
SIN
–8 –6 –4 –2 0 2 4 6 8
–
150
–
100
–50
f
SIN
INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1
INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1
INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1
Figure 64. Complex Modulation by fDAC/2 Under All Interpolation Modes
–8 –6 –4 –2 02 4 68
–
150
–
100
–50
0×2INTERPOLATION
×4INTERPOLATION
×8INTERPOLATION
f
SIN
INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0
–8 –6 –4 –2 0 2 4 6 8
–
150
–
100
–50
0
f
SIN
INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0
–8 –6 –4 –2 0 2 4 6 8
–
150
–
100
–50
0
f
SIN
INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0
03152-065
Figure 65. Complex Modulation by fDAC/4 Under All Interpolation Modes
–8 –6 –4 –2 0 2 4 68
–150
–100
–50
0×2INTERPOLATION
×4INTERPOLATION
×8INTERPOLATION
f
SIN
INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 1
–8 –6 –4 –2 0 2 4 68
–150
–100
–50
0
f
SIN
INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 1
–8 –6 –4 –2 0 2 4 68
–150
–100
–50
0
f
SIN
INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 1
03152-066
Figure 66. Complex Modulation by fDAC/8 Under All Interpolation Modes
AD9786
Rev. B | Page 38 of 56
POWER DISSIPATION
The AD9786 has seven power-supply domains: two 3.3 V
analog domains (AVDD1 and AVDD2), two 2.5 V analog
domains (ADVDD and ACVDD), one 2.5 V clock domain
(CLKVDD), and two digital domains (DVDD, which runs
from 2.5 V; and DRVDD, which runs from 3.3 V).
The current needed for the 3.3 V analog supplies, AVDD1 and
AVDD2, is consistent across speed and varying modes of the
AD9786. Nominally, the current for AVDD1 is 29 mA across all
speeds and modes, whereas the current for AVDD2 is 20 mA.
The current for the 2.5 V analog supplies and the digital
supplies varies depending on speed and mode of operation.
Figure 67, Figure 68, and Figure 69 show this variation. Note
that CLKVDD, ADVDD, and ACVDD vary with clock speed
and interpolation rate, but not with modulation rate.
03152-067
F
DATA
(MSPS) 2500 25 50 75 100 125 150 175 200 225
IDVDD (mA)
0
425
325
300
275
250
225
200
175
400
375
350
150
125
100
75
50
25
1×
2×
2× fs/4
2× fs/8
4×
4× fs/4
4× fs/8
8×
8× fs/4
8× fs/8
Figure 67. DVDD Supply Current vs. Clock Speed,
Interpolation, and Modulation Rates
03152-068
F
DATA
(MSPS) 2500 25 50 75 100 125 150 175 200 225
ICLKVDD (mA)
0
60
50
40
30
20
10
2×
1×
4×8×
Figure 68. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates
03152-069
F
DATA
(MSPS) 2500 25 50 75 100 125 150 175 200 225
IADVDD AND IACVDD (mA)
0
30
25
20
15
10
5
2×
1×
4×
8×
Figure 69. ADVDD and ACVDD Supply Current vs. Clock Speed
and Interpolation Rates
AD9786
Rev. B | Page 39 of 56
FILTERED INTERPOLATION IMAGES
f
S/8 MODULATION
f
S/4 MODULATION
–
f
DAC
–7
f
DAC/8
–3
f
DAC/4
–5
f
DAC/8
–
f
DAC/2
–3
f
DAC/8
–
f
DAC/8
000
f
DAC/8
f
DAC/4
3f
DAC/8
f
DAC/2
5f
DAC/8
3f
DAC/4
7f
DAC/8
f
DAC
–
f
DAC/4
–
f
DAC
–7
f
DAC/8
–3
f
DAC/4
–5
f
DAC/8
–
f
DAC/2
–3
f
DAC/8
–
f
DAC/8
f
DAC/8
f
DAC/4
3f
DAC/8
f
DAC/2
5f
DAC/8
3f
DAC/4
7f
DAC/8
f
DAC
–
f
DAC/4
–
f
DAC
–7
f
DAC/8
–3
f
DAC/4
–5
f
DAC/8
–
f
DAC/2
–3
f
DAC/8
–
f
DAC/8
f
DAC/8
f
DAC/4
3f
DAC/8
f
DAC/2
5f
DAC/8
3f
DAC/4
7f
DAC/8
f
DAC
–
f
DAC/4
03152-070
Figure 70. Complex Modulation with Negative Frequency Aliasing
Table 35. Dual Channel Complex Modulation with Hilbert
Hilbert Mode
0 Hilbert transform off
1 Hilbert transform on
When complex modulation is performed, the entire spectrum is
translated by the modulation factor. If the resulting modulated
spectrum is not mirrored symmetrically about dc when the
DAC synthesizes the modulated signal, negative frequency
components fall on the positive frequency axis and can cause
destructive summation of the signals, as shown in Figure 70. For
some applications, this can distort the modulated output signal.
Re
Im
f
Re
Im
f
Re
Im
f
Re
Im
f
0000
A/2 A/2
A/2
A/2
A
A
A/2
A/2A/2 A/2
A/2
A/2 A/2 A/2
X = Ae
j2π(f + fm)t
Y = Ae
j2π(f + fm)t – π/2
Z = HILBERT(Y) C = X – Z
03152-071
Figure 71. Negative Frequency Image Rejection
In Figure 71, Figure X represents a complex signal typically
found in the AD9786 signal path. Figure Y is identical to Figure X,
but it is shifted by π/2. The phase shifting in the AD9786 occurs
because the digital LO driving the digital quadrature modulator
in the Hilbert transform path is phase shifted by π/2.
The operation of the Hilbert transform (Figure Z) rotates the
negative frequency components of Figure Y by +π/2, and the
positive frequency components of Figure Y by −π/2. The result
of the Hilbert transform output is then summed with the complex
signal in the main signal path. The result is that negative frequen-
cies are cancelled and, therefore, do not fold back into the
positive side of the frequency spectrum. The Δt block in the main
signal path offsets the delay inherent in the Hilbert transform
(nine DAC clock cycle delay). When the DAC synthesizes the
modulated output, there are no negative frequency components to
fold onto the positive frequency axis out of phase; consequently,
no distortion is produced as a result of the modulation process.
03152-072
ALIASED NEGATIVE FREQUENCY INTERPOLATION IMAGES
0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4
dBFS
–150
0
–50
–100
Figure 72. Negative Frequency Aliasing Distortion
AD9786
Rev. B | Page 40 of 56
Figure 72 shows this effect at the DAC output for a signal
mirrored asymmetrically about dc that is produced by complex
modulation without a Hilbert transform. The signal bandwidth
was narrowed to show the aliased negative frequency
interpolation images.
In contrast, Figure 73 shows the same waveform with the
Hilbert transform applied. Clearly, the aliased interpolation
images are not present.
03152-073
0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4
dBFS
–150
0
–50
–100
Figure 73. Effects of Hilbert Transform
If the output of the AD9786 is used with a quadrature modulator,
negative frequency images are cancelled without the need for
a Hilbert transform.
HILBERT TRANSFORM IMPLEMENTATION
The Hilbert transform on the AD9786 is implemented as a
19-coefficient FIR. The coefficients are given in Table 36.
Table 36.
Coefficient Integer Value
H(1) –6
H(2) 0
H(3) –17
H(4) 0
H(5) –40
H(6) 0
H(7) –91
H(8) 0
H(9) –318
H(10) 0
H(11) +318
H(12) 0
H(13) +91
H(14) 0
H(15) +40
H(16) 0
H(17) +17
H(18) 0
H(19) +6
The transfer function of an ideal Hilbert transform has a +90°
phase shift for negative frequencies, and a –90° phase shift for
positive frequencies. Because of the discontinuities that occur at
0 Hz and at 0.5 × the sample rate, any real implementation of
the Hilbert transform trades off bandwidth vs. ripple.
Figure 74 and Figure 75 show the gain of the Hilbert transform
vs. frequency. Gain is essentially flat, with a pass-band ripple of
0.1 dB over the frequency range of 0.07 × the sample rate to
0.43 × the sample rate.
Figure 76 shows the phase response of the Hilbert transform
implemented in the AD9786. The phase response for positive
frequencies begins at –90° at 0 Hz, followed by a linear phase
response (pure time delay) equal to nine filter taps (nine
DACCLK cycles). For negative frequencies, the phase response
at 0 Hz is +90°, followed by a linear phase delay of nine filter
taps. To compensate for the unwanted 9-cycle delay, an equal
delay of nine taps is used in the AD9786 digital signal path
opposite the Hilbert transform. This delay block is shown as Δt
in the Functional Block Diagram (Figure 1).
03152-074
1000100 200 300 400 500 600 700 800 900
–100
10
–20
–60
0
–40
–30
–70
–80
–90
–10
–50
Figure 74. Hilbert Transform Gain
03152-075
1000100 200 300 400 500 600 700 800 900
–
1.0
1.0
0.4
–
0.4
0.8
0
0.2
–
0.6
–
0.8
0.6
–
0.2
Figure 75. Hilbert Transform Ripple
AD9786
Rev. B | Page 41 of 56
03152-076
1200100 200 400 600 800 1000
–4
4
3
–1
1
2
–2
–3
0
Figure 76. Phase Response of Hilbert Transform
Table 37. Dual Channel Complex Modulation Sideband Selection
Sideband Mode
0 Upper IF sideband rejected
1 Lower IF sideband rejected
090
AD9786
AD9786
LO
I
QIm()
Re()
03152-077
Figure 77. AD9786 Driving Quadrature Modulator
The AD9786 can be configured to drive a quadrature modulator,
as in Figure 77. When two AD9786s are used with one AD9786
producing the real output, the second AD9786 produces the
imaginary output. By configuring the AD9786 as a complex
modulator coupled to a quadrature modulator, IF image
rejection is possible. The quadrature modulator acts as the real
part of a complex modulation, producing a double sideband
spectrum at the local oscillator (LO) frequency with mirror
symmetry about dc.
A baseband double sideband signal modulated to IF increases
IF filter complexity and reduces power efficiency. If the base-
band signal is complex, a single sideband IF modulation can be
used, relaxing IF filter complexity and increasing power
efficiency.
The AD9786 has the ability to place the baseband single side-
band complex signal either above or below the IF frequency.
Figure 78, Figure 79, and Figure 80 illustrate this.
03152-078
0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4
dBFS
–150
0
–50
–100
Figure 78. Upper IF Sideband Rejected
03152-079
0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4
dBFS
–150
0
–50
–100
Figure 79. Lower IF Sideband Rejected
00
f
IF
–f
IF
–
f
IF
f
IF
0
–
f
IF
f
IF
BASEBAND IF
SIDEBAND = 1
SIDEBAND = 0
03152-080
Figure 80. IF Quadrature Modulation of Real and Complex Baseband Signals
AD9786
Rev. B | Page 42 of 56
Master/Slave, Modulator/DATACLK Master Modes
In applications where two or more AD9786s are used to synthe-
size several digital data paths, it might be necessary to ensure
that the digital inputs to each device are latched synchronously.
In complex data processing applications, digital modulator phase
alignment might be required between two AD9786s. To allow
data synchronization and phase alignment, only one AD9786
should be configured as a master device, providing a reference
clock for another slave-configured AD9786.
With synchronization enabled, a reference clock signal is
generated on the DATACLK pin of the master. The DATACLK
pins on the slave devices act as inputs for the reference clock
generated by the master. The DATACLK pin on the master and
all slaves must be directly connected. All master and slave devices
must have the same clock source connected to their respective
CLK+/CLK– pins.
When configured as a master, the reference clock generated can
take one of two forms. In modulator master mode, the reference
clock is a square wave with a period equal to 16 cycles of the
DAC update clock. Internal to the AD9786 is a 16-state, finite
state machine, running at the DAC update rate. This state machine
generates all internal and external synchronization clocks and
modulator phasings. The rising edge of the master reference clock
is time aligned to state zero of the internal state machine. Slave
devices use the master reference clock to synchronize data latching
and align modulator phase by aligning state zero of the local
state machine to the master.
The second master mode, DATACLK master mode, generates a
reference clock that is at the channel data rate. In this mode, the
slave devices align their internal channel data rate clock to the
master. If modulator phase alignment is needed, a concurrent
serial write to all slave devices is necessary. To achieve this, the
CSB pin on all slaves must be connected together, and a group
serial write to the MODADJ register bits must be performed.
Following a successful serial write, the modulator coefficient
alignment is updated upon the next rising edge of the internal
state machine (see Figure 81). Modulator master mode does not
need a concurrent serial write, because slaves lock to the master
phase automatically.
In a slave device, the local channel data rate clock and the
digital modulator clock are created from the internal state
machine. The local channel data rate clock is used by the slave
to latch digital input data. At high data rates, the delay inherent
in the signal path from master to slave can cause the slave to lag
the master when acquiring synchronization. To accommodate
for this, an integer number of the DAC update clock cycles can
be programmed into the slave device as an offset. The value in
DATAADJ allows the local channel data rate clock in the slave
device to advance by up to eight cycles of the DAC clock, or to
be delayed by up to seven cycles (see Figure 82).
The digital modulator coefficients are updated at the DAC clock
rate and decoded in sequential order from the state machine
according to Figure 83. The MODADJ bits can be used to align
a different coefficient to the finite state machine’s zero state, as
shown in Figure 84.
DAC
CLOCK
STATE
MACHINE
STATE MACHINE
CHANNEL DATA
CYCLE CLOCK
RATE CLOCK
MODULATOR
COEFFICIENT
MODADJ 000 000
10–1010–1010–1010–10–1010–1010–1010–1010
01234567891011121314150123456789101112131415
03152-081
Figure 81. Synchronous Serial Modulator Phase Alignment
AD9786
Rev. B | Page 43 of 56
DATADJ[3:0]
DAC CLOCK
RECEIVED CHANNEL
DATA RATE CLOCK
LOCAL CHANNEL
DATA RATE CLOCK
0000 00011111
03152-082
–1 +1
Figure 82. Local Channel Data Rate Clock Synchronized with Offset
1
fs/2
STATE 2 3 4 5 6 7 8 9 10 11 12 13 4 1510
0 1
03152-083
DECODE 0 0 0 0 0 –1 0 0 0 0 01 1/ 2 –1/ 2 –1/ 2 –1/ 2
fs/4 1 2 30
fs/8 12345670
Figure 83. Digital Modulator State Machine Decode
MODADJ[2:0]
DAC CLOCK
STATE MACHINE
CYCLE CLOCK
000 101010
STATE
MACHINE
MODULATOR
COEFFICIENT
03152-084
–1 0 1 0 –1 0 0 –1 0 1 0 –1 0
14150123 1501 15012
Figure 84. Local Modulator Coefficient Synchronized with Offset
AD9786
Rev. B | Page 44 of 56
OPERATING THE AD9786 REV. F EVALUATION BOARD
This section provides information to power up the board and
verify correct operation; a description of more advanced modes
of operation has been omitted.
POWER SUPPLIES
The AD9786 Rev. F evaluation board has five power supply
connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD,
CLKVDD, and DVDD, whereas the AD9786 has seven power
supply domains. To reconcile the power supply domains on the
chip with the power supply connectors on the evaluation board,
use Table 38.
Additionally, the DRVDD power supply on the AD9786 is used
to supply power for the digital input bus. DRVDD should be
run from 3.3 V. On the evaluation board, DRVDD is jumper-
selectable by JP1, which is just to the left of the chip on the
evaluation board. With the jumper set to the 3.3 V position, the
DRVDD chip receives its power from VDD3IN.
PECL CLOCK DRIVER
The AD9786 system clock is driven from an external source via
Connector S1. The AD9786 evaluation board includes an
ON Semiconductor® MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CLKVDD power connector
or 3.3 V from the VDD3IN power connector. This setting is
done via Jumper JP2, situated next to the CLKVDD power
connector, and by setting Input Bias Resistor R23 and Input
Bias Resistor R4 on the evaluation board. The factory default is
for the PECL driver to be powered from CLKVDD at 2.5 V
(R23 = 90.9 Ω, R4 = 115 Ω). To operate the PECL driver with
a 3.3 V supply, R23 must be replaced with a 115 Ω resistor; R4
must be replaced with a 90.9 Ω resistor; and the position of JP2
must be changed. The schematic of the PECL driver section of
the evaluation board is shown in Figure 85. A low jitter sine
wave should be used as the clock source. Care must be taken to
ensure that the clock amplitude does not exceed the power
supply rails for the PECL driver.
03152-085
U2
71
2
COND;5
CLKVDDS;8
C32
0.1μF
R23
115Ω
R4
90.9Ω
A
CLK
X
CLKVDDS
R5
50Ω
R7
50Ω
R6
50Ω
CLKVDDS
MC100EPT22
CLK+
CLK–
Figure 85. PECL Driver on AD9786 Rev. F Evaluation Board
Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board
Evaluation Board Label/PS Domain on Chip
Nominal Power
Supply Voltage (V) Description
DVDD 2.5 SPI port
CLKVDD 2.5 Clock circuitry
ACVDD/ADVDD 2.5 Analog circuitry containing clock and digital interface circuitry
AVDD2 3.3 Switching analog circuitry
AVDD1 3.3 Analog output circuitry
AD9786
Rev. B | Page 45 of 56
DATA INPUTS
Digital data inputs to the AD9786 are accessed on the evaluation
board through Connector J1 and Connector J2. These are 40-pin,
right-angle connectors that are intended to be used with standard
ribbon cable connectors. The input level should be 3.3 V. The
data format is selectable through Register 0x02, Bit 7 (DATAFMT).
With this bit set to a default 0, the AD9786 assumes that the input
data is in twos complement format. With this bit set to 1, data
should be input in offset binary format.
When the evaluation board is first powered up and the clock
and data are running, it is recommended that the proper operating
current be verified. Press Reset Switch SW1 to ensure that the
AD9786 is in default mode. The default mode for the AD9786 is
for the interpolation set to 1×. The modulator is turned off in
default mode. The nominal operating currents for the evaluation
board in the power-up default mode are shown in Table 39.
Table 39. Nominal Operating Currents in Power-Up Default
Mode
Nominal Current @ Speed (mA)
Evaluation Board
Power Supply
50
MSPS
100
MSPS
150
MSPS
200
MSPS
DVDD 26 49 74 99
CLKVDD 78 83 87 92
ACVDD/ADVDD 1 4 6 8
AVDD1 30 30 30 30
AVDD2 27 27 27 27
Table 40. SPI Registers
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 0
0x01 INTERP[1] INTERP[0]
SERIAL PORT
SW1 is a hard reset switch that sets the AD9786 to its default
state. It should be used every time the AD9786 power supply is
cycled, the clock is interrupted, or new data is to be written via
the SPI port. Set the SPI software to read back data from the
AD9786, and then verify that the expected values are read back
when the software is run.
ANALOG OUTPUT
The analog output of the AD9786 is accessed via Connector S3.
Once all settings are selected and the current levels and SPI port
functionality are verified, the analog signal at S3 can be viewed.
For most of the AD9786 applications, a spectrum analyzer is the
preferred instrument to verify proper performance. A typical
spectral plot is shown in Figure 86, with the AD9786 synthesizing
a two-tone signal in the default mode with a 200 MSPS sample
rate. A single-tone CW signal should provide output power of
approximately +0.5 dBm to the spectrum analyzer.
If the spectrum does not look correct at this point, the data
input might be violating setup and hold times with respect to
the input clock. To correct this, the user should vary the input
data timing. If this is not possible, SPI Register 0x02, Bit 4
(DCLKPOL), can be inverted. This bit controls the clock edge
upon which the data is latched. If neither of these methods corrects
the spectrum, it is unlikely that the issue is timing related. In this
case, verify that all instructions have been followed correctly and
that the SPI port readback indicates the correct values.
03152-086
STOP 200MHzSTART 100MHz 19.9MHz/
0
–20
–10
–40
–30
–60
–50
–80
–70
–100
–90
–110
–120
1MA
A
0dBm
MARKER 1 [T1]
193.00170300MHz
–84.96dBm VBW
SWT
RBW 30kHz
560ms
30kHz
UNIT
RF ATT
dBm
20dB
REF LVL
1AVG
Figure 86. Typical Spectral Plot
AD9786
Rev. B | Page 46 of 56
S11 CGND;3,4,5
S9 AGND2; 3,4,5
S7 AGND2; 3,4,5
S5 DGND; 3,4,5
2
1
R7
50Ω
R5
50Ω
R6
50Ω
JP8
JP6
AVDD_IN
ADVDD2_IN
DVDD_IN
TP18
BLK
TP30 TP31 TP32 TP33 TP34
BLK BLKBLKBLKBLKBLKBLK
TP36
C28
4.7μF
6.3V
C75
0.1μF
JP33
2
1CGND; 5
CLKVDDS; 8
2
1
7
CLKVDDS
C35
0.1μF
JP30
C47
0.1μF
ADVDD
ACVDD
C76
0.1μF
C46
22μF
16V
C45
22μF
16V
C64
22μF
16V
C68
0.1μF
C63
22μF
16V
CLKVDDS; 8
CGND; 5
L9
FERRITE
TP13
RED
L8
FERRITE
L11
FERRITE
L12
FERRITE
TP1
RED
TP12
BLK
TP2
RED
TP3
BLK
L1
FERRITE
TP6
RED
TP5
BLK
C69
0.1μF
TP16
BLK
C48
0.1μF
AVD3
L2
FERRITE
TP4
RED AVD1
AVDD
L3
FERRITE
C65
22μF
16V
ACLKX
L6
FERRITE
CLKVDDS
C34
0.1μF
CLKVDDS
JP10
CVD
CLKVDD
JP5
JP36
TP7
BLK
ADVDD3_IN
C67
0.1μFC29
22μF
16V
R23
90.9Ω
TP35
JP34 DVDD
VDD
AVD2
JP9 AVDD2
L13
VAL
L10
VAL
L7
VAL
L14
VAL
JP7
CLKVDD_IN
TP17
BLK
CLK+
CLK–
DVDDS
DVDD AVDD2
DRVDD
SMAEDGE
SMAEDGE
SMAEDGE
SMAEDGE
SMAEDGE
AGND; 3,4,5
MC100EPT22
S10
+
+
+
+
+
+
JP1
AB
3
2
1
JP2
A
B
3
R4
115Ω
C32
0.1μFU2
+
4
3
6
MC100EPT22
U2
POWER INPUT FILTERS
2.5VQ
3.3VQ
3.3V
2.5VN
2.5V
03152-087
Figure 87. Power Supply Distribution, Rev. F Evaluation Board
AD9786
Rev. B | Page 47 of 56
03152-088
SPCSB
BD04
SPCLK
SPSDI
SPSDO
C6
10μF
6.3V
C22
0.001μF
C37
0.1μF
BD08
BD07
DVDD
BD06
BD05
BD03
BD02
BD01
BD00
RESET
TP11
WHT TP10
WHT
CLK+
CLK–
CLKCOM1
CLKCOM2
CLKVDD1
CLKVDD2
DCLK-PLLL
DCOM1
DCOM2
DCOM3
DCOM4
DRVDD1
DVDD1
DVDD2
DVDD3
DVDD4
LPF
P1B0LSB
P1B1
P1B10
P1B11
P1B12
P1B13
P1B14
P1B15MSB
P1B2
P1B3
P1B4
P1B5
P1B6
P1B7
P1B8
P1B9
P2B10
P2B11
P2B12
P2B13
P2B14-OPCLK
P2B15MSB-IQSEL
P2B9
ACCOM2P2
ACCOMP1
ACOM1P11
ACOM2P12
ACOM1P21
ACOM2P1
ACOM2P2
ACVDDP1
ACVDDP2
ADCOMP2
ADVDDP1
ADVDDP2
AVDD1P1
AVDD1P2
AVDD2P1
AVDD2P2
DCOM5
DCOM6
DNC1
DVDD5
DVDD6
FSADJ
IOUTA
IOUTB
P2B0LSB
P2B1
P2B2
P2B3
P2B4
P2B5
P2B6
P2B7
P2B8
REFIO
RESET
SP-CLK
SP-SDI
SP-SDO
SPI_CSB
DNC2
U1
AD9786BTSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TP8
WHT
+
C5
10μF
6.3V
C21
0.001μF
C38
0.1μF
DVDD
+
SW1
4
3
RESET 2
1
DRVDD
FLOAT; 5
C55
0.001μF
C20
0.001μF
C49
0.1μF
AVDD C18
0.001μF
C4
0.1μF
AVDD2
C62
0.1μFC61
0.001μF
C16
0.1μF
C30
10V
10μF
+R8
2kΩ
0.01%
C19
0.1μF
C14
0.1μFC2
10μF
6.3V
C17
0.1μF
C15
0.1μFC3
10μF
6.3V
+
+
C66
10μF
6.3V
+
ACVDD
ADTL1-12
P
S
46
31
ADVDD
R10
49.9Ω
R9
49.9Ω
T3
PS
6
3
1
5
4NC = 5
T2B
TTWB-1-B
R42
49.9Ω
OUT1S3
S8 TP29
BLK
C12
0.1μF
C1
10μF
6.3V
C11
0.1μFC42
0.1μFC27
1pF
+
C26
0.001μF
C10
10μF
6.3V
C40
0.1μF
+
BD09
BD10
BD11
BD12
BD13
AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
DVDD
C25
0.001μF
C9
10μF
6.3V
C41
0.1μF
+
DVDD
CLKVDD
CLKVDD
CLK– CLK+
R1
50Ω
4
1
2
3
5
6
T1
T1-1T
S1
CGND; 3,4,5
ACLKX
TP15
WHT
R2
10kΩ
C13
0.1μF
R3
10kΩ
C54
0.001μF
C33
0.1μF
C31
10μF
6.3V
+
DRVDD
C24
0.001μF
C8
10μF
6.3V
C39
0.1μF
+
DVDD
C23
0.001μF
C7
10μF
6.3V
C36
0.1μF
+
DVDD
TP14
WHT
S2
S4
S6
BD15
OPCLK_3
IQ
DATACLK
OPCLK
OPCLK
BD14
JP27
JP28 A
B
JP23
JP22
3
2
1
DGND; 3,4,5
DGND; 3,4,5
AGND; 3,4,5
AGND; 3,4,5
Figure 88. AD9786 Local Circuitry, Rev. F Evaluation Board
AD9786
Rev. B | Page 48 of 56
03152-089
R43
100Ω
R44
100Ω
R41
100Ω
R46
100Ω
R39
100Ω
R38
100Ω
R40
100Ω
R34
100Ω
R31
100Ω
R30
100Ω
R32
100Ω
R33
100Ω
R27
100Ω
R26
100Ω
R28
100Ω
R29
100Ω
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DATA-A
RIBBON
J1
AX07
AX06
AX05
AX04
AX15
AX14
AX13
AX12
AX00
AX01
AX02
AX03
AX08
AX09
AX10
AX11
JP21
JP19
21 345678910
R1 R2 R3 R4 R5 R6 R7 R8 R9
21 345678910
R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
RCOM
RP8
DNP
RP6
DNP
21 34567891021 345678910
R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
RCOM
RP7
DNP
RP5
DNP
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
AX15
AX14
AX13
AX12
AX11
AX10
AX09
AX08
AX07
AX06
AX05
AX04
AX03
AX02
AX01
AX00
116
215
314
413
512
611
710
89
116
215
314
413
512
611
710
89
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP1 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
RP2 22
JP3
JP12
Figure 89. Digital Data Port A Input Terminations, Rev. F Evaluation Board
AD9786
Rev. B | Page 49 of 56
03152-090
R49
100
Ω
R51
100
Ω
R47
100
Ω
R52
100
Ω
R54
100
Ω
R55
100
Ω
R53
100
Ω
R56
100
Ω
R58
100
Ω
R57
100
Ω
R59
100
Ω
R63
100
Ω
R61
100
Ω
R62
100
Ω
R60
100
Ω
R64
100
Ω
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DATA-B
RIBBON
J2
BX07
BX06
BX05
BX04
BX15
BX14
BX13
BX12
BX00
BX01
BX02
BX03
BX08
BX09
BX10
BX11
JP25
JP24
21 345678910
R1 R2 R3 R4 R5 R6 R7 R8 R9
21 345678910
R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
RCOM
RP10
DNP
RP11
DNP
21 34567891021 345678910
R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
RCOM
RP9
DNP
RP12
DNP
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
BD05
BD04
BD03
BD02
BD01
BD00
BX15
BX14
BX13
BX12
BX11
BX10
BX09
BX08
BX07
BX06
BX05
BX04
BX03
BX02
BX01
BX00
SDO
CLK
SDI
CSB
116
215
314
413
512
611
710
89
116
215
314
413
512
611
710
89
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP3 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
JP26
JP31
Figure 90. Digital Data Port B Input Terminations, Rev. F Evaluation Board
AD9786
Rev. B | Page 50 of 56
03152-091
DVDDS
OPCLK
DGND;8
DVDDS;16
1
2
3
6
5
15
4C53
0.1μF
C52
4.7μF
6.3V
C44
4.7μF
6.3V
C51
0.1μF
C43
4.7μF
6.3V
C50
0.1μF
R50
9kΩ
R48
9kΩ
R45
9kΩ
OPCLK_3
SPCSB
SPCLK
R20
10kΩ
SPSDI
R21
10kΩ
SPSDO
U5
12 13
11
9
10
DVDDS
8
3
5
4
2
1
6
PRE
CLR
Q
Q_
J
K
CLK
74LCX112
U7
74AC14
74AC14
74AC14
SPI PORT
P1
U5
U5
U5
21
3
5
4
6
74AC14
74AC14
74AC14
U5
U5
++
U6
13 12
10
8
11
9
74AC14
74AC14
74AC14
U6
U6
U6
12
4
6
3
5
74AC14
74AC14
74AC14
U6
U6
DGND;8
DVDDS;16
13
12
11
7
9
14
10
PRE
CLR
Q
Q_
J
K
CLK
74LCX112
U7
+
Figure 91. SPI and One-Port Clock Circuitry, Rev. F Evaluation Board
AD9786
Rev. B | Page 51 of 56
03152-092
Figure 92. PCB Assembly, Primary Side, Rev. F Evaluation Board
03152-093
Figure 93. PCB Assembly, Secondary Side, Rev. F Evaluation Board
AD9786
Rev. B | Page 52 of 56
03152-094
Figure 94. PCB Assembly, Layer 1 Metal, Rev. F Evaluation Board
03152-095
Figure 95. PCB Assembly, Layer 6 Metal, Rev. F Evaluation Board
AD9786
Rev. B | Page 53 of 56
03152-096
Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane),Rev. F Evaluation Board
03152-097
Figure 97. PCB Assembly, Layer 3 Metal (Power Plane),Rev. F Evaluation Board
AD9786
Rev. B | Page 54 of 56
03152-098
Figure 98. PCB Assembly, Layer 4 Metal (Power Plane), Rev. F Evaluation Board
03152-099
Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane), Rev. F Evaluation Board
AD9786
Rev. B | Page 55 of 56
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
0.27
0.22
0.17
1
20
21 40 40
6180 60
41
14.20
14.00 SQ
13.80 12.20
12.00 SQ
11.80
0.50 BSC
LEAD PITCH
0.75
0.60
0.45
1.20
MAX
1
20
21
61 80
60
41
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
0° MIN
7°
3.5°
0°
0.15
0.05
VIEW A
PIN 1
TOP VIEW
(PINS DOWN)
6.00
BSC SQ
BOTTOM VIEW
(PINS UP)
EXPOSED
PAD
Figure 100. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-80-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9786BSV −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786BSVRL −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786BSVZ1 −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786BSVZRL1 −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786-EB Evaluation Board
1 Z = Pb-free part.
AD9786
Rev. B | Page 56 of 56
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03152-0-10/05(B)
