128K x 16 Static RAM
CY7C1011BV33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-050 21 Rev. *A Revised June 6, 2001
Features
• 3.0 – 3.6V Operation
• High speed
—tAA = 12, 15 ns
• CMOS for optimum speed/power
• Low active pow er
—684 mW (Max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II
Functional Description
The CY7C1011BV33 is a high-performance CMOS static
RAM orga niz ed as 1 31, 072 words by 1 6 bit s. Th is dev ice has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the W rite
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appea r on I/O1 to I/O 8. If Byte High En able ( BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011BV33 is available in standard 44-pin TSOP
Type II package.
Logic Block Diagram
128K x 16
RAM Array I/O1–I/O8
ROW DECODER
A7
A6
A5
A4
A3
A0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
512 X 2048
SENSE AMPS
DATA IN DRIVERS
OE
A2
A1
I/O9–I/O16
CE
WE
BLE
BHE
A
8
1011B-1
A
15
A
16
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 2 of 10
Maximum Ratings
(Above w hi ch the useful life m ay be im pai red. For user guide-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1]......................................–0.5V to VCC+0.5V
DC Input Voltage[1] ..................................–0.5V to VCC+0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Pin Configuration
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top Vi e w
TSOP II
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
A4
A3
OE
VSS
A5
I/O16
A2
CE
I/O3
I/O1
I/O2
BHE
NC
A1
A0
1011B-2
18
17
20
19
I/O4
27
28
25
26
22
21 23
24 NC
VSS
I/O7
I/O5
I/O6
I/O8
A6
A7
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
A16
Selection Guide
1011BV33-12 1011BV33-15
Maximum Access Time (ns) Commercial 12 15
Maximum Operating Current (mA) Commercial 190 170
Maximum CMOS Standby Current (mA) Commercial 10 10
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C3.3V ± 10%
Electrical Characteristics Ov er the Op erating Range
Parameter Description Test
Conditions 1011BV33-12 1011BV33-15 UnitMin. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 0.4 V
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 3 of 10
VIH Input HIGH Voltage 2.2 2.2 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1+1 –1+1 µA
IOZ Output
Leakage
Current
GND < VI < VCC,
Output D isa bl ed –1+1 –1+1 µA
IOS Output Short
Circuit
Current[3]
VCC = Max.,
VOUT = GND –300 –300 mA
ICC VCC
Operating
Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
190 170 mA
ISB1 Automati c CE
Power-Down Current
—TTL Inputs
Max. VCC,
CE > VIH
VIN > VIH or
VIN < VIL,
f = fMAX
40 40 mA
ISB2 Automati c CE
Power-Down Current
—CMOS
Inputs
Max. VCC,
CE > VCC – 0.3V, VIN
> VCC – 0.3V,
or VIN < 0.3V, f = 0
10 10 mA
L0.5 0.5
Electrical Characteristics Ov er the Op erating Range (continued )
Parameter Description Test
Conditions 1011BV33-12 1011BV33-15 UnitMin. Max. Min. Max.
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 8pF
COUT Output Capacitance 8pF
AC Test Loads and W aveforms
Notes:
1. VIL (min.) = –2.0V for pulse durat ions of less than 20 ns.
2. TA is the “instant on” cas e temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
1011B-3
1011B-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R 481ΩR 481Ω
R2
255ΩR2
255Ω
167
Equivalent to: THÉVENIN
EQUIVALENT 1.73V
30 pF
Rise Time: 1 V/ns Fall Ti me:1 V/ns
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 4 of 10
Switching Characteristics[5] Over the Operating Range
Parameter Description 1011BV33-12 1011BV33-15 UnitMin. Max. Min. Max.
READ CYCLE
tRC Read Cyc le Time 12 15 ns
tAA Address to Data Valid 12 15 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 12 15 ns
tDOE OE LOW to Data Valid 6 7 ns
tLZOE OE LOW to Low Z[6] 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 6 7 ns
tLZCE CE LOW to Low Z[6] 3 3 ns
tHZCE CE HIGH to High Z[6, 7] 6 7 ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 12 15 ns
tDBE Byte Enable to Data Valid 6 7 ns
tLZBE Byte Enable to Low Z 0 0 ns
tHZBE Byte Disable to High Z 6 7 ns
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
IOL/IOH and 30-pF l oad capa citan ce.
6. At any given temperature and voltage condition, tHZCE is less tha n tLZCE, tHZOE is less than tLZOE, and tHZWE is less t han tLZWE for an y giv en dev ice.
7. tHZOE, tHZBE, tHZCE, an d tHZWE are sp ecifie d wit h a load capac itance o f 5 p F as i n part (b) o f AC Test Loads . T ran sition is m easured ±500 mV from steady-st ate voltag e.
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 5 of 10
WRITE CYCLE[8]
tWC Write Cycle Time 12 15 ns
tSCE CE LOW to Write End 10 12 ns
tAW Address Set-Up to Write End 10 12 ns
tHA Addr ess Ho ld from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 10 12 ns
tSD Data Set-Up to Write End 7 8 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[6] 3 3 ns
tHZWE WE LOW to High Z[6, 7] 6 7 ns
tBW Byte Enable to End of Write 10 12 ns
Switching Characteristics[5] Over the Operating Range
Parameter Description 1011BV33-12 1011BV33-15 UnitMin. Max. Min. Max.
Switching Waveforms
Note:
8. The internal write time of the memory is defined by the overlap of C E LO W, WE LOW and BHE / BLE LOW . CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
10. WE is HIGH for read c ycle.
Read Cycle No. 1
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
1011B-5
ADDRESS
DATA OUT
[9, 10]
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 6 of 10
Notes:
11. Address valid prior to or coincident with CE trans ition L OW .
12. Data I/O is high impedance if OE or BHE and/ or BLE= VIH.
13. If CE goe s HIGH simulta neously wi th WE going HIGH , th e outpu t remains in a high-i mpedanc e state.
Switching Waveforms (continued)
Read Cycle No. 2 (OEControlled)
1011B-6
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
[10, 11]
CURRENT
ICC
ISB
Write Cycle No. 1 (CE Controlled)
1011B-7
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATA I/O
ADDRESS
CE
WE
BHE, BLE
[12, 13]
t
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 7 of 10
Switching Waveforms (continued)
Write Cycle No. 2 (BLEor BHE Controlled)
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA I/O
ADDRESS
BHE,BLE
WE
CE
1011B-8
Write Cycle No. 3 (WE Controlled,OE LOW)
1011B-10
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 8 of 10
Truth Table
CE OE WE BLE BHE I/O1–I/O8I/O9–I/O16 Mode Power
H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read - All bits Active (ICC)
L H Data Out High Z Read - Lower bits only Active (ICC)
H L High Z Data Out Read - Upper bits only Active (ICC)
L X L L L Data In Data In Wr ite - All b its Active (ICC)
L H Data In High Z Write - Lower bits only Active (ICC)
H L High Z Data In Write - Upper bits only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disable d Active (ICC)
L X X H H High Z High Z Selected, Outputs Disable d Active (ICC)
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 CY7C1011BV33-12ZI Z44 44-Lead TSOP Type II Industrial
CY7C1011BV33-12ZC Z44 44-Lead TSOP Type II Commercial
15 CY7C1011BV33-15ZC Z44 44-Lead TSOP Type II Commercial
CY7C1011BV33-15ZI Z44 44-Lead TSOP Type II Industrial
Package Diagrams
44-Pin TSOP II Z44
51-85087-A
CY7C1011BV33
Document #: 38-05021 Rev. *A Page 10 of 10
Document Title: CY7C1011BV33 128K X 16 Static RAM
Document Numbe r: 38-050 21
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106652 04/26/01 MPR New Data Sheet
*A 107728 07/11/01 DFP Remov e S OJ T QF P Pac k age s. R emov e 8 , 10 ns . c ha nge d L ow Active Power
to 684. Change words/array/ added 2 addresses.
