CY7C1329H
2-Mbit (64 K × 32) Pipelined Sync SRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05673 Rev. *E Revised June 27, 2011
2-Mbit (64 K × 32) Pipelined Sync SRAM
Features
■Registered inputs and outputs for pipelined operation
■64 K × 32 common I/O architecture
■3.3 V core power supply
■2.5 V/3.3 V I/O operation
■Fast clock-to-output times
❐3.5 ns (for 166-MHz device)
❐4.0 ns (for 133-MHz device)
■Provide high-performance 3-1-1-1 access rate
■User-selectable burst counter supporting IntelPentium®
interleaved or linear burst sequences
■Separate processor and controller address strobes
■Synchronous self-timed write
■Asynchronous output enable
■Offered in JEDEC-standard lead-free 100-pin TQFP package
■“ZZ” Sleep Mode Option
Functional Description
The CY7C1329H[1] SRAM integrates 64 K × 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP
, and ADV), Write Enables (BW[A:D] and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
by the Byte Write control inputs. GW when active LOW causes
all bytes to be written.
The CY7C1329H operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 V or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
ADDRESS
REGISTER
ADV
CLK BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BWB
BW
C
BWD
BWA
MEMORY
ARRAY
DQs
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
D
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE DRIVER
DQ
B
BYTE
WRITE DRIVER
DQ
C
BYTE
WRITE DRIVER
DQ
D
BYTE
WRITE DRIVER
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 2 of 20
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Pin Definitions ..................................................................4
Functional Overview ........................................................5
Single Read Accesses ................................................5
Single Write Accesses Initiated by ADSP ................... 5
Single Write Accesses Initiated by ADSC ...................5
Burst Sequences ......................................................... 5
Sleep Mode .................................................................5
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................... 6
Linear Burst Address Table (MODE = GND) .................. 6
ZZ Mode Electrical Characteristics ................................. 6
Truth Table ........................................................................ 7
Truth Table for Read/Write .............................................. 8
Maximum Ratings .............................................................9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 12
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC Solutions ......................................................... 20
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CY7C1329H
Document #: 38-05673 Rev. *E Page 3 of 20
Selection Guide
166 MHz 133 MHz Unit
Maximum Access Time 3.5 4.0 ns
Maximum Operating Current 240 225 mA
Maximum CMOS Standby Current 40 40 mA
Pin Configuration
Figure 1. 100-pin TQFP Pinout
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/18M
NC/9M
A
A
A
A
A
A
NC/4M
NC
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
BYTE A
BYTE B
BYTE D
BYTE C
CY7C1329H
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CY7C1329H
Document #: 38-05673 Rev. *E Page 4 of 20
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the 2-bit
counter.
BWA,BWB,
BWC, BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled
on the rising edge of CLK.
GW Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write
is conducted (All bytes are written, regardless of the values on BW[A:D] and BWE).
BWE Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a Byte Write.
CLK Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new
external address is loaded.
CE2Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
CE3Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active
throughout this document for BGA. CE3 is sampled only when a new external address is loaded.
OE Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
OE is masked during the first clock of a Read cycle when emerging from a deselected state.
ADV Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automat-
ically increments the address in a burst cycle.
ADSP Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized.
ZZ Input-
Asynchronous
ZZ “sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
DQA, DQB
DQC, DQD
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by “A”
during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQ are placed in a tri-state condition.
VDD Power Supply Power supply inputs to the core of the device.
VSS Ground Ground for the core of the device.
VDDQ I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ I/O Ground Ground for the I/O circuitry.
MODE Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
NC No Connects. Not internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M and 1G are
address expansion pins and are not internally connected to the die.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 5 of 20
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1329H supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All Writes are simplified with on-chip synchronous
self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state to
a selected state, its outputs are always tri-stated during the first
cycle of the access. After the first cycle of the access, the outputs
are controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output will
tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the RAM array. The Write signals
(GW, BWE, and BW[A:D]) and ADV inputs are ignored during this
first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corresponding
address location in the memory array. If GW is HIGH, then the
Write operation is controlled by BWE and BW[A:D] signals. The
CY7C1329H provides Byte Write capability that is described in
the Write Cycle Descriptions table. Asserting the Byte Write
Enable input (BWE) with the selected Byte Write (BW[A:D]) input,
will selectively write to only the desired bytes. Bytes not selected
during a Byte Write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided to
simplify the Write operations.
Because the CY7C1329H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BW[A:D]) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
DQ is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write operations.
Because the CY7C1329H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1329H provides a two-bit wraparound counter, fed by
A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.Asserting ADV LOW at clock rise will
automatically increment the burst counter to the next address in
the burst sequence. Both Read and Write burst operations are
supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 6 of 20
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 40 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns
tZZI ZZ Active to sleep current This parameter is sampled – 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns
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CY7C1329H
Document #: 38-05673 Rev. *E Page 7 of 20
Truth Table [2, 3, 4, 5, 6, 7]
Next Cycle Address Used Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE
Unselected None None H X X L X L X X X
Unselected None None L L X L L X X X X
Unselected None None L X H L L X X X X
Unselected None None L L X L H L X X X
Unselected None None L X H L H L X X X
Begin Read External None X X X H X X X X X
Begin Read External External L H L L L X X X L
Continue Read Next External L H L L L X X X H
Continue Read Next External L H L L H L X L X
Continue Read Next External L H L L H L X H L
Continue Read Next External L H L L H L X H H
Suspend Read Current Next X X X L H H L H L
Suspend Read Current
Suspend Read Current Next X X X L H H L H H
Suspend Read Current Next H X X L X H L H L
Begin Write Current Next H X X L X H L H H
Begin Write Current Next X X X L H H L L X
Begin Write External Next H X X L X H L L X
Continue Write Next Current X X X L H H H H L
Continue Write Next Current X X X L H H H H H
Suspend Write Current Current H X X L X H H H L
Suspend Write Current Current H X X L X H H H H
ZZ “Sleep” None Current X X X L H H H L X
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a don't care
for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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CY7C1329H
Document #: 38-05673 Rev. *E Page 8 of 20
Truth Table for Read/Write [8, 9]
Function GW BWE BWDBWCBWBBWA
Read H H X X X X
Read HLHHHH
Write Byte A – DQAHLHHHL
Write Byte B – DQBHLHHLH
Write Bytes B, A H L H H L L
Write Byte C – DQCHLHLHH
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – DQDHLLHHH
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B H L L L L H
Write All Bytes H L L L L L
Write All Bytes L X X X X X
Notes
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
9. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 9 of 20
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up Current ................................................... > 200 mA
Operating Range
Range Ambient
Temperature VDD VDDQ
Commercial 0 °C to +70 °C 3.3 V– 5% /
+ 10%
2.5 V – 5% to
VDD
Industrial –40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter [10, 11] Description Test Conditions Min Max Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ I/O Supply Voltage for 3.3 V I/O 3.135 VDD V
for 2.5 V I/O 2.375 2.625 V
VOH Output HIGH Voltage for 3.3 V I/O, IOH = –4.0 mA 2.4 – V
for 2.5 V I/O, IOH = –1.0 mA 2.0 – V
VOL Output LOW Voltage for 3.3 V I/O, IOL = 8.0 mA – 0.4 V
for 2.5 V I/O, IOL = 1.0 mA – 0.4 V
VIH Input HIGH Voltage [10] for 3.3 V I/O 2.0 VDD + 0.3 V V
for 2.5 V I/O 1.7 VDD + 0.3 V V
VIL Input LOW Voltage [10] for 3.3 V I/O –0.3 0.8 V
for 2.5 V I/O –0.3 0.7 V
IXInput Leakage Current except
ZZ and MODE
GND VI VDDQ –5 5A
Input Current of MODE Input = VSS –30 –A
Input = VDD – 5 A
Input Current of ZZ Input = VSS –5 –A
Input = VDD –30 A
IOZ Output Leakage Current GND VI VDDQ, Output Disabled –5 5A
IDD VDD Operating Supply
Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
6-ns cycle,166 MHz –240 mA
7.5-ns cycle,133 MHz –225 mA
ISB1 Automatic CS Power-down
Current—TTL Inputs
VDD = Max,
Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz –100 mA
7.5-ns cycle,133 MHz –90 mA
ISB2 Automatic CS Power-down
Current—CMOS Inputs
VDD = Max,
Device Deselected,
VIN 0.3 V or
VIN > VDDQ – 0.3 V, f = 0
All speeds –40 mA
Notes
10. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
11. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 10 of 20
ISB3 Automatic CS Power-down
Current—CMOS Inputs
VDD = Max,
Device Deselected, or
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz –85 mA
7.5-ns cycle,133 MHz –75 mA
ISB4 Automatic CS Power-down
Current—TTL Inputs
VDD = Max,
Device Deselected,
VIN VIH or VIN VIL,
f = 0
All speeds –45 mA
Capacitance
Parameter [12] Description Test Conditions 100-pin TQFP
Max Unit
CIN Input Capacitance TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 5 pF
CCLK Clock Input Capacitance 5pF
CI/O Input/Output Capacitance 5pF
Thermal Resistance
Parameter [12] Description Test Conditions 100-pin TQFP
Package Unit
JA Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
30.32 C/W
JC Thermal Resistance
(Junction to Case)
6.85 C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
Electrical Characteristics
Over the Operating Range
Parameter [10, 11] Description Test Conditions Min Max Unit
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
V
T
= 1.5 V
3.3 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
OUTPUT
R = 1667
R =1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.25 V
2.5 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
3.3 V I/O Test Load
2.5 V I/O Test Load
Note
12. Tested initially and after any design or process change that may affect these parameters.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 11 of 20
Switching Characteristics
Over the Operating Range
Parameter [13, 14] Description 166 MHz 133 MHz Unit
Min Max Min Max
tPOWER VDD(Typical) to the First Access[15] 1–1–ms
Clock
tCYC Clock Cycle Time 6.0 – 7.5 – ns
tCH Clock HIGH 2.5 – 3.0 – ns
tCL Clock LOW 2.5 – 3.0 – ns
Output Times
tCO Data Output Valid after CLK Rise – 3.5 – 4.0 ns
tDOH Data Output Hold after CLK Rise 1.5 – 1.5 – ns
tCLZ Clock to Low Z [16, 17, 18] 0–0–ns
tCHZ Clock to High Z [16, 17, 18] – 3.5 – 4.0 ns
tOEV OE LOW to Output Valid – 3.5 – 4.5 ns
tOELZ OE LOW to Output Low Z [16, 17, 18] 0–0–ns
tOEHZ OE HIGH to Output High Z [16, 17, 18] – 3.5 – 4.0 ns
Set-up Times
tAS Address Set-up before CLK Rise 1.5 – 1.5 – ns
tADS ADSC, ADSP Set-up before CLK Rise 1.5 – 1.5 – ns
tADVS ADV Set-up before CLK Rise 1.5 – 1.5 – ns
tWES GW, BWE, BW[A:D] Set-up before CLK Rise 1.5 – 1.5 – ns
tDS Data Input Set-up before CLK Rise 1.5 – 1.5 – ns
tCES Chip Enable Set-Up before CLK Rise 1.5 – 1.5 – ns
Hold Times
tAH Address Hold after CLK Rise 0.5 – 0.5 – ns
tADH ADSP, ADSC Hold after CLK Rise 0.5 – 0.5 – ns
tADVH ADV Hold after CLK Rise 0.5 – 0.5 – ns
tWEH GW, BWE, BW[A:D] Hold after CLK Rise 0.5 – 0.5 – ns
tDH Data Input Hold after CLK Rise 0.5 – 0.5 – ns
tCEH Chip Enable Hold after CLK Rise 0.5 – 0.5 – ns
Notes
13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
14. Test conditions shown in (a) ofFigure 2 on page 10 unless otherwise noted.
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
can be initiated.
16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 10. Transition is measured ± 200 mV from steady-state voltage.
17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 12 of 20
Switching Waveforms
Figure 3. Read Cycle Timing [19]
Note
19. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 13 of 20
Figure 4. Write Cycle Timing [20, 21]
Switching Waveforms (continued)
Notes
20. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A : D] LOW.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 14 of 20
Figure 5. Read/Write Cycle Timing [22, 23, 24]
Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A2
tCEH
tCES
BWE,
BW[A:D]
Data Out (Q) High-Z
ADV
Single WRITE
D(A3)
A4 A5 A6
D(A5) D(A6)
Data In (D)
BURST READBack-to-Back READs
High-Z
Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)
tWEH
tWES
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
tCLZ
tCO
Back-to-Back
WRITEs
A1
DON’T CARE UNDEFINED
A3
Notes
22. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
23. The data bus (Q) remains in High Z following a Write cycle unless an ADSP
, ADSC, or ADV cycle is performed.
24. GW is HIGH.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 15 of 20
Figure 6. ZZ Mode Timing [25, 26]
Switching Waveforms (continued)
Notes
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in High Z when exiting ZZ sleep mode.
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CY7C1329H
Document #: 38-05673 Rev. *E Page 16 of 20
Ordering Code Definitions
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
133 CY7C1329H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial
Temperature Range:
C = Commercial
Pb-free
Package Type:
AX = 100-pin TQFP
Speed: 133 MHz
Process Technology: greater than or equal to 90 nm
1329 = SCD, 064 K × 32 (2 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1329 - 133 X7 CH A
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CY7C1329H
Document #: 38-05673 Rev. *E Page 17 of 20
Package Diagram
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA, 51-85050
51-85050 *D
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CY7C1329H
Document #: 38-05673 Rev. *E Page 18 of 20
Acronyms Document Conventions
Units of Measure
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TQFP thin quad flat pack
TTL transistor-transistor logic
Symbol Unit of Measure
°C degree Celsius
µA micro Amperes
µs micro seconds
mA milli Amperes
mm milli meter
ms milli seconds
mV milli Volts
mW milli Watts
MHz Mega Hertz
ns nano seconds
% percent
pF pico Farad
VVolts
WWatts
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CY7C1329H
Document #: 38-05673 Rev. *E Page 19 of 20
Document History Page
Document Title: CY7C1329H, 2-Mbit (64 K × 32) Pipelined Sync SRAM
Document Number: 38-05673
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 347357 See ECN PCI New Data Sheet
*A 424820 See ECN RXU Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from VIH < VDD to VIH VDD
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B
*B 433014 See ECN NXR Included 3.3V I/O option
Updated the Ordering Information table.
*C 2896585 03/20/2010 NJY Removed obsolete part numbers from Ordering Information table and updated
package diagrams.
*D 3052882 10/08/2010 NJY Removed obsolete part numbers from Ordering Information table and added
Ordering definitions.
*E 3293640 06/27/2011 NJY Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated in new template.
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Document #: 38-05673 Rev. *E Revised June 27, 2011 Page 20 of 20
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All products and company names mentioned in this
document may be the trademarks of their respective holders.
CY7C1329H
© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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