Document Number: MC33978
Rev. 8.0, 7/2018
NXP Semiconductors
Technical Data
© NXP B.V. 2018.
22 channel multiple switch detection
interface with programmable wetting
current
The 33978 is designed to detect the closing and opening of up to 22 switch
contacts. The switch status, either open or closed, is transferred to the
microprocessor unit (MCU) through a serial peripheral interface (SPI). This
SMARTMOS device also features a 24-to-1 analog multiplexer for reading the
input channels as analog inputs. The analog selected input signal is buffered and
provided on the AMUX output pin for the MCU to read.
Independent programmable wetting currents are available as needed for the
application. A battery and temperature monitor are included in the IC and
available via the AMUX pin.
The 33978 device has two modes of operation, Normal and Low-power mode
(LPM). Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors the change of state on
the switches. The LPM provides low quiescent current, which makes the 33978
ideal for automotive and industrial products requiring low sleep-state currents.
Features
• Fully functional operation 4.5 V ≤ VBATP ≤ 36 V
• Full parametric operation 6.0 V ≤ VBATP ≤ 28 V
• Operating switch input voltage range from -1.0 V to 36 V
• Eight programmable inputs (switches to battery or ground)
• 14 switch-to-ground inputs
• Selectable wetting current (2, 6, 8, 10, 12, 14, 16, or 20 mA)
• Interfaces directly to an MCU using 3.3 V / 5.0 V SPI protocol
• Selectable wake-up on change of state
• Typical standby current IBATP = 30 μA and IDDQ = 10 μA
• Active interrupt (INT_B) on change-of-switch state
• Integrated battery and temperature sensing
Figure 1. 33978 simplified application diagram
Notes
1. The IC is functional from 4.5 V < VBATP < 6.0 V, but with degraded parametric values. The parameters may not meet the minimum and maximum
specifications when VBATP drops below 6.0 V.
MULTIPLE SWITCH DETECTION INTERFACE
33978
34978
Applications
• Automotive
• Heating ventilation and air conditioning (HVAC)
• Lighting
• Central gateway/in-vehicle networking
• Gasoline engine management
• Industrial
• Programmable logic control (PLC)
• Process control, temperature control
• Input-output control (I/O Control)
• Single board computer
• Ethernet switch
EK SUFFIX (PB-FREE)
98ASA10556D
32-PIN SOICW-EP
ES SUFFIX (PB-FREE)
98ASA00656D
32-PIN QFN (WF-TYPE)
SP0
SG12
SG13
SG0
SP7
SP1
Battery
VBATP
VDDQ
MISO
MOSI
SCLK
AMUX
EP
GND
WAKE_B
Battery
Power
Supply
Power
Supply
VDDQ
MCU
MISO
MOSI
SCLK
AN0
INT_B
CS_B CSB
INTB
SG1
33978
NXP Semiconductors 2
33978
Table of Contents
1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 General IC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Battery voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Power sequencing conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 Input functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Oscillator and timer control functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Temperature monitor and control functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6 WAKE_B control functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.7 INT_B functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8 AMUX functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.9 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.10 SPI control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3 Abnormal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10 Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3NXP Semiconductors
33978
1 Orderable parts
This section describes the part numbers available to be purchased along with their differences.
Table 1. Orderable part variations
Part number Temperature (TA)Package Notes
MC33978EK
-40 °C to 125 °C
SOICW-EP 32 pins
(2), (3)
MC33978AEK
(2)
MC33978AES QFN (WF-TYPE) 32 pins
MC34978EK
-40 °C to 105 °C
SOICW-EP 32 pins
(2), (3)
MC34978AEK
(2)
MC34978AES QFN (WF-TYPE) 32 pins
Notes
2. To order parts in tape and reel, add the R2 suffix to the part number.
3. Refer to errata MC33978ER ER01 for details on current conditions present on the MC33978EK and MC34978EK devices only.
NXP Semiconductors 4
33978
2 Internal block diagram
Figure 2. 33978 internal block diagram
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
VBATP
To SPI
SG0
VBATP
4.0 V
reference
To SPI
SP0-7
Internal 2.5 V
VBATP
+
-
VDDQ
Inputs
SG0
SG2
SG1
SG13
SP7
SP0
SP1
AMUX
VBATP
VDDQ
GND
SCLK
MOSI
MISO
CS_B
WAKE_B
INT_B
Oscillator
and
Clock control
VBATP, VDDQ
Internal 2.5 V/5.0 V
Power On Reset
Bandgap reference
Sleep Power
Temperature
Monitor and
Control
SPI Interface and
Control
Internal 2.5 V
Internal 2.5 V
Internal 2.5 V
VDDQ
Mux control
24
Interrupt
control
VDDQ
125 kΩ
WAKE_B control
VDDQ
125 kΩ
Internal 2.5 V
VBATP
EP
Internal 2.5 V
4.0 V
reference
VBATP
To SPI
SGx
4.0 V
reference
VBATP
To SPI
SG5
4.0 V
reference
SG5
1/6 Ratio
VDDQ
125 kΩ
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (1.0 mA)
Wetting (2.0 mA to 20 mA)
Sustain (2.0 mA)
Low Power Mode (2.0 mA)
5NXP Semiconductors
33978
3 Pin connections
3.1 Pinout
Figure 3. 33978 SOICW-EP and QFN (WF-Type) pinouts
3.2 Pin definitions
Table 2. 33978 pin definitions
Pin number
SOIC
Pin number
QFN Pin name Pin function Formal name Definition
129 GND Ground Ground Ground for logic, analog
230 MOSI Input/SPI SPI Slave In SPI control data input pin from the MCU
331 SCLK Input/SPI Serial Clock SPI control clock input pin
432 CS_B Input/SPI Chip Select SPI control chip select input pin
5 – 8
25 – 28
1 - 4
21 - 24
S P 0 – 3
S P 4 – 7 Input Programmable
S w i t c h e s 0 – 7 Switch to programmable input pins (SB or SG)
9 – 15,
18 – 24
5 - 11
14 - 20
SG0 – 6,
SG7 –13 Input Switch-to-Ground
Inputs 0 – 13 Switch-to-ground input pins
16 12 VBATP Power Battery Input Battery supply input pin. Pin requires external reverse battery
protection
17 13 WAKE_B Input/Output Wake-up Open drain wake-up output. Designed to control a power supply
enable pin. Input used to allow a wake-up from an external event.
29 25 INT_B Input/Output Interrupt
Open-drain output to MCU. Used to indicate an input switch change
of state. Used as an input to allow wake-up from LPM via an external
INT_B falling event.
30 26 AMUX Output Analog Multiplex Output Analog multiplex output.
31 27 VDDQ Input Voltage Drain Supply 3.3 V/ 5.0 V supply. Sets SPI communication level for the MISO driver
and I/O level buffer
MISO
1
SP7
SP6
SP5
SP4
SG13
SG12
SG11
SG10
SG9
SG7
WAKE_B
SG8
INT_B
VDDQ
AMUX
GND
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG6
VBATP
SG5
CS_B
MOSI
SCLK
8
9
10
11
12
13
14
15
16
3
4
5
6
7
2
32
25
24
23
22
21
20
19
18
17
30
29
28
27
26
31
Exposed Pad
EK Suffix
Only
Transparent Top View
1
2
3
4
5
6
7
8
9 10111213141516
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VBATP
WAKE_B
SG7
SG8
SG9
SP7
SP6
SP5
SP4
SG13
SG12
SG11
SG10
CS_B
SCLK
MOSI
GND
MISO
VDDQ
AMUX
INT_B
NXP Semiconductors 6
33978
32 28 MISO Output/SPI SPI Slave Out Provides digital data from the 33978 to the MCU.
EP Ground Exposed Pad It is recommended that the exposed pad is terminated to GND (pin 1)
and system ground.
Table 2. 33978 pin definitions (continued)
Pin number
SOIC
Pin number
QFN Pin name Pin function Formal name Definition
7NXP Semiconductors
33978
4 General product characteristics
4.1 Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol Description (rating) Min. Max. Unit Notes
Electrical ratings
VBATP Battery Voltage -0.3 40 V
VDDQ Supply Voltage -0.3 7.0 V
CS_B, MOSI,
MISO, SCLK SPI Inputs/Outputs -0.3 7.0 V
SGx, SPx Switch Input Range -14(4) 38 V
AMUX AMUX -0.3 7.0 V
INT_B INT_B -0.3 7.0 V
WAKE_B WAKE_B -0.3 40 V
VESD1-2
VESD1-3
VESD3-1
VESD2-1
VESD2-2
ESD Voltage
• Human Body Model (HBM) (VBATP versus GND)
MC33978 and MC34978
MC33978A and MC34978A
• Human Body Model (HBM) (All other pins)
• Machine Model (MM)
• Charge Device Model (CDM) (Corners pins)
• Charge Device Model (CDM) (All other pins)
±2000
±4000
±2000
±200
±750
±500
V(5)
VESD5-3
VESD5-4
VESD6-1
VESD6-2
Contact Discharge
• VBATP(8)
• WAKE_B (series resistor 10 kΩ)
• SGx and SPx pins with 100 nF capacitor (100 Ω series R) based on external
protection performance(7)
• SGx and SPx pins with 100 nF capacitor (50 Ω series R)
±8000
±8000
±15000
±8000
V(6)
Notes
4. Minimum value of -18 V is guaranteed by design for switch input voltage range (SGx, SPx).
5. ESD testing is performed in accordance AEC Q100, with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model
(MM) (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM).
6. CZAP = 330 pF, RZAP = 2.0 kΩ (Powered and unpowered) / CZAP = 150 pF, RZAP = 330 Ω (Unpowered)
7. ±15000V capability in powered condition, ±8000V in all other conditions.
8. External component requirements at system level:
Cbulk = 100uF aluminum electrolytic capacitor
Cbypass= 100nF ±37 % ceramic capacitor
Reverse blocking diode from Battery to VBATP (0.6 V < VF < 1 V). See Figure 23, Typical application diagram.
NXP Semiconductors 8
33978
4.2 Thermal characteristics
Table 4. Thermal ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol Description (rating) Min. Max. Unit Notes
Thermal ratings
TA
TJ
Operating Temperature
• Ambient
•Junction
-40
-40
125
150
°C
TSTG Storage Temperature -65 150 °C
TPPRT Peak Package Reflow Temperature During Reflow – – °C
Thermal resistance
RΘJA
Junction-to-Ambient, Natural Convection, Single-Layer Board
• 32 SOIC-EP
• 32 QFN
79
94
°C/W (9),(10)
RΘJB
Junction-to-Board
• 32 SOIC-EP
• 32 QFN
9.0
12
°C/W (11)
RΘJC
Junction-to-Case (Bottom)
• 32 SOIC-EP
• 32 QFN
3.0
2.0
°C/W (12)
ΨJT
Junction-to-Package (Top), Natural convection
• 32 SOIC-EP
• 32 QFN
11
2.0
°C/W (13)
Package dissipation ratings
TSD
Thermal Shutdown
• 32 SOIC-EP
• 32 QFN
155 185 °C
TSDH
Thermal Shutdown Hysteresis
• 32 SOIC-EP
• 32 QFN
3.0 15 °C
Notes
9. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
10. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board,
respectively.
11. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
12. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.
13. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
9NXP Semiconductors
33978
4.3 Operating conditions
This section describes the operating conditions of the device. Conditions apply to the following data, unless otherwise noted.
4.4 Electrical characteristics
4.4.1 Static electrical characteristics
Table 5. Operating conditions
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol Ratings Min. Max. Unit Notes
VBATP Battery Voltage 4.5 36 V
VDDQ Supply Voltage 3.0 5.25 V
CS_B, MOSI,
MISO, SCLK SPI Inputs / Outputs 3.0 5.25 V
SGx, SPx Switch Input Range -1.0 36 V
AMUX, INT_B AMUX, INT_B 0.0 5.25 V
WAKE_B WAKE_B 0.0 36 V
Table 6. Static electrical characteristics
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Units Notes
Power input
VBATP(POR)
VBATP Supply Voltage POR
• VBATP Supply Power on Reset voltage. 2.7 3.3 3.8 V
VBATPUV VBATP Undervoltage Rising Threshold — 4.3 4.5 V
VBATPUVHYS VBATP Undervoltage Hysteresis 250 — 500 mV
VBATPOV VBATP Overvoltage Rising Threshold 32 — 37 V
VBATPOVHYS VBATP Overvoltage Hysteresis 1.5 — 3.0 V
IBAT(ON)
VBATP Supply Current
• All switches open, Normal mode, Tri-state disabled (all channels) —7.012mA
IBATP,IQ,LPM,P
IBATP,IQ,LPM,F
VBATP Low-power Mode Supply Current (polling disabled)
• Parametric VBATP, 6.0 V < VBATP < 28 V
• Functional Low VBATP, 4.5 V < VBATP < 6.0 V
—
—
—
—
40
40
µA
IPOLLING,IQ
VBATP Polling Current
• Polling 64 ms, 11 inputs of wake enabled ——20µA
(14)
IVDDQ,NORMAL
Normal mode (IVDDQ)
•SCLK, MOSI, WakeB = 0 V, CS_B, INT_B =VDDQ, no SPI
communication, AMUX selected no input
— — 500 uA
IVDDQ,LPM
Logic Low-power mode Supply Current
• SCLK, MOSI = 0 V, CS_B, INT_B, WAKE_B = VDDQ, no SPI
communication
——10µA
VGNDOFFSET
Ground Offset
• Ground offset of Global pins to IC ground -1.0 — 1.0 V
VDDQUV VDDQ Undervoltage Falling Threshold 2.2 — 2.8 V
VDDQUVHYS VDDQ Undervoltage Hysteresis 150 — 350 mV
NXP Semiconductors 10
33978
Switch input
ILEAKSG_GND
Leakage (SGx/SPx pins) to GND
• Inputs tri-stated, analog mux selected for each input, voltage at
SGx = VBATP
——2.0μA
ILEAKSG_BAT
Leakage (SGx/SPx pins) to Battery
• Inputs tri-stated, analog mux selected for each input, voltage at
SGx = GND
——2.0μA
ISUSSG
SG Sustain current / Mode 0 Wetting current
• VBATP 6.0 to 28 V 1.6 2.0 2.4 mA
ISUSSGLV
SG Sustain current / Mode 0 Wetting current LV
• VBATP 4.5 V to 6.0 V 1.0 — 2.4 mA (15)
ISUSSB SB Sustain current / Mode 0 Wetting current 1.75 2.2 2.85 mA
IWET
Wetting current level (SG & SB)
• Mode 1 = 6mA
• Mode 2 = 8mA
• Mode 3 = 10mA
• Mode 4 = 12mA
• Mode 5 = 14mA
• Mode 6 = 16mA
• Mode 7 = 20mA
—
6
8
10
12
14
16
20
—mA
IWETSG
SG wetting current tolerance
• Mode 1 to 7 -10 — 10 %
IWETSGLV
SG wetting current tolerance LV (VBATP 4.5 to 6.0V)(15)
• Mode 1 = 6mA
• Mode 2 = 8mA
• Mode 3 = 10mA
• Mode 4 = 12mA
• Mode 5 = 14mA
• Mode 6 = 16mA
• Mode 7 = 20mA
2.0
2.0
2.0
2.0
2.0
2.0
2.0
—
—
—
—
—
—
—
6.6
8.8
11.0
13.2
15.4
17.6
22.0
mA
IWETSB
SB wetting current tolerance
• Mode 1 to 7 -20 — 20 %
IMATCH(SUS) Sustain Current Matching Between Channels — — 10 % (16), (17)
IMATCH(WET) Wetting Current Matching Between Channels — — 6.0 % (18), (19)
VICTHR Switch Detection Threshold 3.7 4.0 4.3 V (20)
VICTHRLV
Switch Detection Threshold Low Battery
• VBATP 4.5 V to 6.0 V
0.55 *
VBATP
—4.3 V
VICTHRLPM Switch Detection Threshold Low-power Mode (SG only) 100 — 300 mV (21)
VICTHRH Switch Detection Threshold Hysteresis (4.0 V threshold) 80 — 300 mV
VICTH2P5
Input Threshold 2.5 V,
• Used for Comp Only and for AMUX Hardwired Select (SG1/2/3) 2.0 2.5 3.0 V
IACTIVEPOLLSG
Low-power Mode Polling Current SG
• VBATP 4.5 V to 28 V 0.7 1.0 1.44 mA
IACTIVEPOLLSB Low-power Mode Polling Current SB 1.75 2.2 2.85 mA
Table 6. Static electrical characteristics (continued)
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Units Notes
11 NXP Semiconductors
33978
Digital interface
IHZ Tri-state Leakage Current (MISO)
• VDDQ = 0.0 to VDDQ -2.0 — 2.0 μA
VINLOGIC
Input Logic Voltage Thresholds
• SI, SCLK, CS_B, INT_B
VDDQ *
0.25 —V
DDQ * 0.7 V
VINLOGICHYS
Input Logic Hysteresis
• SI, SCLK, CS_B, INT_B 300 — — mV
VINLOGICWAKE Input Logic Voltage Threshold WAKE_B 0.8 1.25 1.7 V
VINWAKEBHYS Input Logic Voltage Hysteresis WAKE_B 200 — 800 mV
ISCLK, IMOSI
SCLK / MOSI Input Current
• SCLK / MOSI = 0 V -3.0 — 3.0 µA
ISCLK, IMOSI
SCLK / MOSI Pull-down Current
• SCLK / MOSI = VDDQ 30 — 100 µA
ICS_BH
CS_B Input Current
• CS_B = VDDQ -10 — 10 µA
RCS_BL
CS_B Pull-up Resistor to VDDQ
• CS_B = 0.0 V 40 125 270 kΩ
VOHMISO
MISO High-side Output Voltage
•I
OHMISO = -1.0 mA VDDQ – 0.8 — VDDQ V
VOLMISO
MISO Low-side Output Voltage
•I
OLMISO = 1.0 mA ——0.4V
CIN Input Capacitance on SCLK, MOSI, Tri-state MISO (GBD) — — 20 pF
Analog MUX output
VOFFSET
Input Offset Voltage When Selected as Analog
• EK suffix (SOICW)
• ES suffix (QFN at TA = -40 °C to 25 °C)
-10
-15
—
—
10
15
mV (22)
VOLAMUX
Analog Operational Amplifier Output Voltage
•Sink 1.0 mA ——50mV
VOHAMUX
Analog Operational Amplifier Output Voltage
• Source 1.0 mA VDDQ – 0.1 — — V
AMUX selectable outputs
Temp-Coeff Chip Temperature Sensor Coefficient — 8.0 — mV/°C
VBATSNSACC
Battery Sense (SG5 config) Accuracy
• Battery voltage (SG5 input) divided by 6
• Accuracy over full temperature range
-5.0 — 5.0 %
VBATSNSDIV
Divider By 6 coefficient accuracy
• Offset over operating voltage range (VBATP=6.0 V to 28 V) -3.0 — 3.0 % (23)
Table 6. Static electrical characteristics (continued)
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Units Notes
NXP Semiconductors 12
33978
INT_B
VOLINT
INT_B Output Low Voltage
•I
OUT = 1.0 mA —0.20.5 V
VOHINT
INT_B Output High Voltage
• INT_B = Open-circuit VDDQ – 0.5 — VDDQ V
RPU Pull-up Resistor to VDDQ 40 125 270 kΩ
ILEAKINT_B Leakage Current INT_B
• INT_B pulled up to VDDQ ——1.0µA
Temperature limit
tFLAG
Temperature Warning
• First flag to trip 105 120 135 °C
tLIM Temperature Monitor 155 — 185 °C (24)
tLIM(HYS) Temperature Monitor Hysteresis 5.0 — 15 °C (24)
WAKE_B
RWAKE_B(RPU) WAKE_B Internal pull-up Resistor to VDDQ 40 125 270 kΩ
VWAKE_B(VOH)
WAKE_B Voltage High
• WAKE_B = Open-circuit VDDQ -1.0 — VDDQ V
VWAKE_B(VOL)
WAKE_B Voltage Low
• WAKE_B = 1.0 mA (RPU to VBATP = 16 V) ——0.4V
IWAKE_BLEAK
WAKE_B Leakage
• WAKE_B pulled up to VBATP = 16 V through 10 kΩ——1.0µA
Notes
14. Guaranteed by design
15. During low voltage range operation SG wetting current may be limited when there is not enough headroom between VBATP and SG pin voltage.
16. (ISUS(MAX)– ISUS(MIN)) X 100/ISUS(MIN)
17. Sustain current source (SGs only)
18. (IWET(MAX) – IWET(MIN)) X 100/IWET(MIN)
19. Wetting current source (SGs only)
20. The input comparator threshold decreases when VBATP ≤ 6.0 V.
21. SP (as SB) only use the 4.0 V VICTHR for LPM wake-up detection.
22. For applications requiring a tight AMUX offset through the whole operating range, it is recommended to use the MC33978AEK or MC34978AEK
(SOICW package) variant.
23. Calibration of divider ratio can be done at VBAT = 12 V, 25 °C to achieve a higher accuracy. See Figure 4 for AMUX offset linearity waveform
through the operating voltage range.
24. Guaranteed by characterization in the Development Phase, parameter not tested.
Table 6. Static electrical characteristics (continued)
TA = - 40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28.0 V, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Units Notes
13 NXP Semiconductors
33978
4.4.2 Dynamic electrical characteristics
Table 7. Dynamic electrical characteristics
TA = -40 °C to +125 °C. VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28 V, unless otherwise specified. All SPI timing is performed with a
100 pF load on MISO, unless otherwise noted.
Symbol Parameter Min.Typ. Max. Units Notes
General
tACTIVE
POR to Active time
• Undervoltage to Normal mode 250 340 450 µs
Switch input
tPULSE(ON)
Pulse Wetting Current Timer
• Normal mode 17 20 23 ms
tINT-DLY
Interrupt Delay Time
• Normal mode — — 18.5 µs
tPOLLING_TIMER
Polling Timer Accuracy
• Low-power mode ——15%
tINT-TIMER
Interrupt Timer Accuracy
• Low-power mode ——15%
tACTIVEPOLLSGTI
ME
Tactivepoll Timer SG 49.5 58 66.5 µs
tACTIVEPOLLSBTI
ME
Tactivepoll Timer SB
• SBPOLLTIME=0
• SBPOLLTIME=1
1.0
49.5
1.2
58
1.4
66.5
ms
µs
tGLITCHTIMER
Input Glitch Filter Timer
• Normal mode 5.0 — 18 µs
tDEBOUNCE
LPM Debounce Additional Time
• Low-power mode 1.0 1.2 1.4 ms
AMUX output
AMUXVALID
AMUX Access Time (Selected Output to Selected Output)
• CMUX = 1.0 nF, Rising edge of CS_B to selected —(26) — μs
AMUXVALIDTS
AMUX Access Time (Tristate to ON)
• CMUX = 1.0 nF, Rising edge of CS_B to selected ——20μs
Oscillator
OSCTOLLPM Oscillator Tolerance at 192 kHz in Low-power Mode -15 — 15 %
OSCTOLNOR Oscillator Tolerance Normal Mode at 4.0 MHz -15 — 15 %
Interrupt
INTPULSE INT Pulse Duration
• Interrupt occurs or INT_B request 90 100 110 µs
SPI interface
fOP Transfer Frequency — — 8.0 MHz
tSCK
SCLK Period
•Figure 7 - 1 160 — — ns
tLEAD
Enable Lead Time
•Figure 7 - 2 140 — — ns
tLAG
Enable Lag Time
•Figure 7 - 3 50 — — ns
tSCKHS
SCLK High Time
•Figure 7 - 4 56 — — ns
NXP Semiconductors 14
33978
SPI interface (continued)
tSCKLS
SCLK Low Time
•Figure 7 - 5 56 — — ns
tSUS
MOSI Input Setup Time
•Figure 7 - 6 16 — — ns
tHS
MOSI Input Hold Time
•Figure 7 - 7 20 — — ns
tA
MISO Access Time
•Figure 7 - 8 — — 116 ns
tDIS
MISO Disable Time (25)
•Figure 7 - 9 — — 100 ns
tVS
MISO Output Valid Time
•Figure 7 - 10 — — 116 ns
tHO
MISO Output Hold Time (No cap on MISO)
•Figure 7 - 11 20 — — ns
tRO
Rise Time
•Figure 7 - 12 — — 30 ns (25)
tFO
Fall Time
•Figure 7 - 13 — — 30 ns (25)
tCSN
CS_B Negated Time
•Figure 7 - 14 500 — — ns
WAKE-UP
tCSB_WAKEUP LPM mode wake-up time triggered by edge of CS_B — 755 1000 µs (27)
Notes
25. Guaranteed by characterization.
26. AMUX settling time to be within the 10 mV offset specification. AMUXVALID is dependant of the voltage step applied on the input SGx/SPx pin or
the difference between the first and second channel selected as the multiplexed analog output. See Figure 9 for a typical AMUX access time VS
voltage step waveform.
27. The parameter is guaranteed at VBATP = 4.5 V to 28 V.
Table 7. Dynamic electrical characteristics (continued)
TA = -40 °C to +125 °C. VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28 V, unless otherwise specified. All SPI timing is performed with a
100 pF load on MISO, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Units Notes
15 NXP Semiconductors
33978
Figure 4. Divide by 6 coefficient accuracy
Figure 5. Glitch filter and interrupt delay timers
Figure 6. Interrupt pulse timer
5.96
5.97
5.98
5.99
6
6.01
6.02
6.03
6.04
6 7 8 9 10111213141516171819202122232425262728
VBATP (Volts)
Divide By 6 Coefficient Accuracy
25°C
Divider factor
LPM CLK
SG_Pin
Input Glitch
filter timer
INT_B
500ns
tglitchTIMER
tINT- DLY
LPM CLK
SG_Pin
INT_B tINT- DLY INTPulse
NXP Semiconductors 16
33978
Figure 7. SPI timing diagram
Figure 8. MISO loading for disable time measurement
Figure 9. AMUX access time waveform
SCLK
6
MSB IN
CARE
LSB IN
DON'T
MISO
MOSI
11
MSB OUT DATA LSB OUT
2
3
4
5
810
7
DATA
9
14
12 13
1
CSb
0
50
100
150
200
250
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Step Size (mV)
AMUX Access Tim
e
Settling time (us)
AMUX settling time vs voltage step
17 NXP Semiconductors
33978
5 General description
The 33978 is designed to detect the closing and opening of up to 22 switch contacts. The switch status, either open or closed, is
transferred to the microprocessor unit (MCU) through a serial peripheral interface (SPI). Individually selectable input currents are available
in Normal and Low-power (LPM) modes, as needed for the application.
It also features a 24-to-1 analog multiplexer for reading inputs as analog. The analog input signal is buffered and provided on the AMUX
output pin for the MCU to read. A battery and temperature monitor are included in the IC and available via the AMUX pin.
The 33978 device has two modes of operation, Normal and Low-power mode (LPM). Normal mode allows programming of the device and
supplies switch contacts with pull-up or pull-down current as it monitors the change of state of switches. The LPM provides low quiescent
current, which makes the 33978 ideal for automotive and industrial products requiring low sleep-state currents.
5.1 Features
• Fully functional operation from 4.5 V to 36 V
• Full parametric operation from 6.0 V to 28 V
• Low-power mode current IBATP = 30 μA and IDDQ = 10 μA
• 22 Switch detection channels
• 14 Switch-to-Ground (SG) inputs
• Eight Programmable switch (SP) inputs
• Switch-to-Ground (SG) or Switch-to-Battery (SB)
• Operating switch input voltage range from -1.0 V to 36 V
• Selectable wetting current (2, 6, 8, 10, 12, 14, 16, or 20 mA)
• Programmable wetting operation (Pulse or Continuous)
• Selectable wake-up on change of state
• 24 to 1 Analog Multiplexer
• Buffered AMUX output from SG/SP channels
• Integrated divider by 6 on SG5 for battery voltage sensing
• Integrated die temperature sensing through AMUX output
• Two or three pin hardwire AMUX selection.
• Active interrupt (INT_B) on change-of-switch state
• Direct MCU Interface through 3.3 V / 5.0 V SPI protocol
NXP Semiconductors 18
33978
5.2 Functional block diagram
Figure 10. Functional block diagram
Logic and Control
SG0 – SG13 SP0 – SP7
Bias & References
WAKE_B I/O INT_B I/O
33978 Functional Internal Block Diagram
SPI Serial Communication & Registers
Switch Status Detection
Fault Detection and Protection
4.0 V SW detection reference.
OV Detection
Over Temperature
Protection
1.25 V internal Bandgap
VBATP UV detect
Input Power
VBATP
Battery Supply
VDDQ
Logic Supply
192 kHz
LPM Oscillator
4.0 MHz
Oscillator
SPI Error detect
HASH error detect
Switch to Ground (SG)
Only
Switch to Ground (SG)
Switch to Battery (SB)
Selectable Wetting Current Level
24 to 1 SPI AMUX select
Analog Multiplexer (AMUX)
Battery Voltage sensing (divided by 6 )
Die Temperature Sensing
Modes of Operation
Normal Mode Low Power Mode
Pulse/Continuous Wetting Current
8 x Programmable Switch
14 x Switch to Ground
Programmable Polling/
Interrupt Time
SPI communication/
Switch status read
Hardwire selectable
SPx/SGx Inputs to AMUX
19 NXP Semiconductors
33978
6 General IC functional description
The 33978 device interacts with many connections outside the module and near the end user. The IC detects changes in switch state and
reports the information to the MCU via the SPI protocol. The input pins generally connected to switches located outside the module and
in proximity to battery in car harnesses. Consequently, the IC must have some external protection including an ESD capacitor and series
resistors, to ensure the energy from the various pulses are limited at the IC.
The IC requires a blocking diode be used on the VBATP pin to protect from a reverse battery condition. The inputs are capable of surviving
reverse battery without a blocking diode and also contain an internal blocking diode from the input to the power supply (VBATP), to ensure
there is no backfeeding of voltage/current into the IC, when the voltage on the input is higher than the VBATP pin.
6.1 Battery voltage ranges
The 33978 device operates from 4.5 V ≤ VBATP ≤ 36 V and is capable to withstand up to 40 V. The IC operates functionally from
4.5 V < VBATP < 6.0 V, but with degraded parametrics values. Voltages in excess of 40 V must be clamped externally in order to protect
the IC from destruction. The VBATP pin must be isolated from the main battery node by a diode.
6.1.1 Load dump (overvoltage)
During load dump the 33978 operates properly up to the VBATP overvoltage. Voltages greater than load dump (~32 V) causes the current
sources to be limited to ~2.0 mA, but the register values are maintained. Upon leaving this overvoltage condition, the original setup is
returned and normal operation begins again.
6.1.2 Jump start (double battery)
During a jump start (double battery) condition, the device functions normally and meets all the specified parametric values. No internal
faults are set and no abnormal operation noted as a result of operating in this range.
6.1.3 Normal battery range
The normal voltage range is fully functional with all parametrics in the given specification.
6.1.4 Low-voltage range (degraded parametrics)
In the VBATP range between 4.5 V to 6.0 V the 33978 functions normally, but has some degraded parametric values. The SPI functions
normally with no false reporting. The degraded parameters are noted in Table 6 and Table 7. During this condition, the input comparator
threshold is reduced from 4.0 V and remain ratiometrically adjusted, according to the battery level.
6.1.5 Undervoltage lockout
During undervoltage lockout, the MISO output is tri-stated to avoid any data from being transmitted from the 33978. Any CS_B pulses are
ignored in this voltage range. If the battery enters this range at any point (even during a SPI word), the 33978 ignores the word and enters
lockout mode. A SPI bit register is available to notify the MCU that the 33978 has seen an undervoltage lockout condition once the battery
is high enough to leave this range.
6.1.6 Power on reset (POR) activated
The Power on Reset is activated when the VBATP is within the 2.7 V to 3.8 V range. During the POR all SPI registers are reset to default
values and SPI operation is disabled. The 33978 is initialized after the POR is de-asserted. A SPI bit in the device configuration register
is used to note a POR occurrence and all SPI registers are reset to the default values.
6.1.7 No operation
The device does not function and no switch detection is possible.
NXP Semiconductors 20
33978
Figure 11. Battery voltage range
6.2 Power sequencing conditions
The chip uses two supplies as inputs into the device for various usage. The pins are VBATP and VDDQ. The VBATP pin is the power
supply for the chip where the internal supplies are generated and power supply for the SG circuits. The VDDQ pin is used for the I/O buffer
supply to talk to the MCU or other logic level devices, as well as AMUX. The INT_B pin is held low upon POR until the IC is ready to
operate and communicate. Power can be applied in various ways to the 33978 and the following states are possible:
6.2.1 VBATP before VDDQ
The normal condition for operation is the application of VBATP and then VDDQ. The chip begin to operate logically in the default state but
without the ability to drive logic pins. When the VDDQ supply is available the chip is able to communicate correctly. The IC maintains its
logical state (register settings) with functional behavior consistent with logical state. No SPI communications can occur.
6.2.2 VDDQ before VBATP
The VDDQ supply in some cases may be available before the VBATP supply is ready. In this scenario, there is no back feeding current into
the VDDQ pin that could potentially turn on the device into an unknown state. VDDQ is isolated from VBATP circuits and the device is off
until VBATP is applied; when VBATP is available the device powers up the internal rails and logic within tACTIVE time. Communication is
undefined until the tACTIVE time and becomes available after this time frame.
6.2.3 VBATP okay, VDDQ lost
After power up, it is possible that the VDDQ may turn off or be lost. In this case, the chip remains in the current state but is not able to
communicate. After the VDDQ pin is available again, the chip is ready to communicate.
6.2.4 VDDQ okay, VBATP lost
After power up, the VBATP supply could be lost. The operation is consistent as when VDDQ is available before VBATP.
Functional
Normal Mode
Full Parametrics
Overvoltage
No Operation
41 V
37 V
29 V
7.0 V
0 V
5.5 V
Degraded Parametrics
Battery Voltage
(System Level)
Over Voltage
Load Dump
Normal
Battery
Low Battery
Reset
40 V
36 V
28 V
6.0 V
0 V
4.5 V
VBATP
(IC Level)
Undervoltage lockout
4.8 V 3.8 V
POR 2.7 V3.7 V
21 NXP Semiconductors
33978
7 Functional block description
7.1 State diagram
Figure 12. 33978 state diagram
7.1.1 State machine
After power up, the IC enters into the device state machine, as illustrated in Figure 12. The voltage on VBATP begins to power the internal
oscillators and regulator supplies. The POR is based on the internal 2.5 V digital core rail. When the internal logic regulator reaches
approximately 1.8 V (typically 3.3 V on the VBATP node), the IC enters into the UV range. Below the POR threshold, the IC is in RESET
mode where no activity occurs.
OV / OT
Iwet-> Isus
Wake
Event
Normal Mode
Low Power
Mode
Polling
UV
RESET
Run
VBATP > OV
or OT
VBAT too low:
POR
VBATP applied
Detect change in switch
status (opn/close)
SPI CMD
Polling time expires
Polling timer initiates
VBATP <
UV
IC OFF
VBAT applied >
por
Wait 50 μs
Read fuses
VBATP > UV
threshold
Not VBATP > OV
or OT
SPI RESET
command
NXP Semiconductors 22
33978
7.1.2 UV: undervoltage lockout
After the POR circuit has reset the logic, the IC is in undervoltage. In this state, the IC remembers all register conditions, but is in a lockout
mode, where no SPI communication is allowed. The AMUX is inactive and the current sources are off. The user does not receive a valid
response from the MISO, as it is disabled in this state. The chip oscillators (4.0 MHz for most normal mode activities, 192 kHz for LPM,
and limited normal mode functions) are turned on in the UV state. The chip moves to the Read fuses state when the VBATP voltage rises
above the UV threshold (~4.3 V rising). The internal fuses read in approximately 50 μs and the chip enters the Normal mode.
7.1.3 Normal mode
In normal mode, the chip operates as selected in the available registers. Any command may be loaded in normal mode, although not all
(Low-power mode) registers are used in the Normal mode. All the LPM registers must be programmed in Normal mode as the SPI is not
active in LPM. The Normal mode of the chip is used to operate the AMUX, communicate via the SPI, Interrupt the IC, wetting and sustain
currents, as well as the thresholds available to use. The WAKE_B pin is asserted (low) in Normal mode and can be used to enable a power
supply (ENABLE_B). Various fault detections are available in this mode including overvoltage, overtemperature, thermal warning, SPI
errors, and Hash faults.
7.1.4 Low-power mode
When the user needs to lower the IC current consumption, a low-power mode is used. The only method to enter LPM is through a SPI
word. After the chip is in low-power mode, the majority of circuitry is turned off including most power rails, the 4.0 MHz oscillator, and all
the fault detection circuits. This mode is the lowest current consumption mode on the chip. If a fault occurs while the chip is in this mode,
the chip does not see or register the fault (does not report via the SPI when awakened). Some items may wake the IC in this mode,
including the interrupt timer, falling edge of INT_B, CS_B, or WAKE_B (configurable), or a comparator only mode switch detection.
7.1.5 Polling mode
The 33978 uses a polling mode which periodically (selectable in LPM config register) interrogates the input pins to determine in what state
the pins are, and decide if there was a change of state from when the chip was in Normal mode. There are various configurations for this
mode, which allow the user greater flexibility in operation. This mode uses the current sources to pull-up (SG) or down (SB) to determine
if a switch is open or closed. More information is available in section 7.2, “Low-power mode operation".
In the case of a low VBATP, the polling pauses and waits until the VBATP rises out of UV or a POR occurs. The pause of the polling ensures
all of the internal rails, currents, and thresholds are up at the required levels to accurately detect open or closed switches. The chip does
not wake-up in this condition and simply waits for the VBATP voltage to rise or cause a POR.
After the polling ends, the chip either returns to the low-power mode, or enters Normal mode when a wake event was detected. Other
events may wake the chip as well, such as the falling edge of CS_B, INT_B, or WAKE_B (configurable). A comparator only mode switch
detection is always on in LPM or Polling mode, so a change of state for those inputs would effectively wake the IC in Polling mode as well.
If the Wake-up enable bits are disable on all channels (SG and SP) the device will not wake up with a change of state on any of the input
pins; in this case, the device will disable the polling timer to allow the lowest current consumption during low-power mode.
7.2 Low-power mode operation
Low-power mode (LPM) is used to reduce system quiescent currents. LPM may be entered only by sending the Enter Low-power mode
command. All register settings programmed in Normal mode are maintained while in LPM.
The 33978 exits LPM and enter Normal mode when any of the following events occur:
• Input switch change of state (when enabled)
• Interrupt timer expire
• Falling edge of WAKE_B (as set by the device configuration register)
• Falling edge of INT_B (with VDDQ = 5.0 V)
• Falling edge of CS_B (with VDDQ = 5.0 V)
• Power-ON Reset (POR)
The VDDQ supply may be removed from the device during LPM, however removing VDDQ from the device disables a wake-up from falling
edge of INT_B and CS_B. The IC checks the status of VDDQ after a falling edge of WAKE_B (as selected in the device configuration
register), INT_B and CS_B. The IC returns to LPM and does not report a Wake event, if VDDQ is low. If the VDDQ is high, the IC wakes up
and reports the Wake event. In cases where CS_B is used to wake the device, the first MISO data message is not valid.