THC63LVD823B_Rev.3.1_E THC63LVD823B 160MHz 51Bits LVDS Transmitter General Description Features The THC63LVD823B transmitter is designed to support Single Link transmission between Host and Flat Panel Display and Dual Link transmission between Host and Flat Panel Display up to 1080p/QXGA resolutions. The THC63LVD823B converts 51bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. In Dual Link, the transmit clock frequency of 160MHz, 51bits of RGB data are transmitted at an effective rate of 1.12Gbps per LVDS channel. * Wide dot clock range suited for TV Signal (480p- * * 1080p), PC Signal (VGA-QXGA) TTL/CMOS Input: 10-160MHz LVDS Output: 20-160MHz PLL requires No external components Flexible Input/Output mode 1. Single/Dual TTL IN, Single/Dual LVDS OUT 2. Double edge input for Single TTL IN/Dual LVDS OUT * * * * * * * * * Clock edge selectable 2 LVDS data mapping for simplifying PCB layout. Pseudo Random pattern generation circuit Supports Reduced swing LVDS for Low EMI Power down mode Low power single 3.3V CMOS design 1.2 up to 3.3V tolerant data inputs to connect directly to low power,low voltage application and graphic processor. Backward compatible with THC63LVD823/ THC63LVD823A 100pin TQFP HSYNC VSYNC DE 24 3 R/F RS 28 MAP PARALLEL TO SERIAL R2[7:0] G2[7:0] B2[7:0] 28 24 Data Formatter DATA Port2 R1[7:0] G1[7:0] B1[7:0] 1) DEMUX 2) MUX DATA Port1 TA1 +/- PARALLEL TO SERIAL Block Diagram TA2 +/- TB1 +/- LVDS OUTPUT Port1 TC1 +/TD1 +/- TB2 +/- LVDS OUTPUT Port2 TC2 +/TD2 +/- MODE[1:0] O/E DDRN /PDWN PRBS TCLK1 +/- TRANSMITTER CLOCK IN (10 to 160MHz) PLL TCLK2 +/- (N/C) (20 to 160MHz) Copyright(c)2011 THine Electronics, Inc. 1/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E B14 B13 B12 GND VCC B11 B10 G17 G16 G15 G14 G13 G12 G11 G10 R17 R16 R15 R14 GND VCC R13 R12 R11 R10 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Pin Out (top view) G22 91 35 TB2- G23 92 34 TB2+ G24 93 33 LVCC G25 94 32 TC2- G26 95 31 TC2+ G27 96 30 TCLK2- B20 97 29 TCLK2+ B21 98 28 TD2- B22 99 27 TD2+ B23 100 26 LGND Copyright(c)2011 THine Electronics, Inc. 2/21 25 TA2+ 24 36 PGND 90 PVCC G21 23 TA2- 22 37 PGND G20 N/C LGND 21 38 89 20 88 Reserved GND PRBS TD1+ 19 TD1- 39 18 40 87 /PDWN 86 VCC GND R27 17 TCLK1+ O/E 41 MODE0 85 16 R26 15 TCLK1- MODE1 42 14 TC1+ 13 43 84 MAP 83 R25 DDRN R24 12 TC1- 11 44 RS 82 R/F R23 10 LVCC 9 45 CLKIN R22 DE TB1+ 8 46 81 VSYNC 80 HSYNC R21 7 TB1- 6 TA1+ 47 B27 48 79 B26 78 R20 5 B17 4 TA1- GND 49 3 77 2 B16 VCC LGND B25 50 1 76 B24 B15 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Pin Description Pin Name Pin # TA1+, TA1- 48, 49 TB1+, TB1- 46, 47 TC1+, TC1- 43, 44 TD1+, TD1- 39, 40 TCLK1+, TCLK1- 41, 42 TA2+, TA2- 36, 37 TB2+, TB2- 34, 35 TC2+, TC2- 31, 32 TD2+, TD2- 27, 28 TCLK2+, TCLK2- 29, 30 R17 ~ R10 60 -57, 54 - 51 G17 ~ G10 68 - 61 B17 ~ B10 78 - 73, 70, 69 R27 ~ R20 86 - 79 G27 ~ G20 96 - 89 B27 ~ B20 6, 5, 2, 1, Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT Description The 1st Link. The 1st pixel output data when Dual-Link. LVDS Clock Out for 1st and 2nd Link. The 2nd Link. These pins are disabled when Single Link. Additional LVDS Clock Out. Identical to TCLK1+,-. No connect if not used. IN The 1st Pixel Data Inputs. IN The 2nd Pixel Data Inputs. 100 - 97 DE 9 IN Data Enable Input. VSYNC 8 IN Vsync Input. HSYNC 7 IN Hsync Input. CLKIN 10 IN Clock Input. R/F 11 IN Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge LVDS swing mode, VREF select. See Fig4 - 5. RS 12 IN RS LVDS Swing Small Swing Input Support VIHM 350mV N/A VIMM 350mV RS=VREFa VILM 200mV N/A a. VREF is Input Reference Voltage. LVDS mapping table select. See Fig7 to 8 and Table4 to 7. MAP MAP 14 IN VIHM VILM VIMM Mapping Mode Mapping MODE1 Mapping MODE2 Reserved Pixel Data Mode. MODE1, MODE0 15, 16 Copyright(c)2011 THine Electronics, Inc. IN MODE 1 L H L H 3/21 MODE0 Mode L L H H Dual Link (Dual-in/Dual-out) Dual Link (Single-in/Dual-out) Single Link (Dual-in/Single-out) Single Link (Single-in/Single-out) THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Pin Description (Continued) Pin Name Pin # Type Description Output enable. O/E 17 IN H: Output enable, L: Output disable (all outputs are Hi-Z). /PDWN 19 IN H: Normal operation, L: Power down (all outputs are Hi-Z) PRBS (Pseudo-Random Binary Sequence) generator is active in order to evaluate eye patterns when PRBS a 20 IN MODE<1:0> = LL (Dual-in/Dual-out mode). H: PRBS generator is enable. L: Normal Operation Reserved 21 IN Must be tied to GND. DDR function is active when DDRN 13 IN MODE<1:0> = HL (Single-in/Dual-out mode). Open or H: DDR (Double Edge input) function disable. L: DDR (Double Edge input) function enable. N/C 22 VCC 3, 55, 71, 87 GND 4, 18, 56, 72, 88 Must be Open. Power Power Supply Pins for TTL inputs and digital circuitry. Ground Ground Pins for TTL inputs and digital circuitry. LVCC 33, 45 Power Power Supply Pins for LVDS Outputs. LGND 26, 38, 50 Ground Ground Pins for LVDS Outputs. PVCC 24 Power Power Supply Pin for PLL circuitry. PGND 23, 25 Ground Ground Pins for PLL circuitry. a: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of 223-1. The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and serialized into TXOUT output. This function is normally to be used for analyzing the signal integrity of the transmission channel including PCB traces, connectors, and cables. Copyright(c)2011 THine Electronics, Inc. 4/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Absolute Maximum Ratings Supply Voltage (VCC) -0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V) LVDS Transmitter Output Voltage -0.3V ~ (VCC + 0.3V) Output Current -30mA ~ 30mA Junction Temperature +125 C Storage Temperature Range -55 C ~ +125 C Reflow Peak Temperature / Time +260 C / 10sec. Maximum Power Dissipation @+25 C 2.4W Recommended Operating Conditions Parameter Min. Typ Max Units All Supply Voltage 3.0 3.3 3.6 V Operating Ambient Temperature -20 70 C MODE<1:0>=LL Input 20 160 MHz Dual-in/Dual-out LVDS Output 20 160 MHz MODE<1:0>=LH Input 10 80 MHz Dual-in/Single-out LVDS Output 20 160 MHz Single Edge Input Input 40 160 MHz MODE<1:0>=HL (DDRN =Open/H) LVDS Output 20 80 MHz Single-in/Dual-out Double Edge Input Input 20 80 MHz (DDRN=L) LVDS Output 20 80 MHz MODE<1:0>=HH Input 20 160 MHz Single-in/Single-out LVDS Output 20 160 MHz Clock Frequency Copyright(c)2011 THine Electronics, Inc. 5/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Electrical Characteristics CMOS/TTL DC Specifications VCC = VCC=PVCC=LVCC Symbol Parameter VIHa High Level Data Input Voltage VILa Low Level Data Input Voltage Conditions Min. RS=VIHMor VILM Typ. Max. Units VCC 2.0 V VREFb+0.1 RS=VIMM RS=VIHMor VILM V GND RS=VIMM 0.8 V VREF-0.1 V VIHCc High Level Control Input Voltage 2.0 VCC V VILCc Low Level Control Input Voltage GND 0.8 V VIHMd High Level Control Input Voltage 0.8VCC VCC V VIMMd Middle Level Control Input Voltage 0.6 1.4 V VILMd Low Level Control Input Voltage GND 0.08VCC V IINC Input Current (except DDRN) GND V IN V CC 10 A IINCD Input Current (Only DDRN) GND V IN V CC 20 A a. CLKIN,R10~R17,G10~G17,B10~B17,R20~R27,G20~G27,B20~B27,DE,HSYNC,VSYNC b. VREF is input voltage of RS pin. c. R/F,DDRN,MODE0,MODE1,O/E,PDWN,PRBS d. RS,MAP LVDS Transmitter DC Specifications VCC = VCC=PVCC=LVCC Symbol Parameter Conditions Normal swing VOD Differential Output Voltage RL=100 RS= VCC Reduced swing RS= GND VOD VOC Min. Typ. Max. 250 350 450 mV 100 200 300 mV 35 mV Change in VOD between complementary output states Common Mode Voltage VOC Change in VOC between complementary output states IOS Output Short Circuit Current IOZ Output TRI-State current Copyright(c)2011 THine Electronics, Inc. RL=100 1.125 VOUT=GND, RL=100 /PDWN=GND, VOUT=GND to VCC 6/21 1.25 1.375 Units V 35 mV -24 mA 10 A THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Electrical Characteristics (Continued) Supply Current VCC = VCC=PVCC=LVCC Symbol Parameter Condition mA MODE<1:0>=HH CLKIN=85MHz 100 mA Single-in/Single-out CLKIN=135MHz 122 mA CLKIN=160MHz T.B.D mA CLKIN=65MHz 114 mA CLKIN=85MHz 116 mA CLKIN=135MHz 155 mA CLKIN=150MHz 168 mA CLKIN=160MHz T.B.D mA CLKIN=32.5MHz 114 mA CLKIN=42.5MHz 118 mA CLKIN=67.5MHz 155 mA CLKIN=75MHz 167 mA CLKIN=80MHz T.B.D mA CLKIN=32.5MHz 84 mA MODE<1:0>=LH CLKIN=42.5MHz 98 mA Dual-in/Single-out CLKIN=67.5MHz 120 mA CLKIN=80MHz T.B.D mA CLKIN=65MHz 144 mA MODE<1:0>=LL CLKIN=85MHz 171 mA Dual-in/Dual-out CLKIN=135MHz 217 mA CLKIN=160MHz T.B.D mA 50 A DDRN=H or Open DDR Input Off Current (Worst Case Pattern) Fig1. ITCCS Transmitter Power Down Supply Units 86 Single-in/Dual-out ITCCW Max. CLKIN=65MHz MODE<1:0>=HL Transmitter Supply Typ. RL=100 MODE<1:0>=HL CL=5pF Single-in/Dual-out RS=VCC DDRN=L DDR Input On /PDWN = L, All Inputs = Fixed L or H Current TCLK1+ Txy+ x= A, B, C, D y=1,2 Fig1. Test Pattern (LVDS Output Full Toggle Pattern) Copyright(c)2011 THine Electronics, Inc. 7/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Switching Characteristics VCC = VCC=PVCC=LVCC Symbol Parameter Min. Typ. Max. Units tTCIP CLK IN Period(Fig4,5) tTCH CLK IN High Time(Fig4,5) 0.35tTCIP tTCL CLK IN Low Time(Fig4,5) 0.35tTCIP tTS TTL Data Setup to CLK IN(Fig4,5) 2.5 ns tTH TTL Data Hold from CKL IN(Fig4,5) 0.0 ns 6.25 CLK IN to TCLK+/- Delay(Fig4,5) tTCD MODE<1:0>=LL Dual-in/Dual-out tTCOP tLVT tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 tTPLL CLK OUT Period(Fig6) 100 ns 0.5tTCIP 0.65tTCIP ns 0.5tTCIP 0.65tTCIP ns (4+3/7)tTCIP (4+3/7)tTCIP +2.6 +7.5 6.25 50 ns 0.6 1.5 ns 0.0 +0.15 ns LVDS Transition Time(Fig2) Output Data -0.15 Position0 (Fig6) Output Data Position1 (Fig6) Output Data Position2 (Fig6) tTCOP = Output Data Position3 (Fig6) 6.25ns~20ns Output Data Position4 (Fig6) Output Data Position5 (Fig6) Output Data Position6 (Fig6) ns t TCOP --------------- - 0.15 7 t TCOP --------------7 t TCOP --------------+ 0.15 7 ns t TCOP - 0.15 2 --------------7 t TCOP 2 --------------7 t TCOP + 0.15 2 --------------7 ns t TCOP 3 --------------- 0.15 7 t TCOP 3 --------------7 t TCOP + 0.15 3 --------------7 ns t TCOP 4 --------------- 0.15 7 t TCOP 4 --------------7 t TCOP + 0.15 4 --------------7 ns t TCOP - 0.15 5 --------------7 t TCOP 5 --------------7 t TCOP 5 --------------+ 0.15 7 ns t TCOP - 0.15 6 --------------7 t TCOP 6 --------------7 t TCOP 6 --------------+ 0.15 7 ns 10.0 ms Phase Lock Time(Fig3) DE input period (Fig3-1) tDEINT Single-in / Dual-out, DDR Off mode only(MODE<1:0>=HL, 4tTCIP tTCIP*(2n) a ns 2tTCIP tTCIP*(2m)a ns DDRN =Open or H) DE High time (Fig3-1) tDEH Single-in / Dual-out, DDR Off mode only(MODE<1:0>=HL, DDRN =Open or H) DE Low time(Fig3-1) tDEL Single-in / Dual-out, DDR Off mode only(MODE<1:0>=HL, 2tTCIP ns DDRN =Open or H) a. Refer to Fig3-1 for details. Copyright(c)2011 THine Electronics, Inc. 8/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E AC Timing Diagrams Vdiff=(TA+)-(TA-) TA+ Vdiff 5pF 80% 80% 20% 20% 100 TAtLVT tLVT LVDS Output Load Fig2. LVDS Output Load and Transition Time CLKIN 2.0V /PDWN tTPLL Vdiff=0V TCLKx+/x=1,2 Fig3. PLL Lock Time tDEINT tTCIP CLKIN DE tDEH tDEL Note: In single-in/dual-out, DDR off mode (MODE<1:0>=HL, DDRN =Open or H), the period between rising edges of DE (tDEINT), high time of DE (tDEH) should always satisfy following equations. tDEH = tTCIP * (2m) tDEINT = tTCIP * (2n) m, n =integer Fig3-1. Single IN / Dual OUT, DDR off mode DE input timing Copyright(c)2011 THine Electronics, Inc. 9/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E AC Timing Diagrams (Continued) RS pin VIHM tTCIP tTCH VIMM tTCL VILM VOD 350mV 200mV VREF VCC/2 Input Voltage of RS pin VCC/2 VCC VREF CLKIN VREF VREF GND Rxn, Gxn, Bxn HSYNC VSYNC VREF DE x=1,2 n=0-7 tTS tTH VCC Current Data VREF GND tTCD TCLKx+/x=1,2 VOD Txy+/x=1,2 y= A, B, C, D VOC Current Data Note: CLKIN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line. Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing RS pin VIHM tTCIP tTCH VIMM tTCL VILM VOD 350mV 200mV VREF VCC/2 Input Voltage of RS pin VCC/2 VCC VREF CLKIN VREF VREF GND tTS Rxn, Gxn, Bxn HSYNC VSYNC DE x=1,2 n=0-7 tTH tTS tTH VCC VREF 1st Pixel Data 2nd Pixel Data VREF GND tTCD TCLKx+/x=1,2 VOD Txy+/x=1,2 y= A, B, C, D VOC Current Data Note: CLKIN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line. Fig5. CLKIN Period, High/Low Time, Setup/Hold Timing for Double Edge Input Mode (DDR) MODE<1:0>=HL,DDRN=L Copyright(c)2011 THine Electronics, Inc. 10/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E AC Timing Diagrams (Continued) tTOP2 tTOP3 tTOP4 tTOP5 tTOP6 tTOP0 tTOP1 Tyx+/- Tyx6 Tyx5 Tyx4 Tyx3 TCLKx+ Tyx2 Tyx1 Tyx0 Tyx6 Tyx5 Vdiff = 0V Tyx4 Tyx3 Tyx2 Tyx1 Vdiff = 0V x = 1,2 y = A,B,C,D tTCOP Note: Vdiff = (Tyx+) - (Tyx-), (TCLKx+) - (TCLKx-) Fig6. LVDS Output Data Position Copyright(c)2011 THine Electronics, Inc. 11/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Input Data Mapping *Table1. Input Color Data naming rule X Y Z Description X=R Red Color Data X=G Green Color Data X=B Blue Color Data Y= None Single Pixel Y=E Dual Pixel Y=O Z=0-7 1st Pixel Data 2nd Pixel Data Bit number 0: LSB (Least Significant Bit) 7: MSB (Most Significant Bit) *Table2. TTL/CMOS Input Data Mapping (Single-in mode, MODE1=H) Data Signals Copyright(c)2011 THine Electronics, Inc. Transmitter Input Pin Names R0 R10 R1 R11 R2 R12 R3 R13 R4 R14 R5 R15 R6 R16 R7 R17 G0 G10 G1 G11 G2 G12 G3 G13 G4 G14 G5 G15 G6 G16 G7 G17 B0 B10 B1 B11 B2 B12 B3 B13 B4 B14 B5 B15 B6 B16 B7 B17 12/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Input Data Mapping (Continued) *Table3. TTL/CMOS Input Data Mapping (Dual-in mode, MODE1=L) Data Signals RE0 Transmitter Input Pin Names Data Signals Transmitter Input Pin Names R10 RO0 RE1 R11 RO1 R21 RE2 R12 RO2 R22 RE3 R13 RO3 R23 RE4 R14 RO4 R24 RE5 R15 RO5 R25 RE6 R16 RO6 R26 RE7 R17 RO7 R27 GE0 G10 GO0 G20 GE1 G11 GO1 G21 GE2 G12 GO2 G22 GE3 G13 GO3 G23 GE4 G14 GO4 G24 GE5 G15 GO5 G25 GE6 G16 GO6 G26 GE7 G17 GO7 G27 BE0 B10 BO0 B20 BE1 B11 BO1 B21 BE2 B12 BO2 B22 BE3 B13 BO3 B23 BE4 B14 BO4 B24 BE5 B15 BO5 B25 BE6 B16 BO6 B26 BE7 B17 BO7 B27 Copyright(c)2011 THine Electronics, Inc. 13/21 R20 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E LVDS Output Data Mapping Previous Cycle (2nd Pixel Data) Next Cycle (2nd Pixel Data) Current Cycle (1st Pixel Data) TCLK1+ Tx1+/x= A, B, C, D Tx11(n-1) Tx10(n-1) Tx16(n) Tx15(n) Tx14(n) Tx13(n) Tx12(n) Tx11(n) Tx10(n) Tx16(n+1) Fig7. TTL Data Inputs Mapped to LVDS outputs MODE0= H (Single-out Mode) Previous Cycle Current Cycle TCLK1+ Tx1+/x= A, B, C, D Tx11(n-1) Tx10(n-1) Tx16(n) Tx15(n) Tx14(n) Tx13(n) Tx12(n) Tx11(n) Tx10(n) Tx16(n+1) Tx2+/x= A, B, C, D Tx21(n-1) Tx20(n-1) Tx26(n) Tx25(n) Tx24(n) Tx23(n) Tx22(n) Tx21(n) Tx20(n) Tx26(n+1) Fig8. TTL Data Inputs Mapped to LVDS outputs MODE0= L (Dual-out Mode) Copyright(c)2011 THine Electronics, Inc. 14/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E LVDS Output Data Mapping (Continued) *Table4. LVDS Output Data Mapping (Single-in/Single-out, MODE<1:0>=HH) LVDS Mapping Mode (Input Pin Name) Mode1 Output Data MAP=H Mode2 MAP=L TA10 R12 R10 TA11 R13 R11 TA12 R14 R12 TA13 R15 R13 TA14 R16 R14 TA15 R17 R15 TA16 G12 G10 TB10 G13 G11 TB11 G14 G12 TB12 G15 G13 TB13 G16 G14 TB14 G17 G15 TB15 B12 B10 TB16 B13 B11 TC10 B14 B12 TC11 B15 B13 TC12 B16 B14 TC13 B17 B15 TC14 HSYNC HSYNC TC15 VSYNC VSYNC TC16 DE DE TD10 R10 R16 TD11 R11 R17 TD12 G10 G16 TD13 G11 G17 TD14 B10 B16 TD15 B11 B17 TD16 N/A N/A Copyright(c)2011 THine Electronics, Inc. 15/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E LVDS Output Data Mapping (Continued) *Table5. LVDS Output Data Mapping (Single-in/Dual-out, DDR On/Off, MODE<1:0>=HL, DDRN =Open/H/L) Mapping Mode (Input Pin Name) LVDS Output Data Mode1 (1st Link) MAP=H TA10 R12 LVDS Mapping Mode (Input Pin Name) Mode2 MAP=L Output Data Mode1 (2nd Link) MAP=H Mode2 MAP=L R10 TA20 R12 R10 TA11 R13 R11 TA21 R13 R11 TA12 R14 R12 TA22 R14 R12 TA13 R15 R13 TA23 R15 R13 TA14 R16 R14 TA24 R16 R14 TA15 R17 R15 TA25 R17 R15 TA16 G12 G10 TA26 G12 G10 TB10 G13 G11 TB20 G13 G11 TB11 G14 G12 TB21 G14 G12 TB12 G15 G13 TB22 G15 G13 TB13 G16 G14 TB23 G16 G14 TB14 G17 G15 TB24 G17 G15 TB15 B12 B10 TB25 B12 B10 TB16 B13 B11 TB26 B13 B11 TC10 B14 B12 TC20 B14 B12 TC11 B15 B13 TC21 B15 B13 TC12 B16 B14 TC22 B16 B14 TC13 B17 B15 TC23 B17 B15 TC14 HSYNC HSYNC TC24 HSYNC HSYNC TC15 VSYNC VSYNC TC25 VSYNC VSYNC TC16 DE DE TC26 DE DE TD10 R10 R16 TD20 R10 R16 TD11 R11 R17 TD21 R11 R17 TD12 G10 G16 TD22 G10 G16 TD13 G11 G17 TD23 G11 G17 TD14 B10 B16 TD24 B10 B16 TD15 B11 B17 TD25 B11 B17 TD16 N/A N/A TD26 N/A N/A VCC DE GND R1n,G1n,B1n n=0 - 7 Hsync Vsync VCC 1st Pixel Data 2nd Pixel Data 1st Pixel Data 2nd Pixel Data GND Fig9. The decision rule of 1st Pixel data in Single IN/Dual Out DDR Off (MODE<1:0>=HL, DDRN =Open or H) Copyright(c)2011 THine Electronics, Inc. 16/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E LVDS Output Data Mapping (Continued) *Table6. LVDS Output Data Mapping (Dual-in/Single-out, MODE<1:0>=LH) LVDS Mapping Mode (Input Pin Name) Output Data Mode1 (1st Pixel) MAP=H TA10(n) R12 LVDS Mapping Mode (Input Pin Name) Mode2 Output Data Mode1 Mode2 MAP=L (2nd Pixel) MAP=H MAP=L R10 TA10(n+1) R22 R20 TA11(n) R13 R11 TA11(n+1) R23 R21 TA12(n) R14 R12 TA12(n+1) R24 R22 TA13(n) R15 R13 TA13(n+1) R25 R23 TA14(n) R16 R14 TA14(n+1) R26 R24 TA15(n) R17 R15 TA15(n+1) R27 R25 TA16(n) G12 G10 TA16(n+1) G22 G20 TB10(n) G13 G11 TB10(n+1) G23 G21 TB11(n) G14 G12 TB11(n+1) G24 G22 TB12(n) G15 G13 TB12(n+1) G25 G23 TB13(n) G16 G14 TB13(n+1) G26 G24 TB14(n) G17 G15 TB14(n+1) G27 G25 TB15(n) B12 B10 TB15(n+1) B22 B20 TB16(n) B13 B11 TB16(n+1) B23 B21 TC10(n) B14 B12 TC10(n+1) B24 B22 TC11(n) B15 B13 TC11(n+1) B25 B23 TC12(n) B16 B14 TC12(n+1) B26 B24 TC13(n) B17 B15 TC13(n+1) B27 B25 TC14(n) HSYNC HSYNC TC14(n+1) HSYNC HSYNC TC15(n) VSYNC VSYNC TC15(n+1) VSYNC VSYNC TC16(n) DE DE TC16(n+1) DE DE TD10(n) R10 R16 TD10(n+1) R20 R26 TD11(n) R11 R17 TD11(n+1) R21 R27 TD12(n) G10 G16 TD12(n+1) G20 G26 TD13(n) G11 G17 TD13(n+1) G21 G27 TD14(n) B10 B16 TD14(n+1) B20 B26 TD15(n) B11 B17 TD15(n+1) B21 B27 TD16(n) N/A N/A TD16(n+1) N/A N/A Copyright(c)2011 THine Electronics, Inc. 17/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E LVDS Output Data Mapping (Continued) *Table7. LVDS Output Data Mapping (Dual-in/Dual-out, MODE<1:0>=LL) LVDS Mapping Mode (Input Pin Name) Output Data Mode1 (1st Link) MAP=H TA10 R12 LVDS Mapping Mode (Input Pin Name) Mode2 Output Data Mode1 Mode2 MAP=L (2nd Link) MAP=H MAP=L R10 TA20 R22 R20 TA11 R13 R11 TA21 R23 R21 TA12 R14 R12 TA22 R24 R22 TA13 R15 R13 TA23 R25 R23 TA14 R16 R14 TA24 R26 R24 TA15 R17 R15 TA25 R27 R25 TA16 G12 G10 TA26 G22 G20 TB10 G13 G11 TB20 G23 G21 TB11 G14 G12 TB21 G24 G22 TB12 G15 G13 TB22 G25 G23 TB13 G16 G14 TB23 G26 G24 TB14 G17 G15 TB24 G27 G25 TB15 B12 B10 TB25 B22 B20 TB16 B13 B11 TB26 B23 B21 TC10 B14 B12 TC20 B24 B22 TC11 B15 B13 TC21 B25 B23 TC12 B16 B14 TC22 B26 B24 TC13 B17 B15 TC23 B27 B25 TC14 HSYNC HSYNC TC24 HSYNC HSYNC TC15 VSYNC VSYNC TC25 VSYNC VSYNC TC16 DE DE TC26 DE DE TD10 R10 R16 TD20 R20 R26 TD11 R11 R17 TD21 R21 R27 TD12 G10 G16 TD22 G20 G26 TD13 G11 G17 TD23 G21 G27 TD14 B10 B16 TD24 B20 B26 TD15 B11 B17 TD25 B21 B27 TD16 N/A N/A TD26 N/A N/A Copyright(c)2011 THine Electronics, Inc. 18/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Note 1)Cable Connection and Disconnection Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 2)GND Connection Connect the each GND of the PCB which THC63LVD823B and LVDS-Rx on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 3)Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVD823B LVDS-Rx TCLKLVDS-Rx 4)Asynchronous use Asynchronous use such as following systems are not recommended. CLKOUT DATA IC CLKOUT DATA LVDS-Rx TCLK- DATA IC TCLK+ THC63LVD823B DATA TCLK+ THC63LVD823B CLKOUT DATA Copyright(c)2011 THine Electronics, Inc. DATA LVDS-Rx TCLK- CLKOUT IC CLKOUT TCLK+ THC63LVD823B TCLKTCLK+ THC63LVD823B IC TCLK- 19/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Package 16.00 BSC 1.20 MAX 14.00 BSC 1.00 +/-0.05 14.00 BSC 16.00 BSC 0.050.15 1.00 REF 0.090.20 0.50 BSC 0.20 +0.07/-0.03 SEATING PLANE 07.0 0.10 S S 0.08R MIN 0.08R0.20R GAGE PLANE 0.25mm 0.60 +/-0.15 0.20 BSC Unitmm Copyright(c)2011 THine Electronics, Inc. 20/21 THine Electronics, Inc. THC63LVD823B_Rev.3.1_E Notices and Requests 1.)The product specifications described in this material are subject to change without prior notice. 2.)The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3.)This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4.)Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5.)This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6.)Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7.)Please note that this product is not designed to be radiation-proof. 8.)Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. E-mail: sales@thine.co.jp Copyright(c)2011 THine Electronics, Inc. 21/21 THine Electronics, Inc.