Data Sheet January 1998 T7289A DS1 Line Interface Features Fully integrated DS1 line interface Intended for use in systems that must comply with PUB 43802, CB119, TR-TSY-000170, and TRTSY-000499 (Category I equipment) Low power dissipation On-chip transmit equalization Monolithic clock recovery High jitter accommodation Excellent transmit template performance Single-rail/dual-rail interface Pin-selectable B8ZS encoder and decoder (during single-rail mode only) Loopback modes for fault isolation Multiple link-status and alarm features Minimal external circuitry required Description The Lucent Technologies Microelectronics Group T7289A DS1 Line Interface is an integrated circuit that provides a line interface between the DS1 cross connect (DSX) and terminal equipment circuits for cable distances of up to 655 ft. for 22-gauge, plastic, insulated cable (PIC). The T7289A device performs receive-pulse regeneration, timing recovery, and transmit-pulse shaping and equalization functions. The device is manufactured by using low-power CMOS technology and is available in a 28-pin, plastic DIP or in a 28-pin, plastic SOJ package. The T7289A device is functionally compatible with the T7289, LC1046A, and LC1046C devices for 1.544 Mbits/s operation but provides improved jitter transfer and crosstalk characteristics with a selectable single-rail/ dual-rail system interface. Data Sheet January 1998 T7289A DS1 Line Interface Description (continued) TRANSMIT LINE OUTPUT DRIVERS LP1 RECEIVE LINE RECEIVE ANALOG INPUT LOSS OF SIGNAL LINE LENGTH SELECT INSERT BLUE SIGNAL SELECTABLE PULSE EQUALIZATION B8ZS ENCODER AND RAIL CONVERSION LOOPBACKS LP2 TRANSMIT DATA TRANSMIT CLOCK LP3 B8ZS DECODER AND BPV DETECTION AND RAIL CONVERSION CLOCK EXTRACTION & RETIMING RECEIVED DATA RECEIVED CLOCK SINGLE-RAIL/DUAL-RAIL SELECT BIPOLAR VIOLATION ALARM 5-4348(C) Figure 1. T7289A Block Diagram Pin Information LOS 1 28 T1 LOC 2 27 R1 BZSC/TNDATA 3 26 SD BPV/RNDATA 4 25 GNDA RCLK 5 24 VDDA RDATA/RPDATA TCLK 6 23 DUAL T2 TDATA/TPDATA 7 T7289A-PL 22 8 T7289A-EL 21 VDDD LP1 9 20 R2 LP2 10 19 GNDD LP3 11 18 EC1 ALMT 12 17 EC2 RBC 13 16 EC3 TBC 14 15 BCLK 5-4349(C) Figure 2. Pin Diagram 2 Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface Pin Information (continued) Table 1. Pin Descriptions This table refers to a cleared pin as low (0) and a set pin as high (1). Pin 1 Symbol LOS Type* Ou 2 LOC Ou 3 BZSC/TNDATA Id 4 BPV/RNDATA O 5 6 RCLK RDATA /RPDATA O O 7 8 TCLK TDATA/TPDATA I I 9 LP1 Iu 10 LP2 Iu 11 LP3 Iu 12 ALMT Iu 13 RBC Id Name/Function Loss of Signal (Active-Low). This pin is cleared upon loss of the data signal at the receiver inputs. Loss of Clock (Active-Low). This pin is cleared when SD = 1 and LOS = 0, indicating that a loss of clock has occurred. When LOC = 0, no transitions occur on the RCLK and RDATA outputs. A valid clock must be present at BCLK for this function to operate properly. B8ZS Enable/Transmit Data Negative Rail. If dual = 0, this pin is set to insert a B8ZS substitution code on the transmit side and to remove the substitution code on the receive side. If dual = 1, this pin is used as the transmit data negative rail. Bipolar Violation/Receive Data Negative Rail. If dual = 0, this pin is set upon detection of a bipolar violation on the receive-side input after the removal of the B8ZS substitution code that contains legal violations. If dual = 1, this pin is used as the receive data negative rail. Receive Clock. Output receive clock signal to the terminal equipment. Receive Data (Active-Low)/Receive Data Positive Rail. If dual = 0, this pin is used as 1.544 Mbits/s inverted unipolar output data with a 100% duty cycle. If dual = 1, this pin is used as the transmit data positive rail. Transmit Clock. DS1 input clock signal (1.544 MHz 130 ppm). Transmit Data/Transmit Data Positive Rail. If dual = 0, this pin is used as 1.544 Mbits/s unipolar input data. If dual = 1, this pin is used as the transmit data positive rail. Loopback 1 Enable (Active-Low). This pin is cleared for a full local loopback (transmit converter output to receive converter input). Most of the transmit and receive analog circuitry is exercised in this loopback. Loopback 2 Enable (Active-Low). This pin is cleared for a remote loopback (DSX to DSX). In loopback 2, a high on TBC (pin 14) inserts the blue signal on the transmit side. Loopback 3 Enable (Active-Low). This pin is cleared for a digital local loopback. Only the transmit and receive digital sections are exercised in this loopback. Alarm Test Enable (Active-Low). This pin is cleared, forcing LOS = 0, LOC = 0, and BPV = 1 for testing without affecting data transmission. Receive Blue Control. This pin is set to insert the blue signal on the receive side. During single-rail mode, RDATA is cleared. During dual-rail mode, RPDATA and RNDATA toggle at half the blue clock rate. Blue clock must be present. * I = input, O = output, Iu = input with pull-up, Id = input with pull-down, Ou = output with pull-up. See Table 2. Lucent Technologies Inc. 3 Data Sheet January 1998 T7289A DS1 Line Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin 14 Symbol TBC Type Id 15 BCLK I 16 EC3 Id 17 EC2 Id 18 EC1 Id 19 20 21 22 23 GNDD R2 VDDD T2 DUAL -- O -- O Id 24 25 26 VDDA GNDA SD -- -- Id 27 28 R1 T1 I I Name/Function Transmit Blue Control (AIS). This pin is set to insert the blue signal (all 1s) on the transmit side. This control has priority over a loopback 2 if both are operated simultaneously. Blue Clock. DS1 blue clock signal (1.544 MHz 130 ppm). This clock is independent of the transmit clock. Equalizer Control 3. One of three control leads for selecting transmit equalizers. Equalizer Control 2. One of three control leads for selecting transmit equalizers. Equalizer Control 1. One of three control leads for selecting transmit equalizers. Digital Ground. Transmit Bipolar Ring. Negative bipolar transmit output. 5 V Digital Supply (10%). Transmit Bipolar Tip. Positive bipolar transmit output. Dual-Rail Mode Select. This pin is cleared for single-rail mode and set for dual-rail mode. 5 V Analog Supply (10%). Analog Ground (10%). Shutdown. This pin is set forcing RCLK high, RDATA high, and LOC low (for single-rail operation) if a loss of signal is detected (LOS = 0). For dual-rail mode, RPDATA and RNDATA are forced low. Receive Bipolar Ring. Negative bipolar receive input. Receive Bipolar Tip. Positive bipolar receive input. * I = input, O = output, Iu = input with pull-up, Id = input with pull-down, Ou = output with pull-up. See Table 2. Table 2. Equalizer Control Other bit combinations represent test modes not to be used for normal operation. Distance to DSX (Ft.)* (Applies Only to 22-gauge PIC [ABAM] Cable) 0--133 133--267 267--400 400--533 533--655 Maximum Cable Loss (dB at 772 kHz) EC1 EC2 EC3 0.6 1.2 1.8 2.4 3 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 * Use maximum loss figures for other cable types. 4 Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface Overview The T7289A device is a fully integrated DS1 line interface that requires only two line-interface transformers and three input termination resistors to provide a bidirectional line interface between a DS1 cross connect (DSX) and terminal equipment. A typical application diagram is shown in Figure 3. This device is specified for use with 22-gauge, plastic-insulated ABAM cable, as well as other cable types. The circuit is divided into three main blocks: transmit converter, receive converter, and logic. The transmit and receive converters process information signals through the device in the transmit and receive directions, respectively; the logic is the control and status interface for the device. RECEIVED DATA T1 500 RDATA/RPDATA RECEIVE INPUT 200 500 BPV/RNDATA RCLK R1 1:2 VDDD T7289A DS1 LINE INTERFACE TRANSMITTED DATA +5 V VDDA 1 F GNDD GNDA T2 100 TRANSMIT OUTPUT LOAD R2 TDATA/TPDATA BZSC/TNDATA TCLK 1.14:1 (DS1) 5-4350(C) Note: Lucent 2745 family pulse transformers for through-hole mounting or Lucent 2758 family pulse transformers for surface mounting are recommended. Figure 3. Typical Application Diagram for Bipolar Signal Interfacing Lucent Technologies Inc. 5 Data Sheet January 1998 T7289A DS1 Line Interface Transmit Converter The output pulse waveform consists of four distinct levels: overshoot, pulse, backswing, and tail. They are produced by a high-speed D/A converter and are driven onto the line by using low-impedance output buffers. There are five different pulse shapes, corresponding to 133-ft. increments of cable, that are obtained by setting the appropriate equalizer control inputs. The positive and negative pulses meet the amplitude, rise and fall time, overshoot, undershoot, template, and power requirements for the office DSX cross connect as given in Compatibility Bulletin 119 (CB119). A typical DS1 output waveform at the DSX relative to the CB119 template is shown in Figure 4. The analog circuitry is shown in Figure 5. NORMALIZED AMPLITUDE (V) The line-interface transmission format is return-to-zero, bipolar alternate mark inversion (AMI), requiring transmission and sensing of alternately positive and negative pulses. During single-rail operation, the transmit converter accepts unipolar data at TDATA and converts the signal to a balanced bipolar data signal. Binary 1s in the TDATA data stream become pulses of alternating polarity transmitted between the two output rails, T2 and R2. For dual-rail operation, a binary 1 on TPDATA results in the transmission of a positive pulse between T2 and R2, and a binary 1 on TNDATA results in a negative pulse. Binary 0s are transmitted as null pulses. All necessary transmit pulse shaping is done on-chip, eliminating the need for external shaping networks. This is done by shaping the pulses at the bipolar output (T2, R2) according to the selected equalizer control (EC1--EC3) inputs (see Table 2). The clock multiplier shown in Figure 5 produces the high-speed timing waveforms needed by the D/A converter. The clock multiplier also eliminates the need for the tightly controlled transmit clock duty cycle usually required in discrete implementations. Transmitter specifications are given in Table 7. 1.0 CB119 TEMPLATE 0.5 0 T7289A OUTPUT PULSE SHAPE -0.5 0 250 500 750 1000 1250 TIME (ns) 5-4351(C) Figure 4. Typical T7289A Output Waveform at DSX 6 Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface Transmit Converter (continued) LOS LP1 DIGITAL SIGNAL DETECTOR ANALOG SIGNAL DETECTOR RECEIVER ANALOG INPUT T1 R1 PDATA NDATA RPDATA M U X R2 TRANSMIT OUTPUT DRIVERS D/A SELECTABLE PULSE EQUALIZATION RDATA/RPDATA BPV/RNDATA DATA/CLOCK RNDATA RECOVERY RCLK RCLK TRANSMIT AND RECEIVE LOGIC TP DATA T2 SD TN DATA 4 CLOCK MULTIPLIER TDATA/TPDATA BZSC/TNDATA TCLK TCLK TIMING SIGNALS EC1 EC2 EC3 DUAL 5-4352(C) Figure 5. T7289A Analog Block Diagram Receive Converter The receive converter accepts bipolar input signals (T1, R1), coupled through a receive transformer, from the cross connect over a maximum of 655 ft. of 22gauge PIC (ABAM) cable. The received signal is rectified while the amplitude and rise time are restored. These input signals are peak-detected and sliced by the receiver front end, producing the digital signals PDATA and NDATA (Figure 5). The timing is extracted by means of phase-locked loop (PLL) circuitry that locks an internal, free-running, current-controlled oscillator (ICO) to the 1.544 MHz (DS1 signal) component. The PLL employs a 3-state phase detector and a lowvoltage/temperature coefficient ICO. The ICO freerunning frequency is trimmed to within 2.5% of the data rate at wafer probe, with VDD = 5.0 V and TA = 25 C. For all operating conditions (see Operating Conditions section), the free-running oscillator frequency deviates from the data rate by less than 6%, alleviating the problem of harmonic lock. Lucent Technologies Inc. For robust operation, the PLL is augmented with a frequency-acquisition capability. The frequency acquisition circuitry is intended to guarantee proper phaselocking during start-up conditions, such as powerup or data activation. Once the T7289A device is phaselocked to data, the frequency-acquisition mode will not be activated. A continuous (i.e., ungapped, unswitched) 1.544 MHz reference clock must be present at TCLK to enable the frequency-acquisition circuitry. However, the receive PLL will operate even in the absence of TCLK. Because the clock output of the receive converter is derived from the ICO, a free-running clock can be present at the output of the receive converter without data being present at the input. A shutdown pin (SD) is provided to block this clock, if desired, to eliminate the free-running clock upon loss of the input signal. 7 Data Sheet January 1998 T7289A DS1 Line Interface Receive Converter (continued) Two methods of loss-of-signal detection are used in this chip. The analog signal detector shown in Figure 5 uses the output of the receiver peak detector to determine if a signal is present at T1 and R1. If the input amplitude drops below approximately 0.5 V, the analog detector output becomes active. Hysteresis (250 mV) is provided in the analog detector to eliminate LOS chattering. In addition, the digital signal detector counts 0s in the recovered data. If more than 128 consecutive 0s occur, the digital signal detector becomes active. In normal operation, the detector outputs are ORed together to form LOS; however, in loopback 1, only the digital signal detector is used to monitor the looped signal. Table 3 describes the operation of the shutdown, LOS, and LOC functions in normal operation and in loopback 1. The PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. Low jitter sensitivity to power supply noise allows compact line-card layouts that employ many line interfaces on one board. The minimum input jitter tolerance, as specified in AT&T Publication 43802, and the measured T7289A device jitter tolerance are shown for the DS1 rate in Figure 6. The data shown is typical for measurement to a BER of 10-6. Subtracting approximately 0.02 U.I. from the given data yields the jitter accommodation for error-free operation. Receiver specifications are shown in Table 8. Table 3. Shutdown, LOS, and LOC Truth Table x = don't care. 8 LP1 SD 1 1 1 1 0 0 0 0 x 0 0 1 1 0 0 1 1 x Inputs ALMT Input Signal at T1, R1 1 Active 1 No Signal 1 Active 1 No Signal 1 x 1 x 1 x 1 x 0 x Loopback 1 Signal x x x x Active No Signal Active No Signal x LOS LOC Outputs Receive Side 1 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1 0 0 Normal Free-running VCO Normal No output Normal loopback Free-running VCO Normal loopback No output Unaffected Active LOS Detectors Analog and digital Analog and digital Analog and digital Analog and digital Digital only Digital only Digital only Digital only x Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface Receive Converter (continued) BELLCORE TR-TSY-00170 AND PUB 43801 SPECIFICATION (1/8 PATTERN) 10.0 INPUT JITTER AMPLITUDE (U.I. PEAK-TO-PEAK) PUB 43802 SPECIFICATION (220 - 1 PATTERN) (10, 5) MEASURED T7289A PERFORMANCE BER = 10-6 (220 - 1 PATTERN) (300, 10) MEASURED T7289A PERFORMANCE BER = 10-6 (1/8 PATTERN) (500, 5) 1.0 0.1 MEASURED DATA POINTS 220 - 1 PATTERN 1/8 PATTERN JITTER JITTER JITTER JITTER FREQUENCY AMPLITUDE FREQUENCY AMPLITUDE (kHz) (U.I.pp) (kHz) (U.I.pp) 2.0 6.5 20 10 8.0 1.1 8.0 1.8 20 0.66 20 0.7 30 0.52 30 0.45 40 0.49 40 0.45 50 0.48 50 0.45 60 0.48 70 0.48 0.01 0.1 (10k, 0.3) (8k, 0.1) 1.0 (70k, 0.3) (50k, 0.1) 10 100 JITTER FREQUENCY (kHz) 5-4353(C) Figure 6. DS1 Jitter Tolerance Digital Logic The logic provides alarms, optional B8ZS coding, bluesignal insertion (AIS) circuits, and maintenance loopbacks. It accepts dual-rail or single-rail data patterns. Single-Rail/Dual-Rail Option To implement the rail-select feature, the dual pin (pin 23) is cleared for single-rail mode and set for dual-rail mode. When single-rail mode is selected, pin 8 (TDATA/ TPDATA) accepts transmit data and pin 6 (RDATA/ RPDATA) outputs inverted receive data. When dual-rail Lucent Technologies Inc. mode is selected, pin 8 (TDATA/TPDATA) accepts the positive rail transmit data, and pin 3 (BZSC/TNDATA) is reconfigured to accept negative rail transmit data. Pin 6 (RDATA/RPDATA) outputs positive rail receive data, and pin 4 (BPV/RNDATA) is reconfigured to output negative rail receive data. In dual-rail mode, the B8ZS and bipolar violation functions are disabled. For single-rail operation, TDATA is active-high and RDATA is active-low. For dual-rail operation, TPDATA, TNDATA, RPDATA, and RNDATA are all active-high. This interface scheme is consistent with the dual-rail interfaces of other Lucent Line Interface products. 9 Data Sheet January 1998 T7289A DS1 Line Interface Digital Logic (continued) Single-Rail/Dual-Rail Option (continued) Alarms Loopback Paths An independent loss-of-clock (LOC) output is provided so that loss of clock is detected when the shutdown option is in effect. LOS and LOC can be wire-ORed to produce a single alarm. A bipolar violation (BPV) output is included, giving an alarm each time a violation (two or more successive 1s on a rail) occurs. The violation alarm output is held in a latch for one cycle of the internal clock (RCLK). In the B8ZS mode, bipolar violations within the legal substitution code are not detected and, therefore, do not produce an alarm. The bipolar violation function is disabled when dual = 1. An alarm test pin (ALMT) is provided to test the alarm outputs, LOS, LOC, and BPV. Clearing this pin forces the alarm outputs to the alarm state without affecting data transmission. In order to meet the requirement that the system not report LOS for a string of <100 consecutive 0s and that LOS be reported for 250 consecutive 0s, the digital LOS threshold counter is set at 128. However, between 32 and 64 consecutive 0s, the device changes from locking on incoming data to locking on TCLK. If the phase of TCLK is sufficiently different from the received data, the device can count both 1s and 0s as 0s. This can cause the digital LOS counter to exceed its threshold, even though the number of consecutive 0s in the data is less than 100. B8ZS Option The T7289A device contains a B8ZS encoder and decoder that can be selected by setting the BZSC pin. This allows the encoder to substitute a zero-substitution code for eight consecutive 0s detected in the data stream, as illustrated in Table 4. A V represents a violation of bipolar code, and a B represents a bipolar pulse of correct polarity. The decoder detects the zero-substitution code and reinserts eight 0s in the data stream. The B8ZS option is disabled when dual = 1. Table 4. B8ZS Substitution Code Before B8ZS After B8ZS 00000000 000VB0VB Blue-Signal (AIS) Generators There are two blue-signal generators in this device. If RBC = 1, an all-1s signal is output on the receive data 10 output pin(s). If TBC = 1, a bipolar all-1s signal is transmitted through T2 and R2 and into the network. Both receive and transmit blue signals are synchronous with BCLK. The T7289A device has three independent loopback paths that are activated by clearing the respective control inputs, LP1, LP2, or LP3. Loopback 1 bridges the data stream from the transmit converter (transmit converter included) to the input of the receive converter. The maintenance loop includes most of the internal circuitry. Loopback 2 provides a loopback of data from the bipolar inputs (T1, R1) and the associated recovered clock to the bipolar outputs of the transmit converter (T2, R2). The receive front end, receive PLL, and transmit driver circuitry are all exercised. The loop can be used to isolate failures between systems. Loopback 3 loops the data stream as in loopback 1, but bypasses the transmit and receive converters. The blue signal can be transmitted towards the DSX when in this loopback. Loopbacks 2 and 3 can be operated simultaneously to provide transmission loops in both directions. Device Anomaly T7289A-EL, T7289A-PL, T7289A-EL2, and T7289A-PL2 The T7289A-EL, T7289A-PL, T7289A-EL2, and T7289A-PL2 devices have been found to be sensitive to slow powerup ramp on the +5 V device supply. In general, if the powerup time is >50 s, the device may not operate properly. The device must be power-cycled with a power-ramp interval of less than 50 s to clear the condition. This anomaly is corrected in the T7289A-EL4 and T7289A-PL4. T7289A-EL, T7289A-PL, T7289A-EL2, T7289A-PL2, T7289A-EL3, and T7289A-PL3 The T7289A-EL, T7289A-PL, T7289A-EL2, T7289APL2, T7289A-EL3, and T7289A-PL3 devices have been found to be sensitive to voltage surges on the transmit analog interface leads. The device may latch-up when excessive voltage surges are present on the line. The device must be power-cycled to clear the condition. The immunity to voltage surges has been enhanced in the T7289A-EL4 and T7289A-PL4. Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter dc Supply Voltage Range Power Dissipation Storage Temperature Range Symbol VDD Pdis Tstg Min -0.5 -- -65 Max 6.5 500 125 Unit V mW C Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Human-Body Model ESD Threshold Device Voltage T7289A >2000 V Electrical Characteristics Operating Conditions TA = -40 C to +85 C; VDD = 5 V 10% Table 5. Power Specifications Parameter Power Dissipation* Symbol PD Min -- Typ 115 Max 138 Unit mW * Measurement conditions with 50% 1s on the transmit side, TA = 25 C, and equalizer settings: EC1 = 0, EC2 = 1, EC3 = 0 (VDD = 5 V). Power supply current varies by less than 5% with variations in temperature and power supply voltage. Lucent Technologies Inc. 11 Data Sheet January 1998 T7289A DS1 Line Interface Electrical Characteristics (continued) Operating Conditions (continued) Table 6. Logic Interface Electrical Characteristics Parameter Input Voltage: Low High Output Voltage (except LOS and LOC): Low High High, CMOS Output Voltage (LOS, LOC): Low High Input Capacitance Load Capacitance Symbol Condition Min Max Unit VIL VIH -- -- GNDD 2.0 0.8 VDDD V V VOL VOH VOHC IOL = 4.9 mA IOH = -4.9 mA IOHC = -0.49 mA -- 2.4 3.5 0.4 -- VDDD V V V VOL VOH CI CL IOL = 4.9 mA IOHC = -10 A -- -- -- 3.5 20 40 0.4 VDDD -- -- V V pF pF Internal pull-up devices are provided on the following input leads: LP1, LP2, LP3, and ALMT. Internal pull-down devices are provided on the following leads: SD, RBC, BZSC/TNDATA, TBC, DUAL, EC1, EC2, and EC3. The internal pull-up or pull-down devices require the input to source or sink no more than 20 A. Output pull-up is provided on leads LOS and LOC. Table 7. Transmitter Specifications Parameter Output Pulse Amplitude (at the DSX) Pulse Width (50%) Output Power Levels: 2 kHz Band at 772 kHz 2 kHz Band at 1544 kHz Positive/Negative Pulse Imbalance Rise/Fall Time (20%--80%) Output Termination Output Transformer Turns Ratio PSRR: dc < Frequency < 200 kHz 200 kHz < Frequency < 500 kHz 500 kHz < Frequency < 5 MHz Min 2.4 333 Typ 3.0 350 Max 3.6 362 Unit V ns 12.6 -29 -- -- 95 1:1.12 16.5 -39 -- -- 100 1:1.14 17.9 -- 0.5 50 105 1:1.16 dBm dB* dB ns -- 35 25 8 -- -- -- -- -- -- dB dB dB * Below the power at 772 kHz. Total power difference. 12 Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface Electrical Characteristics (continued) Operating Conditions (continued) Table 8. Receiver Specifications Parameter Receiver Sensitivity (at input of device) PLL: 3 dB Bandwidth Peaking Allowed Cable Loss* at BER = 10-9 Input Density (1s) ICO Free-running Frequency Error Input Transformer Turns Ratio Input Termination Input Resistance, R1 or T1 Condition -- Min 0.85 Typ -- Max -- Unit Vp 1/8 input 1/8 input VDD = 5.0 V; Vac on VDD = 0.5 Vpp, from dc to 4 MHz Maximum number of consecutive 0s = 15 -- -- -- Each Input to Ground -- -- -- 33 1.2 12 -- 2.0 9 kHz dB dB 12.5 -- -- % -- 1:1.9 -- 0.9 -- 1:2.0 100 -- 6 1:2.1 -- 3.0 % -- k * Minimum sensitivity (maximum cable loss limit) occurs when the frequency of Vac is near the clock rate. Timing Characteristics All duty cycle and timing relationships are referenced to a TTL 1.4 V threshold level. Loss-of-Clock Indication Timing The clock must be absent 5.18 s to guarantee a loss-of-clock indication. However, it is possible to produce a lossof-clock indication if the clock is absent for 2.59 s depending on the timing relationship of the interruption with respect to the timing cycle. The returning clock must be present 5.18 s to guarantee a normal condition on the loss-of-clock pin (LOC). However, the loss-of-clock indication can return to normal immediately, depending on the timing relationship of the signal return with respect to the timing cycle. Table 9. System Interface Symbol tTCLTCL tTCHTCL tTDVTCL tTCLTDV tr tf tRCHRDV tRDVRCH tRCLRDV Description TCLK Clock Period TCLK Duty Cycle Data Setup Time, TDATA to TCLCK Data Hold Time, TCLK to TDATA Clock Rise Time (10%--90%) Clock Fall Time (10%--90%) Data Hold Time, RCLK to RDATA, BPV Data Setup Time, RDATA, BPV to RCLK Propagation Delay, RCLK to RDATA Min * 40 50 40 -- -- 227 187 -- Typ 647.7 50 -- -- -- -- -- -- -- Max * 60 -- -- 40 40 -- -- 40 Unit ns % ns ns ns ns ns ns ns * A tolerance of 130 ppm. Lucent Technologies Inc. 13 Data Sheet January 1998 T7289A DS1 Line Interface Timing Characteristics (continued) Loss-of-Clock Indication Timing (continued) tTCLTCL tr tf tr tf TCLK TDATA OR TPDATA TNDATA tTDVTCL tTCLTDV tRCLRDV RCLK tRDVRCH BPV/RDATA OR RPDATA RNDATA tRCHRDV 5-4361(C) Figure 7. Timing Diagram (Single-Rail or Dual-Rail) 14 Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface Outline Diagrams 28-Pin, Plastic DIP Dimensions are in millimeters. L N B 1 W PIN #1 IDENTIFIER ZONE H SEATING PLANE 0.38 MIN 2.54 TYP Number of Pins (N) 28 0.023 MAX 5-4410.R1 Package Dimensions (DIP) Maximum Length Including Leads (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 37.34 13.97 15.49 5.59 Lucent Technologies Inc. 15 Data Sheet January 1998 T7289A DS1 Line Interface Outline Diagrams (continued) 28-Pin, Plastic SOJ Dimensions are in millimeters. L N B 1 PIN #1 IDENTIFIER ZONE W H SEATING PLANE 0.10 1.27 TYP 0.020 MAX 0.64 MIN 5-4413.R1 Number of Pins (N) Package Dimensions (SOJ) Maximum Length Including Leads (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 18.03 7.62 8.81 3.18 28 Ordering Information 16 Device Code Package Temperature T - 7289A - - - PL4 T - 7289A - - - EL4 28-Pin DIP 28-Pin SOJ -40 C to +85 C -40 C to +85 C Comcode (Ordering Number) 107056699 107056673 Lucent Technologies Inc. Data Sheet January 1998 T7289A DS1 Line Interface DS97-196TIC Replaces DS92-072SMOS Catalog CA95-003TIC Version to Incorporate the Following Updates 1. Data sheet format. 2. Note: CA95-003TIC version of data sheet had device advisory AY93-025TCOM incorporated in it. Lucent Technologies Inc. 17 T7289A DS1 Line Interface Interactive Terminal Transmission Convergence Preliminary Data Sheet January 1998 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright (c) 1997 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. January 1998 DS97-196TIC (Replaces DS92-072SMOS) Printed On Recycled Paper