MO SEL VITELIC
1
V43658Y04VATG-75
64MB 168-PIN 133 MHZ SDRAM
UNBUFFERED SODIMM
3.3VOLT, 8Mx64
PRELIMINARY
V43658Y04VATG-75 Rev. 1.4 September 2001
Features
■JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
■Serial Presence Detect with E2PROM
■Nonbuffered
■Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
■Single +3.3V (± 0.3V) Power Supply
■All Device Pins are LVTTL Compatible
■4096 Refresh Cycles every 64 ms
■Self-Refresh Mode
■Internal Pipelined Operation; Column Address
can be changed every System Clock
■Programmable Burst Lengths: 1, 2, 4, or 8
■Auto Precharge and Precharge all Banks by A10
■Data Mask Function by DQM
■Mode Register Set Programming
■Programmable (CAS Latency: 2, 3 Clocks)
Description
The V43658Y04VATG-75 memory module is
organized 8,388,608 x 64 bits in a 144 pin
SODIMM. The 8M x 64 memory module uses 4
Mosel-Vitelic 8M x 16 SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
Part Number Speed
Grade Configuration
V43658Y04VATG-75 -75
(133 MHz) 8M x 64
1
Pin 2 on Backside Pin 144 on Backside
59 61 143
8M x 16 8M x 16 8M x 16 8M x 16
2
V43658Y04VATG-75 Rev. 1.4 September 2001
MO SEL VITELIC
V43658Y04VATG-75
Pin Configurations (Front Side/Back Side)
Note:
1. RAS,CAS,WECASx, CSx are active low signals.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
NC
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0–A11, BA0, BA1 Address, Bank Select
DQ0–DQ63 Data Inputs/Outputs
RAS Row Address Strobes
CAS Column Address Strobes
WE Write Enable
CS0,CS1Chip Select
DQMB0–DQMB7 Output Enable
CKE0, CKE1 Clock Enable
CLK0–CLK1 Clock
SDA Serial Input/Output
SCL Serial Clock
VDD Power Supply
VSS Ground
NC No Connect (Open)
MO SEL VITELIC
V43658Y04VATG-75
3
V43658Y04VATG-75 Rev. 1.4 September 2001
Part Number Information
Block Diagram
V 4 3 65 8 Y 0 4 V A T G -75
SDRAM
3.3V WIDTH
DEPTH
168 PIN REGISTERED
DIMM X16 COMPONENT
REFRESH
RATE 4K 4 BANKS
LVTTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G=GOLD
SPEED
75 = PC133 CL3
MOSEL VITELIC
MANUFACTURED
CS0
WE
U0–U7
A0–A11, BA0, BA1
VDD
U0–U3
CKE0
U4–U7
CKEI
U0–U3
RAS
U0–U3
CAS
U0–U7 U0, U1
CLK0
VSS
U2, U3
10Ω
SCL SDA
10Ω
SPD
A0 A1 A2
DQMB4
DQMB5
DQ32–39
DQ40–47
UDQM
U2
LDQM
DQMB0
DQMB1
DQ0–7
DQ8–15
UDQM
U0
LDQM
DQMB6
DQMB7
DQ43–54
DQ55–63
UDQM
U3
LDQM
DQMB2
DQMB3
DQ16–23
DQ24–31
UDQM
U1
LDQM
CSWE CSWE
CSWE CSWE
4
V43658Y04VATG-75 Rev. 1.4 September 2001
MO SEL VITELIC
V43658Y04VATG-75
Serial Presence Detect Information
A serial presence detect storage device –
E2PROM –is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintotheE
2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
SPD-Table for -10 PC modules:
Byte
Number Function Described SPD Entry Value
Hex Value
133 MHz
-75
0 Number of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses (without BS bits) 12 0C
4 Number of Column Addresses (for x16 SDRAM) 9 09
5 Number of DIMM Banks 1 01
6 Module Data Width 64 40
7 Module Data Width (continued) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75
10 SDRAM Access Time from Clock at CL=3 5.4 ns 54
11 Dimm Config (Error Det/Corr.) none 00
12 Refresh Rate/Type Self-Refresh, 15.6µs80
13 SDRAM width, Primary x16 10
14 ErrorCheckingSDRAMDataWidth n/a/x8 00
15 Minimum Clock Delay from Back to Back
Random Column Address tccd =1CLK 01
16 Burst Length Supported 1, 2, 4, 8 0F
17 Number of SDRAM Banks 4 04
18 Supported CAS Latencies CL = 3 04
19 CS Latencies CS Latency = 0 01
20 WE Latencies WL = 0 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E
23 Minimum Clock Cycle Time at CAS Latency = 2 Not Supported 00
24 Maximum Data Access Time from Clock for CL = 2 Not Supported 00
25 MinimumClockCycleTimeatCL=1 NotSupported 00
26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00
27 Minimum Row Precharge Time tRP 20 ns 14
28 Minimum Row Active to Row Active Delay tRRD 15 ns 0F
29 Minimum RAS to CAS Delay tRCD 20 ns 14
MO SEL VITELIC
V43658Y04VATG-75
5
V43658Y04VATG-75 Rev. 1.4 September 2001
Absolute Maximum Ratings
30 Minimum RAS Pulse Width tRAS 45 ns 2D
31 Module Bank Density (Per Bank) 64 MByte 10
32 SDRAM Input Setup Time 1.5 ns 15
33 SDRAM Input Hold Time 0.8 ns 08
34 SDRAM Data Input Setup Time 1.5 ns 15
35 SDRAM Data Input Hold Time 0.8 ns 08
36-61 Superset Information (May be used in Future) 00
62 SPD Revision Revision 1.2 12
63 Checksum for Bytes 0 - 62 14
64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40
65-71 Manufacturer’s JEDEC ID Code (cont.) 00
72 Manufacturing Location 1 = US, 2 = Taiwan
73-90 Module Part Number (ASCII) V43658Y04VATG-75
91-92 PCB Identification Code Current PCB Revision
93 Assembly Manufacturing Date (Year) Binary Coded year (BCD)
94 Assembly Manufacturing Date (Week) Binary Coded week (BCD)
95-98 Assembly Serial Number byte 95 = LSB, byte 98 =
MSB
99-125 Reserved 00
126 Intel Specification for Frequency 64
127 Supported frequency 8D
128+ Unused Storage Location 00
Parameter Max. Units
VoltageonVDDSupplyRelativetoV
SS -1 to 4.6 V
VoltageonInputRelativetoV
SS -1 to 4.6 V
Operating Temperature 0to+70 °C
Storage Temperature -55to125 °C
Power Dissipation 1.5 W
SPD-Table for -10 PC modules: (Continued)
Byte
Number Function Described SPD Entry Value
Hex Value
133 MHz
-75
6
V43658Y04VATG-75 Rev. 1.4 September 2001
MO SEL VITELIC
V43658Y04VATG-75
DC Characteristics
TA=0°Cto70°C; VSS =0V;V
DD,V
DDQ =3.3V±0.3V
Capacitance
TA=0°Cto70°C; VDD =3.3V± 0.3V, f = 1 MHz
Standby and Refresh Currents1
TA=0°Cto70°C, VCC =3.3V±0.3V
Symbol Parameter
Limit Values
UnitMin. Max.
VIH Input High Voltage 2.0 VCC+0.3 V
VIL Input Low Voltage –0.5 0.8 V
VOH Output High Voltage (IOUT =–2.0 mA) 2.4 —V
VOL Output Low Voltage (IOUT =2.0mA) —0.4 V
II(L) Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V) –10 10 µA
IO(L) Output leakage current
(DQ is disabled, 0V < VOUT <V
CC)–10 10 µA
Symbol Parameter Limit Values Unit
CI1 Input Capacitance (A0 to A11, RAS,CAS,WE) 105 pF
CI2 Input Capacitance (CS0,CSI)32pF
CICL Input Capacitance (CLK0-CLK1) 40 pF
CI3 Input Capacitance (CKE0, CKEI) 65 pF
CI4 Input Capacitance (DQMB0-DQMB7) 20 pF
CSC Input Capacitance (SCL, SA0-2) 8 pF
CIO Input/Output Capacitance 10 pF
Symbol Parameter Test Conditions 8M x 64 Unit Note
ICC1 Operating Current Burst length = 4, CL = 3
tRC>=t
RC(min), tCK>=t
CK(min) 680 mA 1,2
ICC2P Precharged Standby Current in Power
Down Mode CKE< = VIL(max), tCK>=t
CK(min) 6 mA
ICC2N Precharged Standby Current in
Non-Power Down Mode CKE> = VIH(min), tCK>=t
CK(min), Input
changedoncein3cycles 180 mA CS =
High
ICC3P Active Standby Current in Power
Down Mode CKE< = VIL(max), tCK>=t
CK(min) 40 mA
ICC3N Active Standby Current in Non-Power
Down Mode CKE> = VIH(min), tCK>=t
CK(min), Input
changed one time 220 mA CS =
High
ICC4 Burst Operating Current tRC = Infinite, CL = 3, tCK>=t
CK(min) 440 mA 1, 2
ICC5 Auto Refresh Current tRC>= tRC(min) 1000 mA 1,2
ICC6 Self Refresh Current CKE = <0,2 V 6 mA 1,2
L-Version 3.2 mA
MO SEL VITELIC
V43658Y04VATG-75
7
V43658Y04VATG-75 Rev. 1.4 September 2001
AC Characteristics 3,4
TA=0°to 70°C; VSS =0V;V
CC =3.3V±0.3V, tT=1ns
# Symbol Parameter
Limit Values
Unit Note
-75
Min. Max.
Clock and Clock Enable
1t
CK Clock Cycle Time
CAS Latency = 3
CAS Latency = 2 7.5
10 –
–
s
ns
ns
2t
CK Clock Frequency
CAS Latency = 3
CAS Latency = 2 –
–133
100 MHz
MHz
3t
AC Access Time from Clock
CAS Latency = 3
CAS Latency = 2 –
_5.4
6ns
ns
2, 4
4t
CH Clock High Pulse Width 2.5 –ns
5t
CL Clock Low Pulse Width 2.5 –ns
6t
TTransition Tim 0.3 1.2 ns
Setup and Hold Times
7t
IS Input Setup Time 1.5 –ns 5
8t
IH Input Hold Time 0.8 –ns 5
9t
CKS Input Setup Time 1.5 –ns 5
10 tCKH CKE Hold Time 0.8 –ns 5
11 tRSC Mode Register Set-up Time 15 –ns
12 tSB Power Down Mode Entry Time 0 7.5 ns
Common Parameters
13 tRCD Row to Column Delay Time 20 –ns 6
14 tRP Row Precharge Time 20 –ns 6
15 tRAS Row Active Time 45 100K ns 6
16 tRC Row Cycle Time 60 –ns 6
17 tRRD Activate(a) to Activate(b) Command Period 15 –ns 6
18 tCCD CAS(a) to CAS(b) Command Period 1 –CLK
Refresh Cycle
19 tREF Refresh Period (4096 cycles) —64 ms
20 tSREX Self Refresh Exit Time 10 ns
Read Cycle
21 tOH Data Out Hold Time 2.7 –ns 2
22 tLZ Data Out to Low Impedance Time 1 –ns
23 tHZ Data Out to High Impedance Time –5.4 ns 7
24 tDQZ DQM Data Out Disable Latency –2CLK
Write Cycle
25 tWR Write Recovery Time 1 –CLK
26 tDQW DQM Write Mask Latency 0 –CLK
8
V43658Y04VATG-75 Rev. 1.4 September 2001
MO SEL VITELIC
V43658Y04VATG-75
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up,then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL =0.4VandVIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT= 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tTis longer than 1 ns, a time (tT-1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up”the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11. tDAL is equivalent to tDPL +t
RP.
Package Diagram
1.4V
1.4V
tSETUP tHOLD
tAC tAC
tLZ tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+1.4V
50 Ohm
2.4V
0.4V
tT
tCL
tCH
I/O
Measurement conditions for
tac and toh
50 pF
MO SEL VITELIC
V43658Y04VATG-75
9
V43658Y04VATG-75 Rev. 1.4 September 2001
Package Diagram
144 Pin SODIMM
2.661
1.25
0.039
0.09
0.787
1
Pin 2 on Backside 3.3V Pin 144 on Backside
28 29 143
NOTE:
1. All dimensions in inches.
Tolerances ±0.005 unless otherwise specified.
10
V43658Y04VATG-75 Rev. 1.4 September 2001
MO SEL VITELIC
V43658Y04VATG-75
Label Information
CL = 3 or 2 (CLK)
tRCD = 3 or 2 (CLK)
tRP = 3 or 2 (CLK) tAC = 5.4 ns
XXXU
UNBUFFERED DIMM
PC133 54
JEDEC SPD Revision 2
2
V436616R24XXX-XX 128MB CLX
PC133U-XXX-542-A
0130-K682165
Assembly in Taiwan
A
Gerber file Intel® PC100 x 16 Based
-- -
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
CAS Latency
2 = CL2
3 = CL3
Criteria of PC100 or PC133
(refer to MVI datasheet)
V436664S24VATG-10PC
512MB CLX
8
V43658Y04VATG-75 64MB CLX
16 Based
MO SEL VITELIC
WORLDWIDE OFFICES V43658Y04VATG-75
© Copyright , MOSEL VITELIC Inc. Printed in U.S.A.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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