1
Features
•Compatible with MCS-51® Products
•32K Bytes of Reprogrammable Flash Memory
•Endurance: 1000 Write/Erase Cycles
•4V to 5.5V Operating Range
•Fully Static Operation: 0 Hz to 33 MHz
•Three-level Program Memory Lock
•512 x 8-bit Internal RAM
•32 Programmable I/O Lines
•Three 16-b it Timer/Co u nter s
•Eight Interrupt Sources
•Programmable Serial Channel
•Low -po w er Idle and Po w er-do wn Mode s
•Interrupt Reco ve ry fr om Power - down Mode
•Hardware Watchdog Timer
•Dual Data Pointer
•Power-off Flag
Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontr oller with
32K bytes of Flash programmable read only memor y and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonv olatile memory technolog y and
is compati ble with the industry-standar d 80C51 and 80C52 instr u ction set and pinout.
The on-chip Flash allows the program memor y to be user programmed by a conven-
tional nonvolatile memor y programmer. A total of 512 bytes of internal RAM are
avai lable in the AT89 C51RC. The 256-byte expanded in ter nal RAM is accesse d via
MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The other
256-byte RAM segment i s accessed the same way as the Atmel AT89-s eries and
other 8052-compatible products. By combining a versatile 8-bit CPU with Flash on a
monolith ic chi p, the Atmel AT 89C5 1RC is a powerful mi cro co mpu ter wh ic h pr ovides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I /O li nes, three 16-bit ti mer/coun ters, a six -vector two-leve l interr up t
archite ct ur e, a full d upl ex seri al po rt, on- chip os ci ll ator, and cl ock circu itry. In addit ion ,
the AT89C51RC is designed with static logic for operation down to zero frequency and
suppo r ts two software se lecta ble power saving modes. The Idle Mo de stop s the CP U
while allowing the RAM, timer/counters, serial por t, and interrupt system to continue
functioning. The P o w er-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next external interrupt or hardware reset.
8-bit
Microcontroller
with 32K Bytes
Flash
AT89C51RC
Rev. 1920B–MICRO–11/02
2AT89C51RC 1920B–MICRO–11/02
Pin Configurations TQFP
PDIP
PLCC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
(T2) P1.0
(T2EX) P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)
NC
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
3
AT89C51RC
1920B–MICRO–11/02
Block Diag ram
PORT 2 DRIVERS
PORT 2
LATCH
P2.0 - P2.7
FLASH
PORT 0
LATCH
RAM
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DUAL
DPTR
RAM ADDR.
REGISTER
INSTRUCTION
REGISTER
B
REGISTER
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
STACK
POINTER
ACC
TMP2 TMP1
ALU
PSW
TIMING
AND
CONTROL
PORT 3
LATCH
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1
LATCH
PORT 1 DRIVERS
P1.0 - P1.7
OSC
GND
VCC
PSEN
ALE/PROG
EA / VPP
RST
PORT 0 DRIVERS
P0.0 - P0.7
WATCH
DOG
4AT89C51RC 1920B–MICRO–11/02
Pin Description
VCC Supply voltage.
GND Ground.
Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code
bytes during program verification. External pull-ups are required during program
verification.
Port 1 Port 1 is an 8-bit bidir ectional I/O port with internal pull-ups . The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high
by the in ter na l pu ll -ups an d c an b e us ed as in put s. A s in puts , P ort 1 pins that ar e exte r-
nally being pulled low will source current (IIL) because of the internal pull-ups.
In addition , P1.0 and P 1.1 can be configur ed to be the timer/cou nter 2 ext ernal count
input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and
verification.
Port 2 Port 2 is an 8-bit bidir ectional I/O port with internal pull-ups . The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high
by the in ter na l pu ll -ups an d c an b e us ed as in put s. A s in puts , P ort 2 pins that ar e exte r-
nally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high -ord er addr ess by te dur ing fe tches from exte rnal progra m memo ry
and du ring accesses to external data memory th at use 16-bit addresses ( MOVX @
DPTR). In this app li ca tio n, Po r t 2 uses s trong internal pull - ups when emi ttin g 1s . Dur ing
access es to external data me mor y that use 8- bit a ddr es se s (M OVX @ RI) , P ort 2 emits
the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash
progra mming and verificat ion .
Port 3 Port 3 is an 8-bit bidir ectional I/O port with internal pull-ups . The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
by the in ter na l pu ll -ups an d c an b e us ed as in put s. A s in puts , P ort 3 pins that ar e exte r-
nally being pulled low will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89C51RC, as
shown in the following table.
Port Pin Alternate Functions
P1.0 T2 (exter nal count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
5
AT89C51RC
1920B–MICRO–11/02
RST Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives High for 98 oscillator periods after the Watchdog times
out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In
the default state of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG Addres s Latch Enab le is a n ou tput pul se for latchi ng the low by te of th e addr ess dur ing
accesses to external memo ry. This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and
may be used for external timing or clock ing purposes. Note, however, that one ALE
pulse is skipped during each access to external data memory.
If desir ed, A LE ope ratio n can be dis ab led by set ting bit 0 of S FR lo cation 8E H. Wi th th e
bit set , ALE is ac tive only du ring a MOV X or MOVC inst ruction . Otherwis e, the pin is
weakly pulled high . Setting the ALE-disable bit has no effect if the microcontroller is in
external execut ion mode.
PSEN Program Store Enable is the read strobe to external program memory.
When the AT89C51RC is executing code from external program memory, PSEN is acti-
vated twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash
programming.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (exte rnal data memory write stro be)
P3.7 RD (external data memory read strobe)
6AT89C51RC 1920B–MICRO–11/02
Table 1. AT89C51RC SFR Map and Reset Values
0F8H 0FFH
0F0H B
00000000 0F7H
0E8H 0EFH
0E0H ACC
00000000 0E7H
0D8H 0DFH
0D0H PSW
00000000 0D7H
0C8H T2CON
00000000 T2MOD
XXXXXX00 RCAP2L
00000000 RCAP2H
00000000 TL2
00000000 TH2
00000000 0CFH
0C0H 0C7H
0B8H IP
XX000000 0BFH
0B0H P3
11111111 0B7H
0A8H IE
0X000000 0AFH
0A0H P2
11111111 AUXR1
XXXXXXX0 WDTRST
XXXXXXXX 0A7H
98H SCON
00000000 SBUF
XXXXXXXX 9FH
90H P1
11111111 97H
88H TCON
00000000 TMOD
00000000 TL0
00000000 TL1
00000000 TH0
00000000 TH1
00000000 AUXR
XXX00X00 8FH
80H P0
11111111 SP
00000111 DP0L
00000000 DP0H
00000000 DP1L
00000000 DP1H
00000000 PCON
0XXX0000 87H
7
AT89C51RC
1920B–MICRO–11/02
Special Function
Registers A ma p o f th e o n- ch ip memory area c all ed the S pec ia l Fu nctio n Registe r (SF R) spa ce is
shown in Table 1.
Note tha t not all of the ad dresse s a re occu pied, an d unoc cupie d ad dresse s may not be
implem ented on the chip. Read accesses to these addre sses will in general ret urn ran-
dom data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in
future products to invoke new features. In that case, the reset or inactive values of the
new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in
Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H,
RCAP2L) ar e the Captur e/Reload reg isters for Time r 2 in 16-bit ca pture mod e or 16-bit
auto-reload mode.
Interrupt Registers: The i ndi vidu al int err upt enabl e bi ts are in the IE regi ste r. Two p ri-
orities can be set for each of the six interrupt sources in the IP register.
Table 2. T2CON – Timer/Counter 2 Control Register
T2CO N Address = 0C8H Reset Val ue = 0000 000 0B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
76543210
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK
= 1 or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Ti mer 2 interrup t is ena b led, EXF 2 = 1 will caus e the CPU t o v ect or to the Tim er 2 interrupt ro utine . EXF2 mu st be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the se rial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Transm it cl oc k en ab le . When set , caus es the serial po rt to use T imer 2 o v erfl ow p ulses f or it s tr ansm it cl oc k in serial po rt
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a c a pture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or c ounter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
CP/RL2 Capture/Reload select. CP/RL2 = 1 cause s captures to occur o n negati v e tr ansiti ons at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.
When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
8AT89C51RC 1920B–MICRO–11/02
Dual Data Poin ter Registers: To facilitate access ing both in ternal and extern al data
memory , two banks of 16-bi t Data Pointer Register s are pr ovided: DP 0 at SF R address
locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and
DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate
value before accessing the respective Data Pointer Register.
Power Off F lag: The Power O ff Flag (POF) is located at bit 4 (PCON.4) in the PCON
SFR. POF is set to “1” during power up. It can be set and rest under softwa re contro l
and is not affected by reset.
Table 3a. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00X00B
Not Bit Addressable
– – – WDIDLE DISRTO – EXTRAM DISALE
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DISALE Disable/Enable ALE
DISALE Operating Mo de
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only du ring a MOVX or M OVC instr uction
EXTRAM Internal/External RAM access using MOVX @ Ri/@DPTR
EXTRAM Operating Mode
0 Internal ERAM (00H-FFH) access using MOVX @ Ri/@DPTR
1 External data memory access
DISRTO Disable/Enable Reset out
DISRTO Operat ing Mode
0 Reset p in is driven High aft er WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE Operat ing Mode
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
9
AT89C51RC
1920B–MICRO–11/02
Memory Organization MCS-51 devices hav e a separate address sp ace for Prog ram and Data Memory. Up to
64K bytes each of external Program and Data Memory can be addressed.
Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89C51RC, i f EA is c onnected to VCC, progr am fetches to addresse s 0000H
through 7FFFH are directed to internal memory and fetches to addresses 8000H
through FFFFH are to external memory.
Data Memory The AT89C51RC has internal data memory that is mapped into four separate segments:
the lower 128 bytes of RAM, up per 128 by tes of RAM, 128 bytes sp ecial func tion regi s-
ter (SFR) and 256 bytes expanded RAM (ERAM).
The four segments are:
1. The Lower 128 bytes of RAM (addr esses 0 0H to 7FH) are di rectly and ind irectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly
addressable only.
4. The 256-byte e xpanded RAM (ERAM, 00H-FFH) is indirectly accessed by MOVX
instructions, and with the EXTRAM bit cleared.
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes ca n be access ed by indirect ad dressing only. T he Upper 128 bytes occupy
the sa me addres s spa ce as the SF R. Th is means they ha ve the s ame add ress , but are
physically separate from the SFR space.
When an instr uction acce sses an interna l location above address 7FH, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addres sing mode used i n the i nstruc tion. In struc tions th at use direc t addres sing access
SFR space. For example:
MOV 0A0H, # data
Table 3b. AUXR1: Aux i li ary R egister 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
–––– – – –DPS
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
10 AT89C51RC 1920B–MICRO–11/02
accesses the SFR at location 0S0H (which is P2). Instructions that use indirect address-
ing access the Upper 128 bytes of data RAM. For example:
MOV@R0, # data
where R 0 contains 0A0H, acc esses the data byte at a ddress 0A 0H, rather th an P2
(whose address is 0A0H).
Note that stack opera tions are exam ples of indir ect ad dressi ng, so the upp er 128 bytes
of data RAM are available as stack space.
The 25 6 bytes of ERAM can be accessed by indirec t addressing, with EXTR AM bit
cleared and M OVX inst ructi ons. T his par t of memo ry is phy sically loc ated o n-chip , log i-
cally occupying the first 256 bytes of external data memory.
Figure 1. Internal and External Data Memory Address
(with EXTRAM = 0)
With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in
combi natio n wi th an y o f the re gister s R 0, R1 of t he selec ted bank or D PTR . An acce ss
to ERAM wi ll not affect ports P0, P2, P 3.6 (WR), and P 3.7 (RD). For example, with
EXTRAM = 0,
MOVX@R0, # data
where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external
memory. An access to external data memory locations higher than FFH (i.e. 0100H to
FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the
standard 80C51, i.e., with P0 and P2 as data/address bus, and P3.6 and P3.7 as write
and read timing signals. Refer to Figure 1.
With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be similar to the standard
80C51. MOVX@Ri will provide an 8-bit address multiplexed with data on Port 0 and any
output port pins can be used to output higher-order address bits. This is to provide the
externa l pa gin g ca pab il ity . MOVX @ D PTR wi ll gene ra te a 16 -bit ad dr es s. P ort 2 outputs
the high-order 8 address bits (the contents of DP0H), while Port 0 multiplexes the low-
order 8 address bits (the contents of DP0L) with data. MOVX@Ri and MOV X@DPTR
will generate either read or write signals on P3.6 (WR) and P3.7 (RD).
The s tack point er (SP) ma y be loc ated any where in the 256 byt es RAM (l ower and
upper RAM) internal data memory. The stack may not be located in the ERAM.
ERAM
256 BYTES
UPPER
128 BYTES
INTERNAL
RAM
LOWER
128 BYTES
INTERNAL
RAM
FF
00
FF
80
00
SPECIAL
FUNCTION
REGISTER
FF
80
EXTERNAL
DATA
MEMORY
FFFF
0100
0000
11
AT89C51RC
1920B–MICRO–11/02
Hardware Watchdog
Timer
(One-time Enabled
with Reset-out)
The WDT is intended as a recovery method in s ituations where the CPU may be sub-
jected to software upsets. T he WDT consists of a 1 3-bit counter and the WatchDog
Timer Rese t (WDTRS T) SFR. The WDT is defaul ted to disable from exiting r eset. To
enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST regis-
ter (SFR location 0A6H). When the WDT is enabled, it will increment every machine
cycle while the oscillator is running. The WDT timeout period is dependent on the exter-
nal cloc k frequency. T here is no way to disa ble the WDT except through reset (e ither
hardware reset or WDT overflow reset). When WDT overflows, it will drive an output
RESET HIGH pulse at the RST pin.
Using the WDT To enabl e the WDT, a user must wr ite 01EH and 0E1H in seque nce to the WDTRST
register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by
writing 01EH and 0E 1H to WDT RST to avo id a WDT ove rflow . The 13-bi t counte r over-
flows when it reaches 8191 (1FFFH), and this will reset the devic e. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running. This means
the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the
user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The
WDT counter cannot be read or written. When WDT overflows, it will generate an output
RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where
TOSC =1/FO SC. To ma ke the be st use of the WDT , it sh ould be servic ed in th ose sec-
tions of code that will periodically be executed within the time required to prevent a WDT
reset.
WDT During Power-
down and Idle In Power-down m ode the osc illator stops, whi ch means th e WDT also s tops. While i n
Power-down mode, the user does not need to service the WDT. There are two methods
of exitin g Pow er -down mode: by a h ardwar e r eset or v ia a lev el-ac ti va ted e xte rnal inte r-
rupt which is enabled prior to entering Power-down mode. When Power-down is exited
with hard ware reset , servicing the WDT shou ld occur as it normally does whene ver the
AT89C51 RC i s rese t. E x iti ng Pow er -down with an i nter rupt is s ig nif ican tly di ffe re nt. Th e
interrupt is held low long enough for the oscillator to stabiliz e. When the interrupt is
brough t high, the inter rupt is service d. To prevent the WDT from r esetting the de vice
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is su ggested tha t the WD T be rese t during th e inter rupt ser vice for the interrup t used
to exit Power-down mode.
To ensu re that t he WDT doe s not ov erflo w within a few stat es of ex iting Powe r-down, i t
is best to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determi ne
whether the WDT continues to count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the
AT89C51 RC whi le in IDLE mode , the us er sh oul d al ways s et up a timer tha t wil l peri od-
ically exit IDLE, service the WDT, and reenter IDLE mode.
With WDIDLE bit enabl ed, the WDT will stop to count in IDLE mode and resumes the
count upon exit from IDLE.
UART The UART in the AT89C51RC operates the same way as the UART in the AT 89C51
and AT89C52. For further information, see the December 1997 Microcontroller Data
Book, page 2-48, section titled, “Serial Interface”.
12 AT89C51RC 1920B–MICRO–11/02
Timer 0 and 1 Timer 0 and Tim er 1 in th e AT89C51R C operat e the same way as Tim er 0 and Timer 1
in the AT89C51 and AT89C52.
Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter.
The ty pe of ope ration is selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Time r 2 has three oper ating mode s: capture , auto-re load (up or d own counti ng), and
baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 con sist s of two 8-b it regi ste rs, T H2 an d TL 2. In the Timer fun cti on , the TL2 r eg-
ister is incremented every machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Coun ter func tion, the re gister is in creme nted in respo nse to a 1- to-0 tran sition at
its correspondi ng external input pin, T2. In this function, the external input is sampl ed
during S5P2 of every machine cycle. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. The new count value appears in the reg-
ister during S3P1 of the cycle following the one in which t he transition was detected.
Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 tran-
sition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given
level is sampled at least once before it changes, the level should be held for at least one
full machine cycle.
Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 is a 16-b it timer or cou nter whi ch upon overflow s ets bit TF2 in T 2CON. T his bi t
can then be us ed to generate an inter rupt. If EXEN2 = 1, Timer 2 perform s the same
operation, but a 1-to-0 transition at external input T2EX also causes the current value in
TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can
generate an interrupt. The capture mode is illustrated in Figure 2.
Auto-Reload (Up or
Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-
reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MO D (see Table 4 ). Upon reset, the DCE N bit is s et to 0 s o that timer 2 will
default to count up. When DCEN is set, Timer 2 can count up or down, depending on the
value of the T2EX pin.
Table 3. Timer 2 Operating Modes
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)
13
AT89C51RC
1920B–MICRO–11/02
Figure 2. Timer in Capture Mode
Figure 3 shows Timer 2 automatically counting up when DCEN=0. In this mode, two
options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon ov erflow. The overflow also caus es the timer
registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in
Timer in Cap ture Mo deRCA P2H an d RCAP 2L are p rese t by soft ware. If EXEN 2 = 1, a
16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external
input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can gen-
erate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this
mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also
causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,
TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2
equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The E XF2 b it to ggles w henev er Timer 2 ove rflows or underfl ows and can be used as a
17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
OSC
EXF2
T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1 CONTROL
CAPTURE
OVERFLOW
CONTROL
TRANSITION
DETECTOR TIMER 2
INTERRUPT
÷12
RCAP2LRCAP2H
TH2 TL2 TF2
14 AT89C51RC 1920B–MICRO–11/02
Figure 3. Timer 2 Auto Reload Mode (DCEN = 0)
OSC
EXF2
TF2
T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1
CONTROL
RELOAD
CONTROL
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
12
RCAP2LRCAP2H
TH2 TL2
OVERFLOW
Table 4. T2MOD—T imer 2 Mode Control Regis ter
T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
––––––T2OEDCEN
Bit76543210
Symbol Function
– Not implemented, reserved for future
T2O E Timer 2 Output E nable bit
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter
15
AT89C51RC
1920B–MICRO–11/02
Figure 4. Timer 2 Auto Reload Mode (DCEN = 1)
Figure 5. Timer 2 in Baud Rate Generator Mode
OSC
EXF2
TF2
T2EX PIN
COUNT
DIRECTION
1=UP
0=DO
T2 PIN
TR2
CONTROL
OVERFLOW
TOGGLE
TIMER 2
INTERRUPT
12
RCAP2LRCAP2H
0FFH0FFH
TH2 TL2
C/T2 = 0
C/T2 = 1
(DOWN COUNTING RELOAD VALUE)
(UP COUNTING RELOAD VALUE)
OSC
SMOD1
RCLK
TCLK
Rx
CLOCK
Tx
CLOCK
T2EX PIN
T2 PIN
TR2
CONTROL
"1"
"1"
"1"
"0"
"0"
"0"
TIMER 1 OVERFLOW
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
TIMER 2
INTERRUPT
2
2
16
16
RCAP2LRCAP2H
TH2 TL2
C/T2 = 0
C/T2 = 1
EXF2
CONTROL
TRANSITION
DETECTOR
EXEN2
÷
÷
÷
÷
16 AT89C51RC 1920B–MICRO–11/02
Baud Rate Generator Timer 2 is sel ected as the ba ud r ate generat or by setti ng TCLK and /or RCLK in T2CO N
(Table 2) . Note tha t the bau d ra tes for tran sm it an d re ce iv e ca n be di fferen t if Ti me r 2 is
used for the r eceiver or tr ansmitter and Timer 1 is used for the oth er function. Setti ng
RCLK and/or TCLK put s Tim er 2 into i ts baud rate gener ator mode , as sh own in Fig ure
5.
The baud rate genera tor mode is similar to the auto- reload mode, in that a rol lover in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to
the following equation.
The Time r ca n be co nfigured for e ither tim er or c ounter operati on. In m ost ap plic ations,
it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer
2 when it is used as a ba ud rate gen erator. Norm ally, as a ti mer, it inc rements ev ery
machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator frequency). The baud rate formula is
given below.
where (RCAP2H, RCAP2L) is the content of RCA P2H and RCAP2L taken as a 16-bit
unsigned integer.
Timer 2 as a bau d ra te gen erato r is shown in Figure 5. Th is f igur e is v alid only i f RCLK
or TCLK = 1 in T2CO N. No te tha t a rollo ve r in TH 2 doe s not set TF2 an d wil l not gene r-
ate an i nter rupt. Note too, tha t if E XE N2 is s et , a 1- to-0 tr ans it ion i n T2 EX wi ll set EXF2
but will not caus e a r eload from (RC AP2H, RCA P2 L) to (TH2 , TL2) . Thus when Ti mer 2
is in use as a baud rate generator, T2EX can be used as an extra external interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode,
TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is
increme nted ever y state t ime, and th e results of a read or write m ay not be accurat e.
The RCAP2 registers may be read but should not be written to, because a write might
overlap a reload and ca use write and/or reload errors. The timer should be turn ed off
(clear TR2) before accessing the Timer 2 or RCAP2 registers.
Mdes 1 and 3 Baud Rates Timer 2 Overflow Rate
16
------------------------------------------------------------=
Modes 1 and 3
Baud Rate
--------------------------------------- Oscillator Frequency
32 x [65536-RCAP2H,RCAP2L)]
--------------------------------------------------------------------------------------=
17
AT89C51RC
1920B–MICRO–11/02
Figure 6. Timer 2 in Clock-Out Mode
OSC
EXF2
P1.0
(T2)
P1.1
(T2EX)
TR2
EXEN2
C/T2 BIT
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
T2OE (T2MOD.1)
2TL2
(8-BITS)
RCAP2L RCAP2H
TH2
(8-BITS)
2
18 AT89C51RC 1920B–MICRO–11/02
Programmable Clock
Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 6.
This pin, besides being a regular I/O pin, has two alternate functions. It can be p ro-
grammed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle
clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock gener ator, bit C/T2 (T2CON.1) must be
cleared and bit T2OE (T2 MOD.1 ) mus t be set . Bi t TR2 (T2C ON.2) sta rts a nd s tops the
timer.
The clock-out frequency depends on the oscillator frequency and the reload value of
Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
In the c lock-o ut mod e, Timer 2 rol l-over s will not ge nerat e an i nterrup t. This behav ior is
similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as
a baud- rate generator and a clock gen erator s imulta neously. Note, h owever, that th e
baud-ra te and clock- out frequencie s cannot be determin ed independen tly from one
another since they both use RCAP2H and RCAP2L.
Interrupts The AT89C51RC has a total of six interrupt vectors: two external interrupts (INT0 and
INT1), th ree timer in terrupts (T imers 0, 1, and 2), and the ser ial port inte rrupt. Thes e
interrupts are all shown in Figure 7.
Each of these interrupt sources can be individually enabled or disabled by setting or
clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA,
which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimplemented. User software should
not write 1s to these bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the service routine is vec-
tored to. In f ac t, th e ser vic e rout ine may h ave to de ter mi ne w heth er it was TF2 o r EX F2
that generated the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the
timers overflow. The values are then polled by the circuitry in the next cycle. However,
the Ti mer 2 flag , TF2, is set at S2 P2 and is p olled in the same cycle in which th e timer
overflows.
Clock-Out Frequency Oscillator Frequency
4 x [65536-(RCAP2H,RCAP2L)]
-------------------------------------------------------------------------------------=
19
AT89C51RC
1920B–MICRO–11/02
Figure 7. Interrupt Sources
Table 5. Interrupt Enable (IE) Register
(MSB) (LSB)
EA –ET2 ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol Position Function
EA IE.7 Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or
clearing its enable bit.
– IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.
User softw a re shou ld ne ver write 1s to rese rved bits , be caus e the y may be use d in futu re AT89
products.
IE1
IE0
1
1
0
0
TF1
TF0
INT1
INT0
TI
RI
TF2
EXF2
20 AT89C51RC 1920B–MICRO–11/02
Oscillator
Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that
can be confi gu red for use as an on-c hip os ci ll ato r, as shown in F igu re 8. Eit her a quartz
crysta l or ceram ic resonat or may b e used. To drive the device from an exte rnal cl ock
source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 9.
There are no re quire men ts on the duty cy c le of the exter na l clock si gna l, si nce the inp ut
to the i nternal clocking circuit ry is throu gh a divi de-by- two flip-f lop, but m inimum and
maximum voltage high and low time specifications must be observed.
Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on- chip RAM and all the specia l
functio ns re gisters remain unchang ed dur ing thi s mode . The id le mod e can be term i-
nated by any enabled interrupt or by a hardware reset.
Note that when idle mode is te rminated by a ha rdware reset, the device normally
resumes program execution from where it left off, up to two machine cycles before the
interna l res et al gor it hm take s c ontr ol. O n- chi p h ar dware inhib its a cces s to inte rnal RA M
in this event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when idle mode is terminated by a reset, the instruction
following the one that invokes idle mode should not write to a port pin or to external
memory.
Power-do wn Mode In the Po wer-down mode, th e oscillator is stopped, and the instructi on that invok es
Power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the Power-down mode is terminated. Exit from Power-
down can be init iated either by a hardware reset or by an enabled external interrupt.
Reset redefines the SFRs but does not change the on-chip RAM. The reset should not
be activated before VCC is restored to its normal operating level and must be held active
long enough to allow the oscillator to restart and stabilize.
Figure 8. Oscill ato r Conn ec tio ns
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
C2 XTAL2
GND
XTAL1
C1
21
AT89C51RC
1920B–MICRO–11/02
Figure 9. External Clock Drive Configuration
Program Memory
Lock Bits The AT89C51RC has three lock bits that can be left unprogrammed (U) or can be pro-
grammed (P) to obtain the additional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched dur-
ing reset. If the devic e is powered u p without a rese t, the latch initi alizes to a random
value and holds that value until reset is activated. The latched value of EA must agree
with the current logic level at that pin in order for the device to function properly.
XTAL2
XTAL1
GND
NC
EXTERNAL
OSCILLATOR
SIGNAL
Table 6. Status of External Pins During Idle and Power-down Modes
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data
Table 7. Lock Bit Protection Modes
Program Lock Bits
LB1 LB2 LB3 Protection Ty pe
1 U U U No program lock featu res
2 P U U MOVC instructions executed from exte rnal program
mem ory are disabled from fetchi ng code bytes from
internal memo ry, EA is sampled and latched on reset,
and further programming of the Flash memory is
disabled
3 P P U Same as mode 2, but verify is also disabled
4 P P P Same as mode 3, but external execution is also
disabled
22 AT89C51RC 1920B–MICRO–11/02
Programming the
Flash The AT89C51RC is shipped with the on-chip Flash memory array ready to be pro-
grammed. The progr amming inter face needs a high-volta ge (12- volt) prog ram enable
signal and is compatible with conventional third-party Flash or EPROM programmers.
The AT89C51RC code memory array is programmed byte-by-byte.
Programming Algori thm: Before programming the AT89C51RC, the address, data,
and contr ol signals should be set up ac cording to the Flas h programmin g mode tabl e
and Figures 10 and 11. To program the AT89C51RC, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Puls e A LE/ PROG once to pr ogram a byte in th e Fla sh array or the lock bits. The
byte-write cycle is self-timed and typically takes no more than 50 µs. Repeat
steps 1 through 5, cha ngi ng th e ad dres s an d da ta for the entire array or unti l th e
end of the object file is reached.
Chip Erase Sequence: Before the AT89C51RC can be reprogrammed, a Chip Erase
operati on need s to be perfo rmed. To erase t he con tents o f the AT89C51 RC, foll ow this
sequence:
1. Raise VCC to 6.5V.
2. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
3. Power VCC down and up to 6.5V.
4. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
5. Power VCC down and up.
Data Polling: The AT89C51RC features Data Polling to indicate the end of a write
cycle. Du ring a write cycle, an attempted re ad of the las t byte written wil l result in t he
complem ent of the wr itte n d ata on P0 .7. Once th e wri te c y cl e has been co mpl ete d, t ru e
data is valid on all outputs, and the next cycle may begin. Data Polling may begin any
time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the
RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to
indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY.
Program Ve rify: If lock bits LB1 and LB2 have not been programmed, the programmed
code data can be read back via the address and data lines for verification. The status of
the individual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as
a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7
must be pulled to a logic low. The values returned are as follows:
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H
(200H) = 07H indicates 89C51RC
23
AT89C51RC
1920B–MICRO–11/02
Programming
Interface Every code byte in the Flash array can be programmed by using the appropriate combi-
nation of control signals. The write operation cycle is self-timed and once initiated, will
automatically time itself to completion.
Most maj or worldwi de progra mming ve ndors offer support fo r the Atmel mi crocontr oller
series. Please contact your local programming vendor for the appropriate software
revision.
Notes: 1. Write Code Data requires a 200 ns PROG pulse.
2. Write Lock Bits requires a 100 µs PROG pulse.
3. Chip Erase requires a 200 ns - 500 ns PROG pulse.
4. RDY/BSY signal is output on P3.0 during programming.
Table 8. Flash Prog rammi ng Mod es
Mode VCC RST PSEN ALE/
PROG EA/
VPP P2.6 P2.7 P3.3 P3.6 P3.7 P0.7-0
Data
P3.4 P2.5-0 P1.7-0
Address
Write Code Data 5V H L (1) 12 VLHHHHD
IN A14 A13-8 A7-0
Read Code Data 5V H L H H/12
VLLLHHD
OUT A14 A13-8 A7-0
Write Lock Bit 1 6.5V H L (2) 12 VHHHHH X X X X
Write Lock Bit 2 6.5V H L (2) 12 V H H H L L X X X X
Write Lock Bit 3 6.5V H L (2) 12 V H L H H L X X X X
Read Lock Bits
1, 2, 3 5V H L H H H H L H L P0.2,
P0.3,
P0.4 XX X
Chip Erase 6.5V H L (3) 12VHLHLL X X X X
Read Atmel ID 5V H L H H LLLLL1EHXXX 0000 00H
Read Device ID 5V H L H H LLLLL51HXXX 0001 00H
Read Device ID 5V H L H H LLLLL07HXXX 0010 00H
24 AT89C51RC 1920B–MICRO–11/02
Figure 10. Pr og ra mming the Fl ash Memo ry
Figure 11. Verifying the Flash Memory
Note: *Programming address li ne A14 (P3.4) is not the same as the external memor y address
line A14 (P2.6).
P1.0 - P1.7
P2.6
P3.6
P2.0 - P2.5
A0 - A7
ADDR.
0000H/7FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3 - 33 MHz
A14* P0
4.5V to 5.5V
P2.7
PGM
DATA
PROG
V/V
IH PP
VIH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL1
GND
VCC
AT89C51RC
P3.4
P3.3
P3.0 RDY/
BSY
A8 - A13
P1.0 - P1.7
P2.6
P3.6
P2.0 - P2.5
A0 - A7
ADDR.
0000H/7FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3 - 33 MHz
P0
P2.7
PGM DATA
(USE 10K
PULL-UPS)
VIH
VIH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL1
GND
VCC
A14*
AT89C51RC
P3.4
P3.3
A8 - A13
4.5V to 5.5V
25
AT89C51RC
1920B–MICRO–11/02
Flash Programming and Verification Characteristics
TA = 20°C to 30°C, VCC = 4.5V to 5.5V
Symbol Parameter Min Max Units
VPP Prog r am ming Supply Voltage 11.5 12.5 V
IPP Prog r am mi ng Supp ly Curre nt 10 mA
ICC VCC Supply Current 30 mA
1/tCLCL Os ci llator Fre que nc y 3 33 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold after PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold after PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold after PROG 10 µs
tGLGH PROG Width 0.2 1 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float after ENABLE 048t
CLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 80 µs
26 AT89C51RC 1920B–MICRO–11/02
Flash Programming and Verification Waveforms
Lock Bit Programming
tGLGH tGHSL
tAVGL
tSHGL
tDVGL tGHAX
tAVQV
tGHDX
tEHSH tELQV
tWC
BUSY READY
tGHBL
tEHQZ
P1.0 - P1.7
P2.0 - P2.5
P3.4
ALE/PROG
PORT 0
LOGIC 1
LOGIC 0
EA/V
PP
V
PP
P2.7
(ENABLE)
P3.0
(RDY/BSY)
PROGRAMMING
ADDRESS VERIFICATION
ADDRESS
DATA IN DATA OUT
Test Conditions
Setup
Lockbit_1, 2 or 3
Data Setup
ALE/PROG
V
CC = 6.5V VCC = 4.5V to 5.5V
Wait 10 ms to reload
new lock bit status
100 µs
27
AT89C51RC
1920B–MICRO–11/02
Parallel Chip Erase Mode
10 ms
Test Conditions
Setup Test Conditions Setup
ALE/PROG
P3<0> Erase DC
Erase Erase
VCC = 4.5V to 5.5V
Wait 10 ms before
reprogramming
VCC = 6.5V
DC
Erase
200 ns
200 ns
28 AT89C51RC 1920B–MICRO–11/02
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA Por ts 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
Absolute Maxim u m Ratings*
Operating Temperature.................................. -55°C to +125°C Notice*: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause perm anent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximu m Op er ati ng Voltage ............ ..... ...... ...... ............... 6.6V
DC Output Current...................... ...... ..... ..................... 15.0 mA
DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol Parameter Condition Min Max Units
VIL Input Low-voltage (Except EA)-0.50.2 V
CC-0.1 V
VIL1 Input Low-voltage (EA)-0.50.2 V
CC-0.3 V
VIH Input High-voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V
VIH1 Input High-voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V
VOL Output Low-voltage(1) (Ports
1,2,3) IOL = 1.6 mA 0.45 V
VOL1 Outp ut Low-voltage(1)
(Port 0, ALE, PSEN)IOL = 3.2 mA 0.45 V
VOH Output High-voltage
(Ports 1,2,3, ALE, PSEN)
IOH = -60 µA, VCC = 5V ± 10% 2.4 V
IOH = -25 µA 0.75 VCC V
IOH = -10 µA 0.9 VCC V
VOH1 Output High-voltage
(Port 0 in External Bus Mode)
IOH = -800 µA, VCC = 5V ± 10% 2.4 V
IOH = -300 µA 0.75 VCC V
IOH = -80 µA 0.9 VCC V
IIL Logical 0 Input Current (Ports
1,2,3) VIN = 0.45V -50 µA
ITL Logical 1 to 0 Transition Cu rre nt
(Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA
ILI Input Leakage Current (Port 0,
EA)0.45 < VIN < VCC ±10 µA
RRST Reset Pull-down Resistor 10 30 kW
CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
ICC Power Supply Current Active Mode, 12 MHz 25 mA
Idle Mode, 12 MHz 6.5 mA
Power-d own Mode(1) VCC = 5.5V 100 µA
29
AT89C51RC
1920B–MICRO–11/02
AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100
pF; load capacitance for all other outputs = 80 pF.
External Program and Data Memory Characteristics
Symbol Parameter
12 MHz Oscillator Variable Oscillator
UnitsMin Max Min Max
1/tCLCL Oscillator Frequency 0 33 MHz
tLHLL ALE Pulse Width 127 2tCLCL-40 ns
tAVLL Addres s Valid to ALE Low 43 tCLCL-25 ns
tLLAX Address Hold after ALE Low 48 tCLCL-25 ns
tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns
tLLPL ALE Low to PSEN Low 43 tCLCL-25 ns
tPLPH PSEN Pulse Width 205 3tCLCL-45 ns
tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-60 ns
tPXIX Input Instruction Hold after PSEN 00ns
tPXIZ Input Instruction Float after PSEN 59 tCLCL-25 ns
tPXAV PSEN to Address Valid 75 tCLCL-8 ns
tAVIV Address t o Valid Instructi on In 312 5tCLCL-80 ns
tPLAZ PSEN Low to Address Float 10 10 ns
tRLRH RD Pulse Width 400 6tCLCL-100 ns
tWLWH WR Pulse Width 400 6tCLCL-100 ns
tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns
tRHDX Data Hold after RD 00ns
tRHDZ Data Float after RD 97 2tCLCL-28 ns
tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns
tAVDV Address to Valid Data In 585 9tCLCL-165 ns
tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns
tAVWL Address to RD or WR Low 203 4tCLCL-75 ns
tQVWX Data Valid to WR Transition 23 tCLCL-30 ns
tQVWH Data Valid to WR High 433 7tCLCL-130 ns
tWHQX Data Hold after WR 33 tCLCL-25 ns
tRLAZ RD Low to Address Float 0 0 ns
tWHLH RD or WR High to ALE High 43 123 tCLCL-25 tCLCL+25 ns
30 AT89C51RC 1920B–MICRO–11/02
External Program Memory Read Cycle
External Data Memory Read Cyc le
tLHLL
tLLIV
tPLIV
tLLAX tPXIZ
tPLPH
tPLAZ tPXAV
tAVLL tLLPL
tAVIV
tPXIX
ALE
PSEN
PORT 0
PORT 2
A8 - A15
A0 - A7 A0 - A7
A8 - A15
INSTR IN
tLHLL
tLLDV
tLLWL
tLLAX
tWHLH
tAVLL
tRLRH
tAVDV
tAVWL
tRLAZ tRHDX
tRLDV tRHDZ
A0 - A7 FROM RI OR DPL
ALE
PSEN
RD
PORT 0
PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH
A0 - A7 FROM PCL
A8 - A15 FROM PCH
DATA IN INSTR IN
31
AT89C51RC
1920B–MICRO–11/02
External Data Memory Write Cycle
External Clock Drive Waveforms
tLHLL
tLLWL
tLLAX
tWHLH
tAVLL
tWLWH
tAVWL
tQVWX tQVWH tWHQX
A0 - A7 FROM RI OR DPL
ALE
PSEN
WR
PORT 0
PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH
A0 - A7 FROM PCL
A8 - A15 FROM PCH
DATA OUT INSTR IN
tCHCX tCHCX
tCLCX tCLCL
tCHCL
tCLCH
V - 0.5V
CC
0.45V 0.2 V - 0.1V
CC
0.7 VCC
External Clock Drive
Symbol Parameter Min Max Units
1/tCLCL Oscillator Frequency 0 33 MHz
tCLCL Clock Period 30 ns
tCHCX High Time 12 ns
tCLCX Low Time 12 ns
tCLCH Rise Time 5 ns
tCHCL Fall Time 5 ns
32 AT89C51RC 1920B–MICRO–11/02
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1)
Note: 1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.
Float Waveforms(1)
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level occurs.
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
Symbol Parameter
12 MHz Osc Variable Oscillator
UnitsMin Max Min Max
tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs
tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL - 133 ns
tXHQX Output Data Hold after Clock Rising Edge 50 2tCLCL - 80 ns
tXHDX Input Data Hold after Clock Rising Edge 0 0 ns
tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL - 133 ns
t
XHDV
t
QVXH
t
XLXL
t
XHDX
t
XHQX
ALE
INPUT DATA
CLEAR RI
OUTPUT DATA
WRITE TO SBUF
INSTRUCTION
CLOCK
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
SET TI
SET RI
8
VALID VALIDVALID VALIDVALID VALIDVALID VALID
0.45V
TEST POINTS
V - 0.5V
CC 0.2 V + 0.9V
CC
0.2 V - 0.1V
CC
VLOAD+ 0.1V
Timing Reference
Points
V
LOAD- 0.1V
LOAD VVOL+ 0.1V
VOL - 0.1V
33
AT89C51RC
1920B–MICRO–11/02
Ordering In format ion
Speed
(MHz) Power
Supply Ordering Code Package Operation Range
24 4.0V to 5.5V AT89C51RC- 2 4AC
AT89C51RC-24JC
AT89C51RC-24PC
44A
44J
40P6
Commercial
(0°C to 70°C)
AT89C51RC-24AI
AT89C51RC-24JI
AT89C51RC-24PI
44A
44J
40P6
Industrial
(-40°C to 85°C)
33 4.5V to 5.5V AT89C51RC- 3 3AC
AT89C51RC-33JC
AT89C51RC-33PC
44A
44J
40P6
Commercial
(0°C to 70°C)
Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
34 AT89C51RC 1920B–MICRO–11/02
44A – TQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
44A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
35
AT89C51RC
1920B–MICRO–11/02
44J – PLCC
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B
44J
10/04/01
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
36 AT89C51RC 1920B–MICRO–11/02
40P6 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP) B
40P6
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
Printed on recycled paper.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the infor mation contained herein. No licenses to patents or other intellectual proper ty of Atmel are granted
by the Company in connection with the s ale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life suppor t devices or systems.
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