TB62D787FTG TOSHIBA BiCD Digital Integrated Circuit Silicon Monolithic TB62D787FTG 24-channel constant current LED driver with single wire The TB62D787FTG is a constant current driver designed for LED illumination. The TB62D787FTG incorporates 7-bit PWM dimming controllers and 24 channels of constant current drivers. Twenty four constant current circuits are divided into three blocks corresponding to LED luminescence color, and each output current can be adjusted by the external resistors. This product is controlled using only single DATA-IN input signal. The TB62D787FTG can be set maximum 64 ID recognition addresses with the ID setting pin. The LDO function (7 to 28 V) to share this product with LED power supply is included. Additionally the Bi-CMOS process adoption allows high-speed data transmission. TB62D787FTG P-VQFN40-0606-0.50-001 Weight: 0.097g (typ.) Feature * Power supply voltage: VL = 7.0 to 28 V (The case used by sharing with a power supply of LED) Vcc = 5.0 V 10 (The case which supplies a power supply of LED and a power supply of IC separately) * Output withstand voltage: 28 V (max) * Output current capability: 85 mA (max) x 24 channels * Constant current output range: 5 to 40 mA x 24 channels * Voltage applied to constant current output pins: 0.5 V (min, constant current 5 to 40 mA) * Designed for common-anode LEDs. * The input interface is controlled by DATA-IN (single wire) * Logical input signal voltage level: 5 V CMOS Interface (Schmitt trigger input) * PWM control circuit included: 7-bit PWM * Driver identification: Up to 64 drivers can be controlled individually * Thermal shut down (TSD) included. * Operating temperature range: Topr = -40 to 85C * Package: P-VQFN40-0606-0.50-001 * Constant current accuracy Output voltage Current accuracy between channels Current accuracy between ICs Output current 0.5 V 3.0% 6.0% 15 mA This product is very delicate because of elements of MOS structure. In handling, please take care of measures of static electricity, such as use of a ground band or an electric conduction mat, removal of static electricity by an ionizer, and management of temperature and humidity. (c)2017 TOSHIBA Corporation 1 2017-04-18 TB62D787FTG VL VLOUT TEST DATA-IN DATA-OUT Vcc ID2 ID1 ID0 REXT-B REXT-G Pin Assignment (top view) 30 29 28 27 26 25 24 23 22 21 20 REXT-R 31 19 GND NC 32 /OUTB1 38 13 /OUTR6 /OUTR2 39 12 /OUTB5 /OUTG2 40 11 /OUTG5 1 2 3 4 5 6 7 8 9 10 /OUTR5 14 /OUTG6 /OUTB4 /OUTG1 37 /OUTG4 15 /OUTB6 /OUTR4 /OUTR1 36 PGND 16 /OUTR7 PGND /OUTB0 35 /OUTB3 17 /OUTG7 /OUTG3 /OUTG0 34 /OUTR3 18 /OUTB7 /OUTB2 /OUTR0 33 Please be sure to connect the back radiation PAD of a QFN package to GND of a substrate. 2 2017-04-18 TB62D787FTG Block Diagram Vcc ID0 ID1 ID2 VLOUT Internal power supply Address Setting VLED (5V REG) POR DATA-IN Logic process DATA-OUT Note: REXT-B REXT-G REXT-R /OUTR0 PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver /OUTG3 PWM(7bit) Constant current driver /OUTG7 PWM(7bit) Constant current driver /OUTB0 PWM(7bit) Constant current driver PWM(7bit) Constant current driver PWM(7bit) Constant current driver /OUTB3 PWM(7bit) Constant current driver /OUTB7 Oscillator GND VL /OUTR1 /OUTR2 /OUTR3 /OUTR7 /OUTG0 /OUTG1 /OUTG2 /OUTB1 /OUTB2 PGND Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 3 2017-04-18 TB62D787FTG Pin Description Pin No. Pin name 33 /OUTR0 Constant current output pin. (Open-drain type) 34 /OUTG0 Constant current output pin. (Open-drain type) 35 /OUTB0 Constant current output pin. (Open-drain type) 36 /OUTR1 Constant current output pin. (Open-drain type) 37 /OUTG1 Constant current output pin. (Open-drain type) 38 /OUTB1 Constant current output pin. (Open-drain type) 39 /OUTR2 Constant current output pin. (Open-drain type) 40 /OUTG2 Constant current output pin. (Open-drain type) 1 /OUTB2 Constant current output pin. (Open-drain type) 2 /OUTR3 Constant current output pin. (Open-drain type) 3 /OUTG3 Constant current output pin. (Open-drain type) 4 /OUTB3 Constant current output pin. (Open-drain type) 7 /OUTR4 Constant current output pin. (Open-drain type) 8 /OUTG4 Constant current output pin. (Open-drain type) 9 /OUTB4 Constant current output pin. (Open-drain type) 10 /OUTR5 Constant current output pin. (Open-drain type) 11 /OUTG5 Constant current output pin. (Open-drain type) 12 /OUTB5 Constant current output pin. (Open-drain type) 13 /OUTR6 Constant current output pin. (Open-drain type) 14 /OUTG6 Constant current output pin. (Open-drain type) 15 /OUTB6 Constant current output pin. (Open-drain type) 16 /OUTR7 Constant current output pin. (Open-drain type) 17 /OUTG7 Constant current output pin. (Open-drain type) 18 /OUTB7 Constant current output pin. (Open-drain type) 5,6 PGND 20 REXT-R 21 REXT-G 22 REXT-B 19 GND Ground pin 23 ID0 ID setting pin 24 ID1 ID setting pin 25 ID2 ID setting pin 26 Vcc 5 V power supply input pin 27 DATA-OUT 28 DATA-IN 29 TEST 30 VLOUT 31 VL Power supply input pin in the case of sharing a power supply of LED and the power supply of this product. 32 NC Connect to GND in normal operation. Note: Function description Power ground pin. It should be connected to 19 pin (GND) externally. External resistor pin for output current configuration (/OUTR0 to 7) High resistor should be connected even if the output is unused. External resistor pin for output current configuration (/OUTG0 to 7) High resistor should be connected even if the output is unused. External resistor pin for output current configuration (/OUTB0 to 7) High resistor should be connected even if the output is unused. Serial data output pin (Buffer output of DATA-IN input signal) Serial data input pin The pin for vendor use. Please connect surely to GND in normal operation because it does not operate normally in high level or open process. 5 V Regulator output pin. Please connect this pin and Vcc pin directly when internal power supply is used. In case the Vcc voltage is applied from external power supply, please connect VL pin to GND pin. Please pay attention to short circuiting between adjacent pins when pin 29 is connected to GND. 4 2017-04-18 TB62D787FTG Equivalent circuit for inputs and outputs Pin name Equivalent circuit Vcc DATA-IN DATA-IN GND Vcc DATA-OUT DATA-OUT GND Vcc ID0 to 2 Comparator 3 to 2 decoder A2 Q1 A1 Q0 ID0 ID1 ID2 A0 GND /OUTR0 to 7 /OUTG0 to 7 /OUTB0 to 7 /OUTR0 to 7 /OUTG0 to 7 /OUTB0 to 7 PGND Note: The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 5 2017-04-18 TB62D787FTG Programming the TB62D787FTG This product performs the control with single wire data signal. As compared with 2-wire data signal synchronous with the clock signal in conventional products, this product assigns each data state to the transition state (H to L or L to H) as shown below. L H 2-wire input data L L H Single wire input data H For setting data, select from (2) Normal programming mode, (3) Special programming mode, and a) 12-channel programming mode and b) 6-channel programming mode in (4) Dividing programming mode at (1) Data setting format. (1) Data setting format Each command setting input to DATA-IN is set with the following format. This product recognizes the command frequency (1-bit data width) by taking in the start command (the start condition of data input). Since this product continues to recognize the signal interval which recognizes at the start command until the period command, input the pulse width in 1 bit within 50% duty so that the period is not collapsed until completion of the period command. (Refer to "Operating Ranges.") After the completion of the period command input, make sure to set the interval ("L") more than 10 s until next start command input. <Input format> Example) Basic input mode Interval more than 10 s Period command [10000001] DATA-IN Start command [11111111] L input Slave address Sub address Period command [10000001] Data byte Start command [11111111] L input Example 1) Start command 0xAA and 0xAA setting (original binary 11111111) DATA-IN H L H "1" L H "1" L H "1" L H "1" L H "1" L H "1" L H "1" L "1" Example 2) Period command setting 0x95 and 0x56 (original binary 10000001) DATA-IN H L "1" L H "0" L H "0" L H "0" 6 L H "0" L H "0" L H "0" H L "1" 2017-04-18 TB62D787FTG <Block diagram of data setting block> PWM counter Vcc /OUTR0 /OUTG0 /OUTB0 /OUTR1 /OUTG1 /OUTB1 /OUTR2 /OUTG2 /OUTB2 /OUTR7 /OUTG7 /OUTB7 Constant current driver R0 Constant current driver G0 Constant current driver B0 Constant current driver R1 Constant current driver G1 Constant current driver B1 Constant current driver R2 Constant current driver G2 Constant current driver B2 Constant current driver R7 Constant current driver G7 Constant current driver B7 Data compare R0 Data compare G0 Data compare B0 Data compare R1 Data Compare G1 Data compare B1 Data compare R2 Data compare G2 Data compare B2 Data compare R7 Data compare G7 Data compare B7 Data reset POR 8bit Phase detection of single or two-wire conversion PWM data G0 8bit 8-bit counter DATA-IN 8bit PWM data R0 8bit DATA 8bit 8bit PWM data B0 8bit PWM data R1 8bit PWM data G1 8bit 8bit PWM data B1 8bit 8bit 8bit PWM data R2 8bit PWM data G2 8bit 8bit 8bit 8bit PWM data R7 PWM data B2 8bit 8bit 8bit PWM data G7 8bit 8bit PWM data B7 8bit Shift register / ID compare/ Channel selection (each channel, 24-channel continuation, 12 channels x 2-time input, and 6-channel input x 4-time input) CLK 8bit Oscillator DATA-OUT ID setting ID0 ID1 ID2 (2) Normal programming mode Normal programming mode should be set as the following flow. Start command -> Slave address -> Sub-address -> Data byte -> Period command Slave address: ID setting of the chip, Sub-address: Output channel setting, Data byte: Data for PWM setting For each setting data, refer to the descriptions later. Interval Start ("L" more than 10 s) Command Slave Sub-address Data byte Address (channel select) (PWM configuration) Period Interval Command ("L" more than 10 s) (3) Special programming mode It is a setting method to set all channels individually. Special mode setting (In case all channels are selected in order)) When the special mode is set to the sub-address, the illumination data of all channels can be set. Special mode setting: 0110100101010101=0x69 and 0x55 (original binary: 01100000) If it returns to Normal programming mode, input the start command (ALL "H" 8 bits). When this mode setting is used, the quantity of the data to be set can be reduced. Interval Start ("L" more than 10 s) command Slave Sub-address Data Data Data Data Data Data Address (Special mode setting) OUTR0 OUTG0 OUTB0 OUTR1 OUTG1 OUTB1 Data Data Data Data Data Data Data Data Data Data Data Data OUTR2 OUTG2 OUTB2 OUTR3 OUTG3 OUTB3 OUTR4 OUTG4 OUTB4 OUTR5 OUTG5 OUTB5 Data Data Data Data Data Data Period OUTR6 OUTG6 OUTB6 OUTR7 OUTG7 OUTB7 command Please set 24-channel data surely. (In case the data (more than 24 channels) provided the 25th and subsequent data are treated as invalid.) 7 2017-04-18 TB62D787FTG (4) Dividing programming mode a) 12-channel programming mode (12ch+12ch=24ch) If 12-channel mode is set to sub-address, illumination data can be set in the range. 12-channel programming mode (1/2): 0110100101011001=0x69 and 0x59 (original binary: 01100010) 12-channel programming mode (2/2): 0110100101100101=0x69 and 0x65 (original binary: 01100100) Interval Start Slave ("L" more than 10 s) command address Sub-address Data Data Data Data Data Data (12ch programming 1/2) OUTR0 OUTG0 OUTB0 OUTR1 OUTG1 OUTB1 (12ch programming 2/2) OUTR4 OUTG4 OUTB4 OUTR5 OUTG5 OUTB5 Data Data Data Data Data Data OUTR2 OUTG2 OUTB2 OUTR3 OUTG3 OUTB3 OUTR6 OUTG6 OUTB6 OUTR7 OUTG7 OUTB7 Period command b) 6-channel programming mode (6ch+6ch+6ch+6ch=24ch) If 6-channel mode is set to sub-address, illumination data can be set in the range. 6-channel programming mode (1/4): 0110100101101001=0x69 and 0x69 (original binary:01100110) 6-channel programming mode (2/4): 0110100110010101=0x69 and 0x95 (original binary:01101000) 6-channel programming mode (3/4): 0110100110011001=0x69 and 0x99 (original binary:01101010) 6-channel programming mode (4/4): 0110100110100101=0x69 and 0xA5 (original binary:01101100) Interval Start Slave ("L" more than 10 s) command address Sub-address Data Data Data Data Data Data (6ch programming 1/4) OUTR0 OUTG0 OUTB0 OUTR1 OUTG1 OUTB1 (6ch programming 2/4) OUTR2 OUTG2 OUTB2 OUTR3 OUTG3 OUTB3 (6ch programming 3/4) OUTR4 OUTG4 OUTB4 OUTR5 OUTG5 OUTR5 (6ch programming 4/4) OUTR6 OUTG6 OUTB6 OUTR7 OUTG7 OUTB7 Period command (5) Data settings The start command at the beginning and the period command at the end are shown in the following table. The slave address, sub-address, and PWM data byte shown below are input to between the start command and period command. Original binary Single wire input Hexadecimal Decimal Start 11111111 1010101010101010 0xAA,0xAA 170,170 Period Original binary 10000001 Single wire input 1001010101010110 Hexadecimal 0x95,0x56 Decimal 149,86 a) Slave address Input voltages and logic states of the ID0, ID1, and ID2 pins are determined as follows. *: Please set it as a pin for one of REXT-R, -G, and -B. ID 0 1 2 3 4 5 6 7 8 9 10 11 Original binary 00000000 00000010 00000100 00000110 00001000 00001010 00001100 00001110 00010000 00010010 00010100 00010110 Slave address Single wire input Hexadecimal 0101010101010101 0x55,0x55 0101010101011001 0x55,0x59 0101010101100101 0x55,0x65 0101010101101001 0x55,0x69 0101010110010101 0x55,0x95 0101010110011001 0x55,0x99 0101010110100101 0x55,0xA5 0101010110101001 0x55,0xA9 0101011001010101 0x56,0x55 0101011001011001 0x56,0x59 0101011001100101 0x56,0x65 0101011001101001 0x56,0x69 8 Decimal 85,85 85,89 85,101 85,105 85,149 85,153 85,165 85,169 86,85 86,89 86,101 86,105 ID2 GND GND GND GND GND GND GND GND GND GND GND GND ID setting ID1 ID0 GND GND GND REXT-R/G/B* GND Open GND Vcc REXT-R/G/B* GND REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* Open REXT-R/G/B* Vcc Open GND Open REXT-R/G/B* Open Open Open Vcc 2017-04-18 TB62D787FTG a) Slave address (continues) ID 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 ** Original binary 00011000 00011010 00011100 00011110 00100000 00100010 00100100 00100110 00101000 00101010 00101100 00101110 00110000 00110010 00110100 00110110 00111000 00111010 00111100 00111110 01000000 01000010 01000100 01000110 01001000 01001010 01001100 01001110 01010000 01010010 01010100 01010110 01011000 01011010 01011100 01011110 01100000 01100010 01100100 01100110 01101000 01101010 01101100 01101110 01110000 01110010 01110100 01110110 01111000 01111010 01111100 01111110 0XXXXXX1 **: The original binary number Slave address Single wire input Hexadecimal Decimal 0101011010010101 0x56,0x95 86,149 0101011010011001 0x56,0x99 86,153 0101011010100101 0x56,0xA5 86,165 0101011010101001 0x56,0xA9 86,169 0101100101010101 0x59,0x55 89,85 0101100101011001 0x59,0x59 89,89 0101100101100101 0x59,0x65 89,101 0101100101101001 0x59,0x69 89,105 0101100110010101 0x59,0x95 89,149 0101100110011001 0x59,0x99 89,153 0101100110100101 0x59,0xA5 89,165 0101100110101001 0x59,0xA9 89,169 0101101001010101 0x5A,0x55 90,85 0101101001011001 0x5A,0x59 90,89 0101101001100101 0x5A,0x65 90,101 0101101001101001 0x5A,0x69 90,105 0101101010010101 0x5A,0x95 90,149 0101101010011001 0x5A,0x99 90,153 0101101010100101 0x5A,0xA5 90,165 0101101010101001 0x5A,0xA9 90,169 0110010101010101 0x65,0x55 101,85 0110010101011001 0x65,0x59 101,89 0110010101100101 0x65,0x65 101,101 0110010101101001 0x65,0x69 101,105 0110010110010101 0x65,0x95 101,149 0110010110011001 0x65,0x99 101,153 0110010110100101 0x65,0xA5 101,165 0110010110101001 0x65,0xA9 101,169 0110011001010101 0x66,0x55 102,85 0110011001011001 0x66,0x59 102,89 0110011001100101 0x66,0x65 102,101 0110011001101001 0x66,0x69 102,105 0110011010010101 0x66,0x95 102,149 0110011010011001 0x66,0x99 102,153 0110011010100101 0x66,0xA5 102,165 0110011010101001 0x66,0xA9 102,169 0110100101010101 0x69,0x55 105,85 0110100101011001 0x69,0x59 105,89 0110100101100101 0x69,0x65 105,101 0110100101101001 0x69,0x69 105,105 0110100110010101 0x69,0x95 105,149 0110100110011001 0x69,0x99 105,153 0110100110100101 0x69,0xA5 105,165 0110100110101001 0x69,0xA9 105,169 0110101001010101 0x6A,0x55 106,85 0110101001011001 0x6A,0x59 106,89 0110101001100101 0x6A,0x65 106,101 0110101001101001 0x6A,0x69 106,105 0110101010010101 0x6A,0x95 106,149 0110101010011001 0x6A,0x99 106,153 0110101010100101 0x6A,0xA5 106,165 0110101010101001 0x6A,0xA9 106,169 0101010101010110 0x55,0x56 85,86 9 of all the selections is defined ID setting ID2 ID1 GND Vcc GND Vcc GND Vcc GND Vcc REXT-R/G/B* GND REXT-R/G/B* GND REXT-R/G/B* GND REXT-R/G/B* GND REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* REXT-R/G/B* Open REXT-R/G/B* Open REXT-R/G/B* Open REXT-R/G/B* Open REXT-R/G/B* Vcc REXT-R/G/B* Vcc REXT-R/G/B* Vcc REXT-R/G/B* Vcc Open GND Open GND Open GND Open GND Open REXT-R/G/B* Open REXT-R/G/B* Open REXT-R/G/B* Open REXT-R/G/B* Open Open Open Open Open Open Open Open Open Vcc Open Vcc Open Vcc Open Vcc Vcc GND Vcc GND Vcc GND Vcc GND Vcc REXT-R/G/B* Vcc REXT-R/G/B* Vcc REXT-R/G/B* Vcc REXT-R/G/B* Vcc Open Vcc Open Vcc Open Vcc Open Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc All select as x = 0. ID0 GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc GND REXT-R/G/B* Open Vcc 2017-04-18 TB62D787FTG b) Sub-address Original binary 00000010 00000100 00000110 00001000 00001010 00001100 00001110 00010000 00010010 00010100 00010110 00011000 00011010 00011100 00011110 00100000 00100010 00100100 00100110 Output channels, all channels selection, special programming mode, 6-channel programming mode, or 12-channel programming mode can be set. Sub-address Target setting of PWM LED output data Single wire input Hexadecimal Decimal 0101010101011001 0x55,0x59 85,89 /OUTR0 0101010101100101 0x55,0x65 85,101 /OUTG0 0101010101101001 0x55,0x69 85,105 /OUTB0 0101010110010101 0x55,0x95 85,149 /OUTR1 0101010110011001 0x55,0x99 85,153 /OUTG1 0101010110100101 0x55,0xA5 85,165 /OUTB1 0101010110101001 0x55,0xA9 85,169 /OUTR2 0101011001010101 0x56,0x55 86,85 /OUTG2 0101011001011001 0x56,0x59 86,89 /OUTB2 0101011001100101 0x56,0x65 86,101 /OUTR3 0101011001101001 0x56,0x69 86,105 /OUTG3 0101011010010101 0x56,0x95 86,149 /OUTB3 One channel is set 0101011010011001 0x56,0x99 86,153 /OUTR4 separately. 0101011010100101 0x56,0xA5 86,165 /OUTG4 0101011010101001 0x56,0xA9 86,169 /OUTB4 0101100101010101 0x59,0x55 89,85 /OUTR5 0101100101011001 0x59,0x59 89,89 /OUTG5 0101100101100101 0x59,0x65 89,101 /OUTB5 0101100101101001 0x59,0x69 89,105 /OUTR6 00101000 00101010 00101100 00101110 00110000 0101100110010101 0101100110011001 0101100110100101 0101100110101001 0101101001010101 0x59,0x95 0x59,0x99 0x59,0xA5 0x59,0xA9 0x5A,0x55 89,149 89,153 89,165 89,169 90,85 /OUTG6 /OUTB6 /OUTR7 /OUTG7 /OUTB7 01000000 0110010101010101 0x65,0x55 101,85 All channel select 01100000 0110100101010101 0x69,0x55 105,85 01100010 0110100101011001 0x69,0x59 105,89 01100100 0110100101100101 0x69,0x65 105,101 01100110 0110100101101001 0x69,0x69 105,105 01101000 0110100110010101 0x69,0x95 105,149 01101010 0110100110011001 0x69,0x99 105,153 01101100 0110100110100101 0x69,0xA5 105,165 10 Special programming mode 12-channel programming mode (1/2) 12-channel programming mode (2/2) 6-channel programming mode (1/4) 6-channel programming mode (2/4) 6-channel programming mode (3/4) 6-channel programming mode (4/4) All 24 channels are set as same. 24 channels are set at one time. 12 channels are set at two times. 6 channels are set at four times. 2017-04-18 TB62D787FTG c) Data byte Original binary 00000000 00000010 00000100 00000110 00001000 00001010 00001100 00001110 00010000 to 00011110 00100000 to 00101110 00110000 to 00111110 01000000 to 01001110 01010000 to 01011110 01100000 to 01101110 01110000 to 01111110 10000000 to 10001110 10010000 to 10011110 10100000 to 10101110 10110000 to 10111110 11000000 to 11001110 11010000 to 11011110 11100000 to 11101110 11110000 to 11111110 Data bytes set PWM dimming data. PWM data byte Single wire input Hexadecimal 0101010101010101 0x55,0x55 0101010101011001 0x55,0x59 0101010101100101 0x55,0x65 0101010101101001 0x55,0x69 0101010110010101 0x55,0x95 0101010110011001 0x55,0x99 0101010110100101 0x55,0xA5 0101010110101001 0x55,0xA9 0101011001010101 0x56,0x55 to -- 0101011010101001 0x56,0xA9 0101100101010101 0x59,0x55 to -- 0101100110101001 0x59,0xA9 0101101001010101 0x5A,0x55 to -- 0101101010101001 0x5A,0xA9 0110010101010101 0x65,0x55 to -- 0110010110101001 0x65,0xA9 0110011001010101 0x66,0x55 to -- 0110011010101001 0x66,0xA9 0110100101010101 0x69,0x55 to -- 0110100110101001 0x69,0xA9 0110101001010101 0x6A,0x55 to -- 0110101010101001 0x6A,0xA9 1001010101010101 0x95,0x55 to -- 1001010110101001 0x95,0xa9 1001011001010101 0x96,0x55 to -- 1001011010101001 0x96,0xa9 1001100101010101 0x99,0x55 to -- 1001100110101001 0x99,0xa9 1001101001010101 0x9a,0x55 to -- 1001101010101001 0x9a,0xa9 1010010101010101 0xa5,0x55 to -- 1010010110101001 0xa5,0xa9 1010011001010101 0xa6,0x55 to -- 1010011010101001 0xa6,0xa9 1010100101010101 0xa9,0x55 to -- 1010100110101001 0xa9,0xa9 1010101001010101 0xaa,0x55 to -- 1010101010101001 0xAA,0xA9 11 Decimal 85,85 85,89 85,101 85,105 85,149 85,153 85,165 85,169 86,85 -- 86,169 89,85 -- 89,169 90,85 -- 90,169 101,85 -- 101,169 102,85 -- 102,169 105,85 -- 105,169 106,85 -- 106,169 149,85 -- 149,169 150,85 -- 150,169 153,85 -- 153,169 154,85 -- 154,169 165,85 -- 165,169 166,85 -- 166,169 169,85 -- 169,169 170,85 -- 170,169 PWM dimming 0/127 1/127 2/127 3/127 4/127 5/127 6/127 7/127 8/127 to 15/127 16/127 to 23/127 24/127 to 31/127 32/127 to 39/127 40/127 to 47/127 48/127 to 55/127 56/127 to 63/127 64/127 to 71/127 72/127 to 79/127 80/127 to 87/127 88/127 to 95/127 96/127 to 103/127 104/127 to 111/127 112/127 to 119/127 120/127 to 127/127 Note The initial state is set to 0/127 and is always OFF state. As the original binary, set "0" to LSB, and do not set "1." 127/127 is always ON state. 2017-04-18 TB62D787FTG (6) Notes of data setting This product has the specification of data recognition or processing with only a data signal (asynchronous input signal). The data period (communication speed) is learned with the start command (data input start condition). Data are recognized according to this learning period, and are stored to the internal register after the period command (a condition of data input completion). Therefore, the data are not recognized if the data period is collapsed between the start command and the period command (see the following a)). Then the period learned during an interval period is reset and it waits for next communication. a) Learning data period Interval L fixed at more than 10 s Start command Slave address (ID) The period and phase of the communication data is learned during the start command period. Sub-address (Communication mode) Data byte (Illuminating data) Data byte (Illuminating data) The communication data is recognized based on the period and phase learned during the start command period. After learning, Data are not recognized if the intervals and phases are changed compared with the learned result between the slave address and period command. (such as the disturbance of transfer periodicity caused by a disturbance noise or a microcontroller) Period command After the recognition of the period command, the data byte is stored to the internal register when the internal counter counts zero. b) Data recognition The duty of H/L pulse width to input to this product should be set within 10 as shown below. If the duty is out of this range, data cannot be recognized correctly. (Refer to the following "Operating Ranges.") 5010% 0 If there is a reversal of data polarity in this period, communication data can be recognized. H L L H 50 100 12 2017-04-18 TB62D787FTG <Reference: Example of control data input> (7) Example of basic data input to the same ID When data is input to the same ID, next data should be input at the interval of 3 ms or more (128 times of internal PWM clocks) regardless of same or change of sub-address at last input. If the setting to the same channel is overlapped, PWM control cannot perform correctly. If data is input to other slave address, it is not necessary. The following from a) to e) corresponds to them if a sub-address is in each output channel, all channels select or special programming mode. Refer to f) to g) if a sub-address is in 6-channel programming mode or 12-channel programming mode. a) In case DATA "A" is input up to the rising edge of 127 internal PWM clocks. Transferring DATA "A" Reflecti ng LED output Internal PWM clock Pattern 1 125 START DATA "A" PERIOD 0 127 0 127 126 DATA "A" starts to output Input invalid period Output DATA "A" starts at the rising edge of zero internal PWM clocks. Inputting is invalid from the rising edge of 127 internal PWM clocks to the rising edge of zero internal PWM clocks which are just after these 127 PWM clocks. b) In case DATA "A" is input after the rising edge of 127 internal PWM clocks. PERIOD ends after 127 clocks Internal PWM clock Pattern 2 START 125 126 DATA "A" 127 Reflecti ng LED output Transferring DATA "A" 0 127 0 PERIOD DATA "A" starts to output Input invalid period DATA "A" cannot be transferred at the rising edge of 127 internal PWM clocks just after inputting DATA "A." Therefore, DATA "A" starts an output at the rising edge of zero PWM clocks, after passing the rising edge of next 127 internal PWM clocks. The input invalid period is the period to the rising edge of internal PWM clock 0 of which DATA "A" starts to output. c) In case DATA "B" is input after starting the output of pattern 1 Reflecti ng LED output Transferring DATA "A" Internal PWM clock Pattern 3 START 125 DATA "A" 126 127 0 126 START PERIOD Input invalid period Reflecti ng LED output Transferring DATA "B" DATA "B" DATA "A" starts to output 127 0 PERIOD Input invalid period DATA "B" starts to output DATA "A" starts an output at the rising edge of zero internal PWM clocks just after DATA "A" period. Then DATA "B" starts an output at rising edge of zero internal PWM clocks just after DATA "B" period. The input invalid period is the period from the rising edge of 127 internal PWM clocks just after the period input to the rising edge of zero internal PWM clocks. 13 2017-04-18 TB62D787FTG Pay attention that the IC does not operate according to the configuration while the following patterns (patterns 4 and 5) are input. d) In case DATA "B" is input before DATA "A" starts output Transferring DATA "A" Internal PWM clock Pattern 4 125 START DATA "A" 0 127 126 PERIOD 126 Input invalid period START DATA "B" Reflecti ng LED output 127 0 PERIOD DATA "B" is invalid because DATA "A" bec omes latest data. DATA "A" starts to output The period between DATA "A" period end and the second rising edge of zero internal PWM clocks is the input invalid period. Therefore, DATA "B" is invalid and DATA "A" is output. e) In case the period command of DATA "A" is not recognized Not transferring because PERIOD is not input. Internal PWM clock Pattern 5 START 125 DATA "A" 126 127 0 126 START PERIOD is not input. Reflecti ng LED output Transferring DATA "B" DATA "B" 127 0 PERIOD DATA "B" bec omes latest data. DATA "A" is invalid data because PERIOD is not input. Input invalid period DATA "B" starts to output. When the period of DATA "A" is not input and the period of next DATA "B" is input, DATA "B" starts output immediately after at the rising edge of zero internal PWM clocks. 14 2017-04-18 TB62D787FTG f) 6-channel programming mode / 12-channel programming mode When a 6-channel programming mode group (1/4 -> 2/4 -> 3/4 -> 4/4) or 12-channel programming mode group (1/2-> 2/2) is input continuously in order, the interval of 3 ms or more is not necessary. However when same IDs and same channel data in 6 or 12-channel programming mode are input, the interval of 3 ms or more is necessary. PWM control may not be performed correctly. Transferring DATA "A" Reflecti ng LED output Internal PWM clock Pattern 6 START 125 DATA "A" 127 126 Pattern 7 START 125 DATA "A" 0 DATA "A" output starts PERIOD DATA "A" in 12-channel programming mode Internal PWM clock 127 0 Transferring DATA "B" Reflecti ng LED output Transferring DATA "A" Reflecti ng LED output 127 126 0 126 START PERIOD DATA "B" PERIOD DATA "B" in 12-channel input mode DATA "A" in 12-channel programming mode DATA "B" starts to output. DATA "A" starts to output. Transferring DATA "B" Reflecti ng LED output Transferring DATA "A" Reflecti ng LED output Internal PWM clock Pattern 8 125 0 127 0 127 126 126 START START DATA "A" PERIOD DATA "A" in 12-channel programming mode DATA "B" 0 127 PERIOD DATA "B" in 12-channel input mode DATA "B" starts to output . DATA "A" starts to output. Since there is no input invalid period, an input data are started to output at the rising edge of the first zero internal PWM clocks after inputting the period command. Therefore, when other programming mode is input immediately after 6-channel or 12-channel programming, the 6-channel or 12-channel programming data immediately before are re-written to the data input in other programming mode. When 6-channel or 12-channel programming is used, 24-channel units of input are recommended. Transferring DATA "A" Reflecti ng LED output Internal PWM clock Pattern 9 START 125 126 DATA "A" PERIOD DATA "A" in 6- or 12channel input mode 127 0 Transferring DATA "C" Reflecti ng LED output 126 START DATA "A" starts to output 15 DATA "C" 127 0 PERIOD DATA "C" is not in 6- or 12-channel input mode DATA "C" starts to output 2017-04-18 TB62D787FTG g) In case the period command mistakes Not transferring because PERIOD is not input. Internal PWM clock Pattern 10 START 125 DATA "A" DATA "A" of 6 / 12channel programming Pattern 11 START DATA "A" DATA "A" of 6 / 12channel programming 126 PERIOD is not input. PERIOD is not input. 127 0 Transferring DATA "B" Reflecti ng LED output 127 126 START DATA "B" PERIOD DATA "B" of 6 / 12channel programming START DATA "B" PERIOD 0 6- or 12-channel input mode performs a data transfer and an output start when the internal PWM clock is zero. DATA "B" of 6 / 12channel programming DATA "B" bec omes latest data and DATA "A" is invalid because PERIOD is not input. DATA "B" starts to output. DATA "B" starts to output at the rising edge of zero internal PWM clocks if the period of DATA "A" is not input and the period of next DATA "B" is input. 16 2017-04-18 TB62D787FTG (8) Example of basic data input to the different ID. a) In case DATA "B" is input to slave (= 02h) just after DATA "A" is input to slave (= 00h). Transferring DATA "A" and "B" (Except 6- or 12 channel mode) Internal PWM clock Pattern 12 START 126 SLAVE#00h,DATA "A" PERIOD START SLAVE#02h,DATA "B" Reflecti ng LED output 0 127 PERIOD DATA "A" starts to output SLAVE#00h output DATA "B" starts to output SLAVE#02h output Both DATA "A" and DATA "B" are output at the rising edge of zero internal PWM clock which is just after DATA "A" and DATA "B" inputs. <Reference> Pay attention that the IC does not operate according to the configuration while following patterns (patterns 13 and 14) are input. b) In case period command after inputting DATA "A" to the slave (= 00h) is missed or omitted. In case period command after inputting DATA "B" to the slave (= 02h) is missed or omitted. Transferring DATA "A" (Except 6- or 12-channel mode) Reflecti ng LED output Internal PWM clock 126 SLAVE#00h,DATA "A" Miss (omit) START Pattern 13 START 0 127 SLAVE#02h,DATA "B" Miss (omit) DATA "A" starts to output SLAVE#00h output SLAVE#02h output DATA "A" is output. DATA "B" is not output. c) In case start command is input after DATA "B" of pattern 13 is input. Transferring DATA "A" (Except 6- or 12-channel mode) Internal PWM clock Pattern 14 START 126 SLAVE#00h,DATA "A" Miss (omit) START SLAVE#02h,DATA "B" Miss (omit) START SLAVE#00h output 127 Reflecti ng LED output 0 DATA "A" starts to output SLAVE#02h output DATA "A" is output. DATA "B" is not output. 17 2017-04-18 TB62D787FTG Power Supply Block The power supply of this product can be set with the following 2 ways shown in (1) and (2). (1) When the power supply of LEDs and those of this product are shared (The power supply function of this product is used.) (2) When this product is operated with 5 V power supply input, not sharing the power supply of LEDs (The power supply function of this product is not used.) Each settings are shown below. (1) When the power supply of LEDs and those of this product are shared VLOUT Vcc (5.0 V) Linear regulator VL LED power supply 5 V control circuit GND LED As shown in the above, the power supply (7.0 to 28 V) is applied to the VL pin, and VOUT and Vcc pins are connected directly. VLOUT pin output (5 V) should be connected within 15 mA dc (@ all LED outputs 40 mA) except connecting to Vcc of own product. (2) When 5 V power supply is input to Vcc pin directly 5 V power supply VLOUT Vcc (5.0 V) LED power supply Linear regulator VL 5 V control circuit GND LED When 5 V power supply is applied to this product without using the built-in power supply, ground VL pin and VLOUT pin to GND. Note: Add decoupling capacitors to VL pin and Vcc pin. The recommended values are as follows. Recommended value of decoupling capacitors between VL (LED power supply) and GND: 1F of electrolytic capacitor *: Evaluate appropriately since it is dependent on the main power supply performance. Recommended value of decoupling capacitors between Vcc (5 V power supply) and GND: 1F of electrolytic capacitor and 0.1F of ceramic capacitor *: Evaluate appropriately since it is dependent on the LED current to be set and current supply amount of VLOUT. 18 2017-04-18 TB62D787FTG Data buffer Data buffer is built in between DATA-IN and DATA-OUT, and it can be used for the cascade connection of two or more these products. In the case of cascade connection with this buffer, connect up to 5 pieces (@2MHz communication) on the same board. DATA-IN TB62D787FTG DATA-OUT MCU DATA-IN DATA TB62D787FTG DATA-OUT DATA-IN TB62D787FTG Power on reset (POR) It avoids the malfunction by the reset all internal data of IC and setting default in startup. POR circuit operates only when VDD rises from 0 V. To restart POR, Vcc should be 0 V. As for the voltage of storing the internal data, it is guaranteed after Vcc reaches 4.5 V or more once. Vcc waveform Initial clear .0 V Reset voltage 1.8 V Lower limit voltage for guaranteed data End of POR 0V POR working range Beyond POR working range 19 POR working range 2017-04-18 TB62D787FTG Thermal shutdown function (TSD) When the temperature of internal IC exceeds 150C, all constant current outputs are turned off by this function. The constant current is output again when the temperature decreases to the rating. TSD operation temperature TSD reset temperature Note: 150C to 180C -20C from TSD operation temperature TSD function aims at detecting abnormal heating of ICs. Please avoid positively using the TSD function. Notes of setting 1. Output load This product is the driver in which loads are LEDs. Do not connect loads except LEDs to the output. 2. External resistor for LED drive current setting (REXT-R, REXT-G, and REXT-B) The external resistances to be connected to REXT-R, REXT-G, and REXT-B pins should be connected separately. Three pins should not be shared as one pin. The current error may occur in each RGB. 3. Operation sequence of ID setting The ID setting can be available when Vcc exceeds 4.5 V after turning on. However, in order to prevent malfunction of the ID setting, the transitional input signals of less than 2-clock period of external input data (DATA-IN) are not received. Vcc waveform 4.5 V 4.5 V Available range of ID setting Not available range of ID setting 4. Not available range of ID setting Data setting The gradation signals should be input data for 24 channels in the special mode certainly. When the data are input to over 24 channels, the data until the input channel are held and the data in 25th channel are invalid. When the data are input to less than 24 channels, the data of channels to be input are held, and the data of channels not to be input are held data before the input. The gradation signals should be input data for specified channels in 6- or 12-channel programming mode. When the data are input to over specified channels, the data until input channel are held and the data over specified channels are invalid. When the data input to less than specified channels, the data of channels to be input are held, and the data of channels not to be input are held data before the input. Moreover, do not input data which are not indicated in this document. Confirm "Programming the TB62D787FTG" and "(6) Notes of data setting." 5. Data setting timing When data are input to same slave address, next data should be input with spacing the interval 3 ms or more (128 internal PWM clocks) because data may not be received. When data are input to different slave address, the interval 3 ms (128 internal PWM clocks) or more is not required. 6. Decoupling capacitor For the stabilization of power supply system, it is recommended that decoupling capacitor between power supply and GND should place as near IC as possible. For details, refer to "Power Supply Block." 20 2017-04-18 TB62D787FTG State Transition Diagram <With VL pin> VLOUT pin and Vcc pin are wire-connected beforehand, and set each IC's ID (from ID0 to ID2 pin). Turning on power supply (VL pin) VLOUT pin supplies IC operation voltage (more than 4.5 V). VCC pin voltage reaches 4.5 V or more. ID recognition Data should be input after VCC voltage reaches 4.5 V and more, and minimum 15 ms passes. Normal mode The PWM data of each output is updated for every ID set by the DATA signals, and LED illuminating is controlled. Less than TSD detecting temperature range More than TSD detecting temperature TSD (ThermalShutDown) mode All LED outputs are forced to OFF if the TSD detection temperature has reached. Internal data are held. <Without VL pin> VLOUT pin and VCC pin are wire-connected to GND beforehand, and set each IC's ID (from ID0 to ID2 pin). Turning on IC power supply (VCC pin) VCC pin voltage reaches 4.5 V or more. ID recognition Data should be input after VCC voltage reaches 4.5 V and more, and minimum 15 ms passes. Normal mode The PWM data of each output is updated for every ID set by the DATA signals, and LED illuminating is controlled. More than TSD detecting temperature TSD (ThermalShutDown) Less than TSD detecting temperature range mode All LED outputs are forced to OFF if the TSD detection temperature has reached. Internal data are held. 21 2017-04-18 TB62D787FTG Absolute Maximum Ratings (Ta=25C) Characteristics Symbol Rating Unit VL pin power supply voltage VL 29 V Vcc pin power supply voltage Vcc 6.0 V Input voltage VIN -0.3 to 6.0 V Output current IOUT 85 (Note 3) mA/ch Output voltage VOUT -0.3 to 29 V Pd 4.3 (Note 1)(Note 2) W Rth (j-a) 29.1 (Note 1) C/W Operating Temperature Rating Topr -40 to 85 C Storage Temperature Rating Tstg -55 to 150 C Tj 150 C Power dissipation Thermal resistance Maximum junction Temperature Note 1: When mounted on a PCB (Board size: 76.2x114.3x1.6mm, Cu=30%, 35m thickness, Compliant with SEMI, 4 layers) Note 2: Power dissipation is reduced by 1/ Rth(j-a) for each C above 25C ambient. Note 3: Current may be further restricted due to ambient temperature or board condition. Ta: Ambient temperature of ICs Topr: Ambient temperature of ICs to be operated Tj: IC chip temperature during operating For the design, it is recommended that the maximum of Tj is considered of the amount of use dissipation at about 120C. Power Dissipation of package Saturation thermal resistance: 29.1C/W Power dissipation: 4.3 W Maximum operating temperature: 85C Maximum junction temperature: 150C Power dissipation (Pd)(W) 4.3 0 25 85 150 Ambient temperature (Topr)(C) 22 2017-04-18 TB62D787FTG Operating Ranges (Ta=-40 to 85C, unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit VL pin power supply voltage VL -- 7.0 -- 28 V Vcc pin power supply voltage Vcc -- 4.5 -- 5.5 V Output voltage VOUT(ON) All outputs 0.5 -- 4 V Output current IOUT All outputs 5 -- 40 mA/ch Fin -- 0.5 -- 2.0 MHz Fin(duty) -- 40 50 60 0.7 x Vcc -- Vcc VIL GND -- 0.3 x Vcc VID0 0 -- 0.1 Input DATA Frequency Input DATA Duty VIH Input Voltage VID1 DATA-IN ID0, ID1, ID2 VID2 VLOUT load current Vl Except Supply current LED current setting is up to 40 mA. 23 V VREXT VREXT VREXT -0.1 +0.1 Vcc -0.1 -- Vcc -- -- 15 mA 2017-04-18 TB62D787FTG Electrical Characteristics (Ta=25C, VL=15V, VCC=VLOUT, Unless otherwise specified) Characteristics Symbol Output current Output current accuracy between channels Max Unit 12.5 13.3 14.1 mA IOUT2 VOUT = 0.5 V, REXT = 1.2 k All output ON -- -- 3.0 % VOUT = 28 V -- -- 1 A 4.5 -- 5.5 V VLOUT -- IIH DATA-IN -- -- 1 IIL DATA-IN -- -- -1 IID ID0, ID1, ID2 -- -- 10 %/Vcc When changed Vcc = 4.5 V to 5.5 V -- 1 2 Icc (VL) When applied VL=15 V REXT = 1.2 k, VOUT = 0.5 V, -- 12 19 -- 11.5 16 Vcc -0.4 -- -- V -- -- 0.4 V -- -- 20 -- -- 20 -- 70 -- Input current Power supply current in operation Icc (Vcc) REXT = 1.2 k, VOUT = 0.5 V, VOH IOH= -1 mA L Level DATA-OUT pin Output Voltage VOL IOL= 1 mA DATA-IN-DATA-OUT Propagation Delay Time (Note) tpLH PWM reference frequency fPWM tpHL A % mA When connected VL=GND H Level DATA-OUT pin Output Voltage Note: Typ. VOUT = 0.5 V, REXT = 1.2 k IOZ Output current dependent on Vcc Min IOUT1 Output leakage current VLOUT pin voltage Test Condition CL = 15 pF, tf = tf = 3 ns Reference frequency of internal PWM counter ns kHz DATA-IN - DATA-OUT definition 90% 90% DATA-IN 50% 50% 10% 10% tr tf tpHL tpLH DATA-OUT 50% 50% 24 2017-04-18 TB62D787FTG Test Circuit Test Circuit 1 Input Current (IIH) VL Vcc VLOUT VL A DATA-IN OUTR0 A ID0,1,2 OUTB7 REXT-R REXT-G REXT-B GND PGND Test Circuit 2 Input Current (IIL) VL Vcc VLOUT VL A DATA-IN OUTR0 A ID0,1,2 OUTB7 REXT-R REXT-G REXT-B GND PGND Test Circuit 3 Supply Current (VL) Vcc VLOUT A VL VL F.G OUTB7 REXT-R REXT-G REXT-B REXT=1.2k ID0=0.1V ID1=V(REXT)0.1V ID2=Vcc-0.1V ID0 ID1 ID2 REXT=1.2k ID setting OUTR0 REXT=1.2k VIH=Vcc VIL=GND 25 GND PGND 2017-04-18 TB62D787FTG Test Circuit 4 Supply Current (Vcc) Vcc VLOUT A VL Vcc F.G OUTR0 ID0 ID1 ID2 REXT-R REXT-G REXT-B REXT=1.2k ID0=0.1V ID1=V(REXT)0.1V ID2=Vcc-0.1V OUTB7 REXT=1.2k ID setting REXT=1.2k VIH=Vcc VIL=GND GND PGND Test Circuit5 Output Current / Output Leakage Current / Output Current Accuracy / Changes in Constant Output current dependent on Vcc Vcc Vcc F.G REXT-R REXT-G REXT-B REXT=1.2k ID0=0.1V ID1=V(REXT)0.1V ID2=Vcc-0.1V ID0 ID1 ID2 REXT=1.2k ID setting REXT=1.2k VIH=Vcc VIL=GND VLOUT 26 VL OUTR0 A OUTB7 A GND PGND VOUT =0.5V, 28V 2017-04-18 TB62D787FTG Output current - derating (illuminating rate) graph Board condition: 76.2x114.3x1.6 mm, Cu=30%, 35 m thickness, compliant with SEMI When the pulse width is 25 ms or more, it is regarded as DC. IOUT - Duty IOUT - Duty 40 40 VL=15V VL=28V 30 30 25 25 20 Ta=25 VL=15V / 28V VDS=1.0V On PCB (4-Layer) 24ch ON 15 10 5 0 20 10 20 30 Ta=55 VL=15V / 28V VDS=1.0V On PCB (4-Layer) 24ch ON 15 10 5 0 0 VL=15V VL=28V 35 IOUT (mA) IOUT (mA) 35 40 50 60 70 80 90 100 0 10 20 IOUT - Duty 50 60 70 80 VL=28V 60 IOUT (mA) 25 20 Ta=85 VL=15V / 28V VDS=1.0V On PCB (4-Layer) 24ch ON 15 10 5 0 10 20 30 40 50 Unused linear regulator Ta=85 VL=0V, VLOUT=0V VCC=4.5 to 5.5V VDS=1.0V On PCB (4-Layer) 24ch ON 30 10 60 70 80 90 0 100 Duty - turn on rate (%) VL=28V 40 20 50 100 VL=15V 70 30 90 80 35 IOUT (mA) 40 IOUT - Duty VL=15V 40 0 30 Duty - turn on rate (%) Duty - turn on rate (%) 0 10 20 30 40 50 60 70 80 90 100 Duty - turn on rate (%) Output current - external resistance characteristic (typ.) IOUT - REXT 90 80 70 IOUT=1.128(V)REXT()*14.18 50 40 30 20 3 2.8 2.6 2.4 2 2.2 1.8 1.6 1.4 1 1.2 0.8 0.6 0.4 0 0 10 0.2 IOUT (mA) 60 REXT (k) 27 2017-04-18 TB62D787FTG Application circuit 1 LED power supply VLED ID0 ID1 ID2 VLOUT Vcc DATA-IN MCU /OUTR0 ID0 /OUTB7 TB62D787FTG VLOUT VL Vcc DATA-OUT REXT-R REXT-G REXT-B ID1 ID2 /OUTR0 /OUTB7 TB62D787FTG VL DATA-IN GND REXT-R REXT-G REXT-B GND DATA 28 2017-04-18 TB62D787FTG Application circuit 2 When it controls from the same ports of TB62D612FTG, which is 2-wire input control LED driver and the MCU, connect the Exclusive-OR gate (TC74VHC86) and D-Flip/Flop to preceding phase of the input of this product as shown below. At this time, the DATA and CLOCK of the interval period should be set to High level. Since phase differences between DATA from MCU outputting and clock may occur, confirm the operation enough with the following configuration. System configuration TB62D612FTG 2-wire input TB62D612FTG SDA MCU SCLK Logic TC74 VHC86 TC 7WH74 Single wire input TB62D787FTG DATA-IN TB62D787FTG Logic Composite circuit from two wire to single wire Timing charts SCLK(1.5MHz) SDA EX-OR CR delay U3(10) XOR U3(8) XOR U4(11) DATA-IN U5(5) Note: When this circuit is used, the interval period should be fixed to SDA=SCLK=High. 29 2017-04-18 TB62D787FTG Package Dimensions P-VQFN40-0606-0.50-001 Unit: mm Weight: 0.097g (Typ.) 30 2017-04-18 TB62D787FTG Notes of Contents 1. Block diagram Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing charts Timing charts may be simplified for explanatory purposes. 4. Application circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. IC Usage Considerations Notes on handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. (4) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. (5) Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. 31 2017-04-18 TB62D787FTG Points to remember on handling of ICs (1) Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. (2) Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor's power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device's motor power supply and output pins might be exposed to conditions beyond absolute maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. (3) Thermal Shutdown Circuit Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation. 32 2017-04-18 TB62D787FTG RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. * Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. * PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative. * Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. * Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. * The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. * ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. * Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. * Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 33 2017-04-18