TB62D787FTG,EL - TOSHIBA - Datasheet.Live

TB62D787FTG

TOSHIBA BiCD Digital Integrated Circuit Silicon Monolithic

TB62D787FTG

24-channel constant current LED driver with single wire

The TB62D787FTG is a constant current driver designed for LED

illumination.

The TB62D787FTG incorporates 7-bit PWM dimming controllers

and 24 channels of constant current drivers. Twenty four constant

current circuits are divided into three blocks corresponding to LED

luminescence color, and each output current can be adjusted by

the external resistors.

This product is controlled using only single DATA-IN input signal.

The TB62D787FTG can be set maximum 64 ID recognition

addresses with the ID setting pin.

The LDO function (7 to 28 V) to share this product with LED power

supply is included.

Additionally the Bi-CMOS process adoption allows high-speed data

transmission.

Feature

• Power supply voltage: VL = 7.0 to 28 V (The case used by sharing with a power supply of LED)

Vcc = 5.0 V ±10％ (The case which supplies a power supply of LED and

a power supply of IC separately)

• Output withstand voltage: 28 V (max)

• Output current capability: 85 mA (max) × 24 channels

• Constant current output range: 5 to 40 mA × 24 channels

• Voltage applied to constant current output pins: 0.5 V (min, constant current 5 to 40 mA)

• Designed for common-anode LEDs.

• The input interface is controlled by DATA-IN (single wire)

• Logical input signal voltage level: 5 V CMOS Interface (Schmitt trigger input)

• PWM control circuit included: 7-bit PWM

• Driver identification: Up to 64 drivers can be controlled individually

• Thermal shut down (TSD) included.

• Operating temperature range: Topr = -40 to 85°C

• Package: P-VQFN40-0606-0.50-001

• Constant current accuracy

Output voltage Current accuracy

between channels

Current accuracy

between ICs

Output current

0.5 V ±3.0% ±6.0% 15 mA

This product is very delicate because of elements of MOS structure. In handling, please take care of measures of static

electricity, such as use of a ground band or an electric conduction mat, removal of static electricity by an ionizer, and

management of temperature and humidity.

TB62D787FTG

P-VQFN40-0606-0.50-001

Weight: 0.097g (typ.)

TB62D787FTG

2017-04-18

Pin Assignment (top view)

Please be sure to connect the back radiation PAD of a QFN package to GND of a substrate.

8754321

2324252627282930

910

2122

/OUTB2

/OUTR3

/OUTG3

/OUTB3

PGND

/OUTR4

/OUTG4

/OUTB4

/OUTR5

/OUTG5

/OUTB5

/OUTR6

/OUTB6

/OUTR7

/OUTG7

/OUTB7

GND

REXT-R

/OUTG6

ID0

ID1

REXT-G

REXT-B

Vcc

DATA-OUT

ID2

DATA-IN

TEST

VLOUT

/OUTR0

/OUTB0

/OUTR1

/OUTG1

/OUTB1

/OUTR2

/OUTG2

/OUTG0

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Block Diagram

Note: Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for

explanatory purposes.

Logic process

PWM(7bit)

Constant

current

driver

Constant

current

driver

Constant

current

driver

Address

Setting

DATA-IN

/OUTR0

/OUTR1

/OUTR2

VLED

(5V REG)

Internal

power

supply

Vcc

PGND

ID0

ID1

ID2

REXT-R

GND

DATA-OUT

VLOUT

Oscillator

Constant

current

driver

Constant

current

driver

PWM(7bit)

/OUTR3

/OUTR7

PWM(7bit)

Constant

current

driver

Constant

current

driver

Constant

current

driver

/OUTG0

/OUTG1

/OUTG2

Constant

current

driver

Constant

current

driver

PWM(7bit)

/OUTG3

/OUTG7

PWM(7bit)

Constant

current

driver

Constant

current

driver

Constant

current

driver

/OUTB0

/OUTB1

/OUTB2

Constant

current

driver

Constant

current

driver

PWM(7bit)

/OUTB3

/OUTB7

REXT-B

REXT-G

POR

TB62D787FTG

2017-04-18

Pin Description

Pin No. Pin name Function description

33 /OUTR0 Constant current output pin. (Open-drain type)

34 /OUTG0 Constant current output pin. (Open-drain type)

35 /OUTB0 Constant current output pin. (Open-drain type)

36 /OUTR1 Constant current output pin. (Open-drain type)

37 /OUTG1 Constant current output pin. (Open-drain type)

38 /OUTB1 Constant current output pin. (Open-drain type)

39 /OUTR2 Constant current output pin. (Open-drain type)

40 /OUTG2 Constant current output pin. (Open-drain type)

1 /OUTB2 Constant current output pin. (Open-drain type)

2 /OUTR3 Constant current output pin. (Open-drain type)

3 /OUTG3 Constant current output pin. (Open-drain type)

4 /OUTB3 Constant current output pin. (Open-drain type)

7 /OUTR4 Constant current output pin. (Open-drain type)

8 /OUTG4 Constant current output pin. (Open-drain type)

9 /OUTB4 Constant current output pin. (Open-drain type)

10 /OUTR5 Constant current output pin. (Open-drain type)

11 /OUTG5 Constant current output pin. (Open-drain type)

12 /OUTB5 Constant current output pin. (Open-drain type)

13 /OUTR6 Constant current output pin. (Open-drain type)

14 /OUTG6 Constant current output pin. (Open-drain type)

15 /OUTB6 Constant current output pin. (Open-drain type)

16 /OUTR7 Constant current output pin. (Open-drain type)

17 /OUTG7 Constant current output pin. (Open-drain type)

18 /OUTB7 Constant current output pin. (Open-drain type)

5,6 PGND Power ground pin. It should be connected to 19 pin (GND) externally.

20 REXT-R External resistor pin for output current configuration (/OUTR0 to 7)

High resistor should be connected even if the output is unused.

21 REXT-G External resistor pin for output current configuration (/OUTG0 to 7)

High resistor should be connected even if the output is unused.

22 REXT-B External resistor pin for output current configuration (/OUTB0 to 7)

High resistor should be connected even if the output is unused.

19 GND Ground pin

23 ID0 ID setting pin

24 ID1 ID setting pin

25 ID2 ID setting pin

26 Vcc 5 V power supply input pin

27 DATA-OUT Serial data output pin (Buffer output of DATA-IN input signal)

28 DATA-IN Serial data input pin

29 TEST The pin for vendor use. Please connect surely to GND in normal operation because it does not operate

normally in high level or open process.

30 VLOUT 5 V Regulator output pin. Please connect this pin and Vcc pin directly when internal power supply is used.

In case the Vcc voltage is applied from external power supply, please connect VL pin to GND pin.

31 VL Power supply input pin in the case of sharing a power supply of LED and the power supply of this product.

32 NC Connect to GND in normal operation.

Note: Please pay attention to short circuiting between adjacent pins when pin 29 is connected to GND.

TB62D787FTG

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Equivalent circuit for inputs and outputs

Pin name Equivalent circuit

DATA-IN

Vcc

GND

DATA-IN

DATA-OUT

Vcc

GND

ID0 to 2

Vcc

ID0

ID1

ID2

Comparator

GND

3 to 2 decoder

/OUTR0 to 7

/OUTG0 to 7

/OUTB0 to 7

PGND

/OUTR0 to 7

/OUTG0 to 7

/OUTB0 to 7

Note: The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory

purposes.

TB62D787FTG

2017-04-18

Programming the TB62D787FTG

This product performs the control with single wire data signal. As compared with 2-wire data signal synchronous

with the clock signal in conventional products, this product assigns each data state to the transition state (H to L or

L to H) as shown below.

For setting data, select from (2) Normal programming mode, (3) Special programming mode, and a) 12-channel

programming mode and b) 6-channel programming mode in (4) Dividing programming mode at (1) Data setting

format.

(1) Data setting format

Each command setting input to DATA-IN is set with the following format.

This product recognizes the command frequency (1-bit data width) by taking in the start command (the start

condition of data input).

Since this product continues to recognize the signal interval which recognizes at the start command until the period

command, input the pulse width in 1 bit within 50% duty so that the period is not collapsed until completion of the

period command.

(Refer to "Operating Ranges.")

After the completion of the period command input, make sure to set the interval ("L") more than 10 μs until next

start command input.

Example 1) Start command 0xAA and 0xAA setting (original binary 11111111)

Example 2) Period command setting 0x95 and 0x56 (original binary 10000001)

Example) Basic input mode

DATA-IN

2-wire input data

Single wire input data

“1” “0” “0” “0” “0” “0” “0” “1”

HLLHLHLHLHLHLH LH

Start

command

[11111111]

Slave

address Sub address Data byte

Period

command

[10000001]

Start

command

[11111111]

Period

command

[10000001]

L inputL input

Interval more

than 10 µs

“1” “1” “1” “1” “1” “1” “1” “1”

HLHLHLHLHLHLHLHL

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(2) Normal programming mode

Normal programming mode should be set as the following flow.

Start command -> Slave address -> Sub-address -> Data byte -> Period command

Slave address: ID setting of the chip, Sub-address: Output channel setting, Data byte: Data for PWM setting

For each setting data, refer to the descriptions later.

Interval

("L" more than 10 μs

)

Start

Command

Slave

Address

Sub-address

(channel select)

Data byte

(PWM configuration)

Period

Command

Interval

("L" more than 10 μs)

(3) Special programming mode

It is a setting method to set all channels individually.

●Special mode setting (In case all channels are selected in order))

When the special mode is set to the sub-address, the illumination data of all channels can be set.

Special mode setting: 0110100101010101=0x69 and 0x55 (original binary: 01100000)

If it returns to Normal programming mode, input the start command (ALL "H" 8 bits). When this mode setting is

used, the quantity of the data to be set can be reduced.

Interval

("L" more than 10 μs)

Start

command

Slave

Address

Sub-address

(Special mode setting)

Data

OUTR0

Data

OUTG0

Data

OUTB0

Data

OUTR1

Data

OUTG1

Data

OUTB1

Data

OUTR2

Data

OUTG2

Data

OUTB2

Data

OUTR3

Data

OUTG3

Data

OUTB3

Data

OUTR4

Data

OUTG4

Data

OUTB4

Data

OUTR5

Data

OUTG5

Data

OUTB5

Data

OUTR6

Data

OUTG6

Data

OUTB6

Data

OUTR7

Data

OUTG7

Data

OUTB7

Period

command

Please set 24-channel data surely. (In case the data (more than 24 channels) provided the 25th and subsequent

data are treated as invalid.)

PWM

data

DATA-IN Shift register / ID compare/ Channel selection (each channel, 24-channel

continuation, 12 channels × 2-time input, and 6-channel input × 4-time input)

8bit

PWM

data

8bit

PWM

data

8bit

PWM

data

8bit

PWM

data

8bit

PWM

data

8bit

PWM

data

8bit

PWM

data

8bit

PWM

data

8bit

8bit 8bit 8bit 8bit 8bit 8bit8bit 8bit8bit

Constant

current

drive r

Oscillator

Phas e

detection of

single or

two-wire

conversion

ID setting

PWM

counter

Data

compare

Data

compare

Data

compare

Data

compare

Data

Compare

Data

compare

Data

compare

Data

compare

Data

compare

Constant

current

drive r

Constant

current

drive r

Constant

current

drive r

Constant

current

drive r

Constant

current

drive r

Constant

current

drive r

Constant

current

drive r

Constant

current

drive r

8bit

/OUTR0 /OUTG0 /OUTB0 /OUTR1 /OUTG1 /OUTB1 /OUTR2 /OUTG2 /OUTB2

8-bit

counter

CLK

DATA

PWM

data

8bit

PWM

data

8bit

PWM

data

8bit

8bit 8bit 8bit

Data

compare

Data

compare

Data

compare

Constant

current

drive r

Constant

current

drive r

Constant

current

drive r

/OUTR7 /OUTG7 /OUTB7

ID0ID1ID2

DATA-OUT

POR

Vcc

Data reset

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2017-04-18

(4) Dividing programming mode

a) 12-channel programming mode (12ch+12ch=24ch)

If 12-channel mode is set to sub-address, illumination data can be set in the range.

12-channel programming mode (1/2): 0110100101011001=0x69 and 0x59 (original binary: 01100010)

12-channel programming mode (2/2): 0110100101100101=0x69 and 0x65 (original binary: 01100100)

Interval

("L" more than 10 μs)

Start

command

Slave

address

Sub-address

(12ch programming 1/2)

(12ch programming 2/2)

Data

OUTR0

OUTR4

Data

OUTG0

OUTG4

Data

OUTB0

OUTB4

Data

OUTR1

OUTR5

Data

OUTG1

OUTG5

Data

OUTB1

OUTB5

Data

OUTR2

OUTR6

Data

OUTG2

OUTG6

Data

OUTB2

OUTB6

Data

OUTR3

OUTR7

Data

OUTG3

OUTG7

Data

OUTB3

OUTB7

Period

command

b) 6-channel programming mode (6ch+6ch+6ch+6ch=24ch)

If 6-channel mode is set to sub-address, illumination data can be set in the range.

6-channel programming mode (1/4): 0110100101101001=0x69 and 0x69 (original binary:01100110)

6-channel programming mode (2/4): 0110100110010101=0x69 and 0x95 (original binary:01101000)

6-channel programming mode (3/4): 0110100110011001=0x69 and 0x99 (original binary:01101010)

6-channel programming mode (4/4): 0110100110100101=0x69 and 0xA5 (original binary:01101100)

Interval

("L" more than 10 μs)

Start

command

Slave

address

Sub-address

(6ch programming 1/4)

(6ch programming 2/4)

(6ch programming 3/4)

(6ch programming 4/4)

Data

OUTR0

OUTR2

OUTR4

OUTR6

Data

OUTG0

OUTG2

OUTG4

OUTG6

Data

OUTB0

OUTB2

OUTB4

OUTB6

Data

OUTR1

OUTR3

OUTR5

OUTR7

Data

OUTG1

OUTG3

OUTG5

OUTG7

Data

OUTB1

OUTB3

OUTR5

OUTB7

Period

command

(5) Data settings

The start command at the beginning and the period command at the end are shown in the following table.

The slave address, sub-address, and PWM data byte shown below are input to between the start command and

period command.

Original binary

Single wire input

Hexadecimal

Decimal

Start

11111111

1010101010101010

0xAA,0xAA

170,170

Original binary

Single wire input

Hexadecimal

Decimal

Period

10000001

1001010101010110

0x95,0x56

149,86

a) Slave address

Input voltages and logic states of the ID0, ID1, and ID2 pins are determined as follows.

*: Please set it as a pin for one of REXT-R, -G, and -B.

Slave address

ID setting

Original binary

Single wire input

Hexadecimal

Decimal

ID2

ID1

ID0

00000000

0101010101010101

0x55,0x55

85,85

GND

00000010

0101010101011001

0x55,0x59

85,89

GND

REXT-R/G/B*

00000100

0101010101100101

0x55,0x65

85,101

GND

Open

00000110

0101010101101001

0x55,0x69

85,105

GND

Vcc

00001000

0101010110010101

0x55,0x95

85,149

GND

REXT-R/G/B*

GND

00001010

0101010110011001

0x55,0x99

85,153

GND

REXT-R/G/B*

00001100

0101010110100101

0x55,0xA5

85,165

GND

REXT-R/G/B*

Open

00001110

0101010110101001

0x55,0xA9

85,169

GND

REXT-R/G/B*

Vcc

00010000

0101011001010101

0x56,0x55

86,85

GND

Open

GND

00010010

0101011001011001

0x56,0x59

86,89

GND

Open

REXT-R/G/B*

00010100

0101011001100101

0x56,0x65

86,101

GND

Open

00010110

0101011001101001

0x56,0x69

86,105

GND

Open

Vcc

TB62D787FTG

2017-04-18

a) Slave address (continues) **: The original binary number of all the selections is defined as x = 0.

Slave address

ID setting

Original binary

Single wire input

Hexadecimal

Decimal

ID2

ID1

ID0

00011000

0101011010010101

0x56,0x95

86,149

GND

Vcc

GND

00011010

0101011010011001

0x56,0x99

86,153

GND

Vcc

REXT-R/G/B*

00011100

0101011010100101

0x56,0xA5

86,165

GND

Vcc

Open

00011110

0101011010101001

0x56,0xA9

86,169

GND

Vcc

00100000

0101100101010101

0x59,0x55

89,85

REXT-R/G/B*

GND

00100010

0101100101011001

0x59,0x59

89,89

REXT-R/G/B*

GND

REXT-R/G/B*

00100100

0101100101100101

0x59,0x65

89,101

REXT-R/G/B*

GND

Open

00100110

0101100101101001

0x59,0x69

89,105

REXT-R/G/B*

GND

Vcc

00101000

0101100110010101

0x59,0x95

89,149

REXT-R/G/B*

GND

00101010

0101100110011001

0x59,0x99

89,153

REXT-R/G/B*

00101100

0101100110100101

0x59,0xA5

89,165

REXT-R/G/B*

Open

00101110

0101100110101001

0x59,0xA9

89,169

REXT-R/G/B*

Vcc

00110000

0101101001010101

0x5A,0x55

90,85

REXT-R/G/B*

Open

GND

00110010

0101101001011001

0x5A,0x59

90,89

REXT-R/G/B*

Open

REXT-R/G/B*

00110100

0101101001100101

0x5A,0x65

90,101

REXT-R/G/B*

Open

00110110

0101101001101001

0x5A,0x69

90,105

REXT-R/G/B*

Open

Vcc

00111000

0101101010010101

0x5A,0x95

90,149

REXT-R/G/B*

Vcc

GND

00111010

0101101010011001

0x5A,0x99

90,153

REXT-R/G/B*

Vcc

REXT-R/G/B*

00111100

0101101010100101

0x5A,0xA5

90,165

REXT-R/G/B*

Vcc

Open

00111110

0101101010101001

0x5A,0xA9

90,169

REXT-R/G/B*

Vcc

01000000

0110010101010101

0x65,0x55

101,85

Open

GND

01000010

0110010101011001

0x65,0x59

101,89

Open

GND

REXT-R/G/B*

01000100

0110010101100101

0x65,0x65

101,101

Open

GND

Open

01000110

0110010101101001

0x65,0x69

101,105

Open

GND

Vcc

01001000

0110010110010101

0x65,0x95

101,149

Open

REXT-R/G/B*

GND

01001010

0110010110011001

0x65,0x99

101,153

Open

REXT-R/G/B*

01001100

0110010110100101

0x65,0xA5

101,165

Open

REXT-R/G/B*

Open

01001110

0110010110101001

0x65,0xA9

101,169

Open

REXT-R/G/B*

Vcc

01010000

0110011001010101

0x66,0x55

102,85

Open

GND

01010010

0110011001011001

0x66,0x59

102,89

Open

REXT-R/G/B*

01010100

0110011001100101

0x66,0x65

102,101

Open

01010110

0110011001101001

0x66,0x69

102,105

Open

Vcc

01011000

0110011010010101

0x66,0x95

102,149

Open

Vcc

GND

01011010

0110011010011001

0x66,0x99

102,153

Open

Vcc

REXT-R/G/B*

01011100

0110011010100101

0x66,0xA5

102,165

Open

Vcc

Open

01011110

0110011010101001

0x66,0xA9

102,169

Open

Vcc

01100000

0110100101010101

0x69,0x55

105,85

Vcc

GND

01100010

0110100101011001

0x69,0x59

105,89

Vcc

GND

REXT-R/G/B*

01100100

0110100101100101

0x69,0x65

105,101

Vcc

GND

Open

01100110

0110100101101001

0x69,0x69

105,105

Vcc

GND

Vcc

01101000

0110100110010101

0x69,0x95

105,149

Vcc

REXT-R/G/B*

GND

01101010

0110100110011001

0x69,0x99

105,153

Vcc

REXT-R/G/B*

01101100

0110100110100101

0x69,0xA5

105,165

Vcc

REXT-R/G/B*

Open

01101110

0110100110101001

0x69,0xA9

105,169

Vcc

REXT-R/G/B*

Vcc

01110000

0110101001010101

0x6A,0x55

106,85

Vcc

Open

GND

01110010

0110101001011001

0x6A,0x59

106,89

Vcc

Open

REXT-R/G/B*

01110100

0110101001100101

0x6A,0x65

106,101

Vcc

Open

01110110

0110101001101001

0x6A,0x69

106,105

Vcc

Open

Vcc

01111000

0110101010010101

0x6A,0x95

106,149

Vcc

GND

01111010

0110101010011001

0x6A,0x99

106,153

Vcc

REXT-R/G/B*

01111100

0110101010100101

0x6A,0xA5

106,165

Vcc

Open

01111110

0110101010101001

0x6A,0xA9

106,169

Vcc

0XXXXXX1

0101010101010110

0x55,0x56

85,86

All select

TB62D787FTG

2017-04-18

b) Sub-address Output channels, all channels selection, special programming mode, 6-channel programming

mode, or 12-channel programming mode can be set.

Sub-address

LED output

Target setting of PWM

data

Original binary

Single wire input

Hexadecimal

Decimal

00000010

0101010101011001

0x55,0x59

85,89

/OUTR0

One channel is set

separately.

00000100

0101010101100101

0x55,0x65

85,101

/OUTG0

00000110

0101010101101001

0x55,0x69

85,105

/OUTB0

00001000

0101010110010101

0x55,0x95

85,149

/OUTR1

00001010

0101010110011001

0x55,0x99

85,153

/OUTG1

00001100

0101010110100101

0x55,0xA5

85,165

/OUTB1

00001110

0101010110101001

0x55,0xA9

85,169

/OUTR2

00010000

0101011001010101

0x56,0x55

86,85

/OUTG2

00010010

0101011001011001

0x56,0x59

86,89

/OUTB2

00010100

0101011001100101

0x56,0x65

86,101

/OUTR3

00010110

0101011001101001

0x56,0x69

86,105

/OUTG3

00011000

0101011010010101

0x56,0x95

86,149

/OUTB3

00011010

0101011010011001

0x56,0x99

86,153

/OUTR4

00011100

0101011010100101

0x56,0xA5

86,165

/OUTG4

00011110

0101011010101001

0x56,0xA9

86,169

/OUTB4

00100000

0101100101010101

0x59,0x55

89,85

/OUTR5

00100010

0101100101011001

0x59,0x59

89,89

/OUTG5

00100100

0101100101100101

0x59,0x65

89,101

/OUTB5

00100110

0101100101101001

0x59,0x69

89,105

/OUTR6

00101000

0101100110010101

0x59,0x95

89,149

/OUTG6

00101010

0101100110011001

0x59,0x99

89,153

/OUTB6

00101100

0101100110100101

0x59,0xA5

89,165

/OUTR7

00101110

0101100110101001

0x59,0xA9

89,169

/OUTG7

00110000

0101101001010101

0x5A,0x55

90,85

/OUTB7

01000000 0110010101010101 0x65,0x55 101,85 All channel select

All 24 channels are set

as same.

01100000 0110100101010101 0x69,0x55 105,85

Special

programming mode

24 channels are set at

one time.

01100010 0110100101011001 0x69,0x59 105,89

12-channel

programming mode (1/2)

12 channels are set at

two times.

01100100 0110100101100101 0x69,0x65 105,101

12-channel

programming mode (2/2)

01100110 0110100101101001 0x69,0x69 105,105

6-channel

programming mode (1/4)

6 channels are set at

four times.

01101000 0110100110010101 0x69,0x95 105,149

6-channel

programming mode (2/4)

01101010 0110100110011001 0x69,0x99 105,153

6-channel

programming mode (3/4)

01101100 0110100110100101 0x69,0xA5 105,165

6-channel

programming mode (4/4)

TB62D787FTG

2017-04-18

c) Data byte Data bytes set PWM dimming data.

PWM data byte

PWM dimming

Note

Original binary

Single wire input

Hexadecimal

Decimal

00000000

0101010101010101

0x55,0x55

85,85

0/127

The initial state is

set to

0/127 and is always

OFF state.

As the original binary

set "0" to LSB, and

not set "1."

127/127 is

always ON

state.

00000010

0101010101011001

0x55,0x59

85,89

1/127

00000100

0101010101100101

0x55,0x65

85,101

2/127

00000110

0101010101101001

0x55,0x69

85,105

3/127

00001000

0101010110010101

0x55,0x95

85,149

4/127

00001010

0101010110011001

0x55,0x99

85,153

5/127

00001100

0101010110100101

0x55,0xA5

85,165

6/127

00001110

0101010110101001

0x55,0xA9

85,169

7/127

00010000

0101011001010101

0x56,0x55

86,85

8/127

—

00011110

0101011010101001

0x56,0xA9

86,169

15/127

00100000

0101100101010101

0x59,0x55

89,85

16/127

—

00101110

0101100110101001

0x59,0xA9

89,169

23/127

00110000

0101101001010101

0x5A,0x55

90,85

24/127

—

00111110

0101101010101001

0x5A,0xA9

90,169

31/127

01000000

0110010101010101

0x65,0x55

101,85

32/127

—

01001110

0110010110101001

0x65,0xA9

101,169

39/127

01010000

0110011001010101

0x66,0x55

102,85

40/127

—

01011110

0110011010101001

0x66,0xA9

102,169

47/127

01100000

0110100101010101

0x69,0x55

105,85

48/127

—

01101110

0110100110101001

0x69,0xA9

105,169

55/127

01110000

0110101001010101

0x6A,0x55

106,85

56/127

—

01111110

0110101010101001

0x6A,0xA9

106,169

63/127

10000000

1001010101010101

0x95,0x55

149,85

64/127

—

10001110

1001010110101001

0x95,0xa9

149,169

71/127

10010000

1001011001010101

0x96,0x55

150,85

72/127

—

10011110

1001011010101001

0x96,0xa9

150,169

79/127

10100000

1001100101010101

0x99,0x55

153,85

80/127

—

10101110

1001100110101001

0x99,0xa9

153,169

87/127

10110000

1001101001010101

0x9a,0x55

154,85

88/127

—

10111110

1001101010101001

0x9a,0xa9

154,169

95/127

11000000

1010010101010101

0xa5,0x55

165,85

96/127

—

11001110

1010010110101001

0xa5,0xa9

165,169

103/127

11010000

1010011001010101

0xa6,0x55

166,85

104/127

—

11011110

1010011010101001

0xa6,0xa9

166,169

111/127

11100000

1010100101010101

0xa9,0x55

169,85

112/127

—

11101110

1010100110101001

0xa9,0xa9

169,169

119/127

11110000

1010101001010101

0xaa,0x55

170,85

120/127

—

11111110

1010101010101001

0xAA,0xA9

170,169

127/127

TB62D787FTG

2017-04-18

(6) Notes of data setting

This product has the specification of data recognition or processing with only a data signal (asynchronous input

signal). The data period (communication speed) is learned with the start command (data input start condition).

Data are recognized according to this learning period, and are stored to the internal register after the period

command (a condition of data input completion). Therefore, the data are not recognized if the data period is

collapsed between the start command and the period command (see the following a)). Then the period learned

during an interval period is reset and it waits for next communication.

a) Learning data period

b) Data recognition

The duty of H/L pulse width to input to this product should be set within ±10％ as shown below.

If the duty is out of this range, data cannot be recognized correctly. (Refer to the following "Operating Ranges.")

St art command Slave address

(ID)

Sub-addr ess

(Communicat ion mode)

Data byte

(Illuminating data)

Data byte

(Illuminating data)Period command

In terval

L fixed at more

than 10 μs

After the

recognition of the

period comma nd,

the data byte is

stored to the

inte rna l re gister

whe n the internal

co unter counts

zero.

The communication data is recogn ized

based on the period and phase learned

during the start command period.

After learning, Data are not recogni zed if th e int ervals an d

phases are changed compared with the learned result

between the slave address and period command.

(such as the disturbance of transfer periodicity caused by a

disturbance noise or a microcontroller)

The period and

phase of the

communication

data is learned

during the start

command period.

0％50％100％

50±10%If there is a reversal of data polarity

in this period, communication data

can be recognized.

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2017-04-18

<Reference: Example of control data input>

(7) Example of basic data input to the same ID

When data is input to the same ID, next data should be input at the interval of 3 ms or more (128 times of internal

PWM clocks) regardless of same or change of sub-address at last input. If the setting to the same channel is

overlapped, PWM control cannot perform correctly.

If data is input to other slave address, it is not necessary.

The following from a) to e) corresponds to them if a sub-address is in each output channel, all channels select or

special programming mode.

Refer to f) to g) if a sub-address is in 6-channel programming mode or 12-channel programming mode.

a) In case DATA "A" is input up to the rising edge of 127 internal PWM clocks.

Output DATA "A" starts at the rising edge of zero internal PWM clocks.

Inputting is invalid from the rising edge of 127 internal PWM clocks to the rising edge of zero internal PWM clocks

which are just after these 127 PWM clocks.

b) In case DATA "A" is input after the rising edge of 127 internal PWM clocks.

DATA "A" cannot be transferred at the rising edge of 127 internal PWM clocks just after inputting DATA "A."

Therefore, DATA "A" starts an output at the rising edge of zero PWM clocks, after passing the rising edge of next

127 internal PWM clocks.

The input invalid period is the period to the rising edge of internal PWM clock 0 of which DATA "A" starts to output.

c) In case DATA "B" is input after starting the output of pattern 1

DATA "A" starts an output at the rising edge of zero internal PWM clocks just after DATA "A" period. Then DATA

"B" starts an output at rising edge of zero internal PWM clocks just after DATA "B" period.

The input invalid period is the period from the rising edge of 127 internal PWM clocks just after the period input to

the rising edge of zero internal PWM clocks.

STA RT DATA ”A” PERIOD

Pattern 1

Internal PWM

clock

Transferring DA TA “A”

127

126125 0127 0

Reflecti ng LED output

Input invalid

per io d

DATA "A” starts to output

STA RT DATA “A” PERIOD

Pattern 2

Internal PWM clock

Transferring

DATA “A”

127

126125 0127 0

Reflecti ng

LED output

Input invalid

per io d

DATA “A” starts to output

PERIOD ends

a fte r 127 clocks

STA RT DATA “A” PERIOD

Pattern 3

Internal PWM clock

Transferring

DATA “A”

127

126125 0127 0

Reflecti ng

LED output

Input invalid

per io d

DATA “A” starts to output

STA RT DATA “B” PERIOD

Input invalid

per io d

Transferring

DATA “B”

Reflecti ng

LED output

DATA “B” starts

to output

126

TB62D787FTG

2017-04-18

Pay attention that the IC does not operate according to the configuration while the following patterns (patterns 4

and 5) are input.

d) In case DATA "B" is input before DATA "A" starts output

The period between DATA "A" period end and the second rising edge of zero internal PWM clocks is the input

invalid period. Therefore, DATA "B" is invalid and DATA "A" is output.

e) In case the period command of DATA "A" is not recognized

When the period of DATA "A" is not input and the period of next DATA "B" is input, DATA "B" starts output immediately

after at the rising edge of zero internal PWM clocks.

STA RT DATA “A” PERIOD

Pattern 4

Internal PWM

clock

127

126125 0127 0

Input invalid

per io d STA RT DATA “B” PERIOD

Transferring DA TA “A” Reflecting LED

output

DATA “A”

starts to

output

126

DATA “B” is invalid because

DATA ”A“ bec omes latest data.

STA RT DATA “A” ─

Pattern 5

Internal PWM

clock

127

126

125 0127 0

Input invalid

per io d

STA RT DATA “B” PERIOD

Transferring DA TA “B” Reflecti ng

LED output

DATA “B”

starts to

output.

126

DATA “B” becomes latest data.

DATA “A” is invalid data because

PERIOD is not input.

PERIOD is

not input.

Not transferring because

PERIOD is not input.

TB62D787FTG

2017-04-18

f) 6-channel programming mode / 12-channel programming mode

When a 6-channel programming mode group (1/4 -> 2/4 -> 3/4 -> 4/4) or 12-channel programming mode

group (1/2-> 2/2) is input continuously in order, the interval of 3 ms or more is not necessary.

However when same IDs and same channel data in 6 or 12-channel programming mode are input, the interval of

3 ms or more is necessary. PWM control may not be performed correctly.

Since there is no input invalid period, an input data are started to output at the rising edge of the first zero internal

PWM clocks after inputting the period command.

Therefore, when other programming mode is input immediately after 6-channel or 12-channel programming, the

6-channel or 12-channel programming data immediately before are re-written to the data input in other

programming mode.

When 6-channel or 12-channel programming is used, 24-channel units of input are recommended.

STA RT DATA ”A” PERIOD

Pattern 6

Internal PWM clock 127

126125 0127 0

Transferring DA TA “A”

Reflecti ng LED output

DATA “A” output

starts

DATA "A" in 12-channel

pro g ra mm ing mode

STA RT DATA “A” PERIOD

Pattern 7

Internal PWM clock 127

126125 0127 0

Transferring DA TA “A”

Reflecti ng LED output

DATA “A” starts to output.

STA RT DATA “B” PERIOD

DATA “B” starts

to output.

126

DATA "A" in 12-channel

pro g ra mm ing mode

DATA “B” in 12-channel input mode

STA RT DATA “A” PERIODPattern 8

Internal PWM clock 127

126125 0127 0

STA RT DATA “B” PERIOD

126

Transferring DA TA “B”

Reflecti ng LED output

Transferring DA TA “A”

Reflecti ng LED output

Transferring DA TA “B”

Reflecti ng LED output

DATA “A” starts to output.

DATA “B” starts

to output .

DATA "A" in 12-channel

pro g ra mm ing mode DATA “B” in 12-channel input mode

STA RT DATA ”A” PERIOD

Pattern 9

Internal PWM clock 127

126125 0127 0

STA RT DATA ”C” PERIOD

126

Transferring DA TA “A”

Reflecti ng LED output Reflecti ng

LED output

DATA “A” starts

to output

DATA “C” starts

to output

DATA "A" in 6- or 12-

channel input mode DATA "C" is not in 6- or

12-channel input mode

Transferring DA TA “C”

TB62D787FTG

2017-04-18

g) In case the period command mistakes

DATA "B" starts to output at the rising edge of zero internal PWM clocks if the period of DATA "A" is not input and

the period of next DATA "B" is input.

STA RT DATA “A” ─

Pattern 10

Internal PWM

clock

127

126125 0127 0

STA RT DATA “B” PERIOD

DATA “B” starts to

output.

126

PERIOD

is not

input.

Not transferring because

PERIOD is not input.

DATA "A” of 6 / 12-

channel programming

DATA "B” of 6 / 12-

channel programming

Transferring DA TA “B”

Reflecti ng LED output

STA RT DATA “B” PERIOD

DATA “B” becomes latest data and

DATA “A” is invalid because PERIOD

is not input.

6- or 12-channel input

mode pe rf orm s a data

transfer and an output

start when the internal

PWM clock is zero.

STA RT DATA “A” ─

Pattern 11

PERIOD

is not

input.

DATA "A” of 6 / 12-

channel programming

DATA "B” of 6 / 12-

channel programming

TB62D787FTG

2017-04-18

(8) Example of basic data input to the different ID.

a) In case DATA "B" is input to slave (= 02h) just after DATA "A" is input to slave (= 00h).

Both DATA "A" and DATA "B" are output at the rising edge of zero internal PWM clock which is just after DATA "A"

and DATA "B" inputs.

Pay attention that the IC does not operate according to the configuration while following patterns (patterns 13 and

14) are input.

b) In case period command after inputting DATA "A" to the slave (= 00h) is missed or omitted.

In case period command after inputting DATA "B" to the slave (= 02h) is missed or omitted.

DATA "A" is output. DATA "B" is not output.

c) In case start command is input after DATA "B" of pattern 13 is input.

DATA "A" is output. DATA "B" is not output.

STA RT SL AVE #00h,DATA ”A” PERIOD

Pattern 12

Internal PWM clock 127 0

STA RT SL AVE #02h,DATA ”B”

Transferring DA TA “A” a n d “B”

(Exce pt 6- or 12 channel mode)Reflecting

LED output

DATA "A” starts to

output

126

PERIOD

SL AVE #00h output

DATA "B” starts to

output

SL AVE #02h output

STA RT SL AVE #00h,DATA ”A” Miss (omit )

Pattern 13

Internal PWM clock 127 0

STA RT SL AVE #02h,DATA ”B”

Transferring DA TA “A”

(Exce pt 6- or 12-channel mode)Reflecti ng

LED output

DATA "A" starts to

output

126

SL AVE #00h output

SL AVE #02h output

Miss (omit )

STA RT SL AVE #00h,DATA ”A” Miss (omit )

Pattern 14

Internal PWM clock 127 0

STA RT SL AVE #02h,DATA ”B”

Transferring DA TA “A”

(Exce pt 6- or 12-channel mode)

Reflecti ng

LED output

DATA "A" starts to

output

126

SL AVE #00h output

SL AVE #02h output

STA RT

Miss (omit )

TB62D787FTG

2017-04-18

Power Supply Block

The power supply of this product can be set with the following 2 ways shown in (1) and (2).

(1) When the power supply of LEDs and those of this product are shared (The power supply function of this product

is used.)

(2) When this product is operated with 5 V power supply input, not sharing the power supply of LEDs (The power

supply function of this product is not used.)

Each settings are shown below.

(1) When the power supply of LEDs and those of this product are shared

As shown in the above, the power supply (7.0 to 28 V) is applied to the VL pin, and VOUT and Vcc pins are

connected directly.

VLOUT pin output (5 V) should be connected within 15 mA dc (@ all LED outputs 40 mA) except connecting to Vcc

of own product.

(2) When 5 V power supply is input to Vcc pin directly

When 5 V power supply is applied to this product without using the built-in power supply, ground VL pin and VLOUT

pin to GND.

Note: Add decoupling capacitors to VL pin and Vcc pin. The recommended values are as follows.

Recommended value of decoupling capacitors between VL (LED power supply) and GND: 1μF of electrolytic

capacitor

*: Evaluate appropriately since it is dependent on the main power supply performance.

Recommended value of decoupling capacitors between Vcc (5 V power supply) and GND: 1μF of electrolytic

capacitor and 0.1μF of ceramic capacitor

*: Evaluate appropriately since it is dependent on the LED current to be set and current supply amount of

VLOUT.

5 V control circuit

Linear

regulator

GND LED

VLOUT

Vcc

(5.0 V)

LED power

supply

5 V control circuit

Linear

regulator

GND LED

VLOUT

Vcc

(5.0 V)

LED power supply

5 V power supply

TB62D787FTG

2017-04-18

Data buffer

Data buffer is built in between DATA-IN and DATA-OUT, and it can be used for the cascade connection of two or

more these products.

In the case of cascade connection with this buffer, connect up to 5 pieces (@2MHz communication) on the same

board.

Power on reset (POR)

It avoids the malfunction by the reset all internal data of IC and setting default in startup.

POR circuit operates only when VDD rises from 0 V. To restart POR, Vcc should be 0 V.

As for the voltage of storing the internal data, it is guaranteed after Vcc reaches 4.5 V or more once.

DATA

MCU

TB62D787FTG

DATA-IN

DATA-OUT

DATA-IN

DATA-OUT

DATA-IN

２.0 V

1.8 V

0 V

Vcc waveform

Reset voltage

Lower limit

voltage for

guaranteed data

End of POR

POR working range POR working range

Beyond P OR working range

Initia l clear

TB62D787FTG

2017-04-18

Thermal shutdown function (TSD)

When the temperature of internal IC exceeds 150°C, all constant current outputs are turned off by this function.

The constant current is output again when the temperature decreases to the rating.

TSD operation temperature 150°C to 180°C

TSD reset temperature -20°C from TSD operation temperature

Note: TSD function aims at detecting abnormal heating of ICs. Please avoid positively using the TSD function.

Notes of setting

1. Output load

This product is the driver in which loads are LEDs. Do not connect loads except LEDs to the output.

2. External resistor for LED drive current setting (REXT-R, REXT-G, and REXT-B)

The external resistances to be connected to REXT-R, REXT-G, and REXT-B pins should be connected separately.

Three pins should not be shared as one pin. The current error may occur in each RGB.

3. Operation sequence of ID setting

The ID setting can be available when Vcc exceeds 4.5 V after turning on.

However, in order to prevent malfunction of the ID setting, the transitional input signals of less than 2-clock

period of external input data (DATA-IN) are not received.

4. Data setting

The gradation signals should be input data for 24 channels in the special mode certainly.

When the data are input to over 24 channels, the data until the input channel are held and the data in 25th

channel are invalid.

When the data are input to less than 24 channels, the data of channels to be input are held, and the data of

channels not to be input are held data before the input.

The gradation signals should be input data for specified channels in 6- or 12-channel programming mode.

When the data are input to over specified channels, the data until input channel are held and the data over

specified channels are invalid.

When the data input to less than specified channels, the data of channels to be input are held, and the data of

channels not to be input are held data before the input.

Moreover, do not input data which are not indicated in this document.

Confirm "Programming the TB62D787FTG" and "(6) Notes of data setting."

5. Data setting timing

When data are input to same slave address, next data should be input with spacing the interval 3 ms or more

(128 internal PWM clocks) because data may not be received.

When data are input to different slave address, the interval 3 ms (128 internal PWM clocks) or more is not

required.

6. Decoupling capacitor

For the stabilization of power supply system, it is recommended that decoupling capacitor between power supply

and GND should place as near IC as possible. For details, refer to "Power Supply Block."

Vcc waveform

4.5 V4.5 V

Not available range of ID

set ting

Available range of ID setting

Not available range of ID

set ting

TB62D787FTG

2017-04-18

State Transition Diagram

VLOUT pin and Vcc pin are wire-connected beforehand, and set each IC's ID (from ID0 to ID2 pin).

VLOUT pin and VCC pin are wire-connected to GND beforehand, and set each IC's ID (from ID0 to ID2 pin).

Turning on power supply (VL pin)

VCC pin voltag e reaches 4.5 V or more.

VLOUT pin supplies IC operation voltage (more than 4.5 V).

ID recognition

Data should be input

after VCC voltage reaches 4.5 V an d more,

and minimum 15 ms passes.

Normal mode

Th e PWM data of each output is

updated for every ID set by the

DATA signals, and LED

illuminating is controlled.

TSD

(The rmal ShutDown )

mode

All LED outputs are forced to OFF

if the TSD detection temperature

has reached.

Internal data are held.

More than TSD

detecting

temperature

Less than TSD

detecting

temperature

rang e

VCC pin voltag e reaches 4.5 V or more.

Turning on IC power supply (VCC pin)

ID recognition

Data should be input

after VCC voltage reaches 4.5 V and more,

and minimum 15 ms passes.

Normal mode

Th e PWM data of each output is

updated for every ID set by the

DATA signals, and LED

illuminating is controlled.

TSD

(The rmal Shut Down)

mode

All LED outputs are forced to OFF

if the TSD detection temperature

has reached.

Internal data are held.

More than TSD

detecting

temperature

Less than TSD

detecting

temperature

rang e

TB62D787FTG

2017-04-18

Absolute Maximum Ratings (Ta=25°C)

Characteristics Symbol Rating Unit

VL pin power supply voltage VL 29 V

Vcc pin power supply voltage Vcc 6.0 V

Input voltage V

-0.3 to 6.0 V

Output current IOUT 85 (Note 3) mA/ch

Output voltage V

OUT

-0.3 to 29 V

Power dissipation

4.3 (Note 1)(Note 2) W

Thermal resistance

th (j-a)

29.1 (Note 1) °C/W

Operating Temperature Rating Topr -40 to 85 °C

Storage Temperature Rating T

stg

-55 to 150 °C

Maximum junction Temperature T

150 °C

Note 1: When mounted on a PCB (Board size: 76.2×114.3×1.6mm, Cu=30%, 35µm thickness, Compliant with

SEMI, 4 layers)

Note 2: Power dissipation is reduced by 1/ Rth(j-a) for each °C above 25°C ambient.

Note 3: Current may be further restricted due to ambient temperature or board condition.

Ta: Ambient temperature of ICs

Topr: Ambient temperature of ICs to be operated

Tj: IC chip temperature during operating

For the design, it is recommended that the maximum of Tj is considered of the amount of use dissipation at

about 120°C.

Power Dissipation of package

025 85 150

4.3

Saturation thermal resistance: 29.1°C/W

Power dissipation: 4.3 W

Maximum operating temperature: 85°C

Maximum junction temperature: 150°C

Ambient temperature (T

opr

)(°C)

Power dissipation

(Pd)(W)

TB62D787FTG

2017-04-18

Operating Ranges (Ta=-40 to 85°C, unless otherwise specified)

Characteristics Symbol Test Condition Min Typ. Max Unit

VL pin power supply voltage VL — 7.0 — 28 V

Vcc pin power supply voltage Vcc — 4.5 — 5.5 V

Output voltage V

OUT(ON)

All outputs 0.5 — 4 V

Output current IOUT All outputs 5 — 40 mA/ch

Input DATA Frequency Fin — 0.5 — 2.0 MHz

Input DATA Duty Fin(duty) — 40 50 60 ％

Input Voltage

VIH

DATA-IN

0.7 ×

Vcc — Vcc

VIL GND — 0.3 ×

Vcc

ID0

ID0, ID1, ID2

0 — 0.1

VID1 VREXT

-0.1 VREXT VREXT

+0.1

VID2 Vcc

-0.1 — Vcc

VLOUT load current ΔVl Except Supply current

LED current setting is up to 40 mA.

— — 15 mA

TB62D787FTG

2017-04-18

Electrical Characteristics (Ta=25°C, VL=15V, VCC=VLOUT, Unless otherwise specified)

Characteristics Symbol Test Condition Min Typ. Max Unit

Output current IOUT1 VOUT = 0.5 V, REXT = 1.2 kΩ 12.5 13.3 14.1 mA

Output current accuracy between

channels ∆IOUT2 VOUT = 0.5 V, REXT = 1.2 kΩ

All output ON — — ±3.0 %

Output leakage current I

OUT

= 28 V — — 1 μA

VLOUT pin voltage VLOUT — 4.5 — 5.5 V

Input current

IIH DATA-IN — — 1

μA

DATA-IN — — -1

IID ID0, ID1, ID2 — — ±10

Output current dependent on Vcc %/Vcc When changed Vcc = 4.5 V to 5.5 V

— 1 2 %

Power supply current in operation

Icc (VL) When applied VL=15 V

REXT = 1.2 kΩ, V

OUT

= 0.5 V, — 12 19

Icc (Vcc) When connected VL=GND

REXT = 1.2 kΩ, V

OUT

= 0.5 V, — 11.5 16

H Level DATA-OUT pin

Output Voltage VOH IOH= -1 mA Vcc

-0.4 — — V

L Level DATA-OUT pin

Output Voltage VOL IOL= 1 mA — — 0.4 V

DATA-IN–DATA-OUT

Propagation Delay Time (Note)

tpLH

CL = 15 pF, tf = tf = 3 ns

— — 20

tpHL — — 20

PWM reference frequency fPWM Reference frequency of internal

PWM counter — 70 — kHz

Note: DATA-IN – DATA-OUT definition

DATA-IN

DATA-OUT

90%90%

50%50%

10%10%

tr tf

50%50%

tpLH

tpHL

TB62D787FTG

2017-04-18

Test Circuit

Test Circuit 1 Input Current (IIH)

Test Circuit 2 Input Current (IIL)

Test Circuit 3 Supply Current (VL)

VLVLOUT

Vcc

DATA-IN

ID0,1,2

REXT-R REXT-G REXT-B GND

PGND

OUTR0

OUTB7

VLVLOUTVcc

DATA-IN

ID0,1,2

REXT-R REXT-G REXT-B GND

PGND

OUTR0

OUTB7

VLVLOUTVcc

VIH=Vcc

VIL=GND

ID0

REXT-R REXT-G REXT-B GND

PGND

OUTR0

OUTB7

F.G

setting ID1

ID2

ID0=0.1V

ID1=V(REXT)±0.1V

ID2=Vcc-0.1V

REXT=1.2kΩ

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Test Circuit 4 Supply Current (Vcc)

Test Circuit5 Output Current / Output Leakage Current / Output Current Accuracy / Changes in Constant Output

current dependent on Vcc

VLVLOUTVcc

VIH=Vcc

VIL=GND

ID0

REXT-R REXT-G REXT-B GND

PGND

OUTR0

OUTB7

F.G

setting ID1

ID2

ID0=0.1V

ID1=V(REXT)±0.1V

ID2=Vcc-0.1V

REXT=1.2kΩ

Vcc

VLVLOUTVcc

VIH=Vcc

VIL=GND

ID0

REXT-R REXT-G REXT-B GND

PGND

OUTR0

OUTB7

F.G

setting ID1

ID2

ID0=0.1V

ID1=V(REXT)±0.1V

ID2=Vcc-0.1V

REXT=1.2kΩ

Vcc

VOUT

=0.5V, 28V

TB62D787FTG

2017-04-18

Output current - derating (illuminating rate) graph

Board condition: 76.2×114.3×1.6 mm, Cu=30%, 35 µm thickness, compliant with SEMI

When the pulse width is 25 ms or more, it is regarded as DC.

Output current - external resistance characteristic (typ.)

010 20 30 40 50 60 70 80 90 100

IOUT (mA)

Duty -turn on rate (%)

IOUT -Duty

Ta=85℃

VL=15V / 28V

VDS=1.0V

On PCB (4

-Layer)

24ch ON

VL=28V

VL=15V

010 20 30 40 50 60 70 80 90 100

IOUT (mA)

Duty -turn on rate (%)

IOUT -Duty

Ta=25℃

VL=15V / 28V

VDS=1.0V

On PCB (4

-Layer)

24ch ON

VL=15V

VL=28V

010 20 30 40 50 60 70 80 90 100

IOUT (mA)

Duty -turn on rate (%)

IOUT -Duty

Ta=55℃

VL=15V / 28V

VDS=1.0V

On PCB (4

-Layer)

24ch ON

VL=28V

VL=15V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

IOUT (mA)

REXT (kΩ)

IOUT -REXT

IOUT=1.128(V)／REXT(Ω)*14.18

010 20 30 40 50 60 70 80 90 100

IOUT (mA)

Duty -turn on rate (%)

IOUT -Duty

Ta=85℃

VL=0V,

VLOUT=0V

VCC=4.5 to 5.5V

VDS=1.0V

On PCB (4

-Layer)

24ch ON

VL=28V

VL=15V

Unused linear regulator

TB62D787FTG

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Application circuit 1

MCU

VLED

TB62D787FTG TB62D787FTG

GND

DATA-IN

/OUTR0

/OUTB7

DATA-IN

/OUTR0

/OUTB7

ID0

ID1

ID2

DATA

ID1

ID0

LED power supply

REXT-R

REXT-G

VLOUT

GND

REXT-B

Vcc

REXT-R

VLOUT

REXT-G

Vcc

REXT-B

DATA-OUT

TB62D787FTG

2017-04-18

Application circuit 2

When it controls from the same ports of TB62D612FTG, which is 2-wire input control LED driver and the MCU, connect

the Exclusive-OR gate (TC74VHC86) and D-Flip/Flop to preceding phase of the input of this product as shown below.

At this time, the DATA and CLOCK of the interval period should be set to High level.

Since phase differences between DATA from MCU outputting and clock may occur, confirm the operation enough with

the following configuration.

●System configuration

●Logic

●Timing charts

Note: When this circuit is used, the interval period should be fixed to SDA=SCLK=High.

Composite circuit from two wire to single wire

MCU

TC74

VHC86

7WH74

TB62D787FTG

TB62D612FTG

2-wire input

Single wire

input

SCLK

SDA

DATA-IN

Logic

SCLK(1.5MHz)

SDA

EX-OR

CR delay U3(10)

XOR U3(8)

XOR U4(11)

DATA-IN U5(5)

TB62D787FTG

2017-04-18

Package Dimensions

P-VQFN40-0606-0.50-001

Unit: mm

Weight: 0.097g (Typ.)

TB62D787FTG

2017-04-18

Notes of Contents

1. Block diagram

Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for

explanatory purposes.

2. Equivalent circuits

The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory

purposes.

3. Timing charts

Timing charts may be simplified for explanatory purposes.

4. Application circuits

The application circuits shown in this document are provided for reference purposes only. Thorough evaluation

is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial

property rights by providing these examples of application circuits.

5. Test circuits

Components in the test circuits are used only to obtain and confirm the device characteristics. These components

and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment.

IC Usage Considerations

Notes on handling of ICs

(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded,

even for a moment. Do not exceed any of these ratings.

Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury

by explosion or combustion.

(2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of

over current and/or IC failure. The IC will fully break down when used under conditions that exceed its

absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs

from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or

ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings,

such as fuse capacity, fusing time and insertion circuit location, are required.

(3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design

to prevent device malfunction or breakdown caused by the current resulting from the inrush current at

power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown

may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If

the power supply is unstable, the protection function may not operate, causing IC breakdown. IC

breakdown may cause injury, smoke or ignition.

(4) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative

terminals of power supplies are connected properly. Otherwise, the current or power consumption may

exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown,

damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any

device that is applied the current with inserting in the wrong orientation or incorrectly even just one time.

(5) Carefully select external components (such as inputs and negative feedback capacitors) and load

components (such as speakers), for example, power amp and regulator.

If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC

voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage,

overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from

the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that

inputs output DC voltage to a speaker directly.

TB62D787FTG

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Points to remember on handling of ICs

(1) Heat Radiation Design

In using an IC with large current flow such as power amp, regulator or driver, please design the device so

that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and

condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead

to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the

device taking into considerate the effect of IC heat radiation with peripheral components.

(2) Back-EMF

When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the

motor's power supply due to the effect of back-EMF. If the current sink capability of the power supply is small,

the device's motor power supply and output pins might be exposed to conditions beyond absolute maximum

ratings. To avoid this problem, take the effect of back-EMF into consideration in system design.

(3) Thermal Shutdown Circuit

Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown

circuits operate against the over temperature, clear the heat generation status immediately. Depending on

the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the

thermal shutdown circuit to not operate properly or IC breakdown before operation.

TB62D787FTG

2017-04-18

RESTRICTIONS ON PRODUCT USE

• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this

document, and related hardware, software and systems (collectively "Product") without notice.

• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written

permission, reproduction is permissible only if reproduction is without alteration/omission.

• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for

complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk

and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data

loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications,

customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this

document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA

Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are

solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the

use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or

in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating

parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR

APPLICATIONS.

• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY

HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN

LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific

applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment

used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling

equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and

equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR

PRODUCT. For details, please contact your TOSHIBA sales representative.

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• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable

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• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of

patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right

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• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR

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WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT

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AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION,

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• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the

design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass

destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including,

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• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use

Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without

limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF

NONCOMPLIANCE WITH APPLICABL E LAWS AND REGULATIONS.