HV9308 32-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs Features General Description The HV9308 is a low voltage serial to high voltage parallel converters with push-pull outputs. This device has been designed for use as a driver for AC-electroluminescent displays.It can also be used in any application requiring multiple output, high voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum fluorescent, or large matrix LCD displays. Processed with HVCMOS(R) technology Low power level shifting Shift register speed 8.0MHz Latched data outputs 5.0V CMOS compatible inputs Forward and reverse shifting options Diode to VPP allows efficient power recovery These devices consist of a 32-bit shift register, 32 latches, and control logic to enable outputs. HVOUT1 is connected to the first stage of the shift register through the Output Enable logic. Data is shifted through the shift register on the low to high transition of the clock. The HV9308 shifts in the clockwise direction when viewed from the top of the package. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (32). Operation of the shift register is not affected by the LE (latch enable) or the OE (output enable) inputs. Transfer of data from the shift register to the latch occurs when the LE input is high. The data in the latch is retained when LE is low. Block Diagram Output Enable Latch Enable VPP Data Input HVOUT1 Clock 32 bit Static Shift Register Data Out 32 Latches HVOUT2 * * * 32 Outputs Total * * * HVOUT31 HVOUT32 HV9308 Pin Configurations Ordering Information 6 Package Options Device 44-Lead Quad Plastic Chip Carrier HV9308 HV9308PJ-G 1 44 40 .653inx.653in body .180in height (max) .050in pitch -G indicates package is RoHS compliant (`Green') 44-Lead Quad Plastic Chip Carrier (PJ) Product Marking Top Marking YY = Year Sealed WW = Week Sealed LLLLLLLLLL L = Lot Number C = Country of Origin* Bottom Marking A = Assembler ID* = "Green" Packaging CCCCCCCCCCC Absolute Maximum Ratings YYWW HV9308PJ Parameter Value Supply voltage, VDD -0.5V to +7.0V Supply voltage, VPP -0.5V to +90V Logic input levels Ground current AAA -0.5V to VDD +0.5V 44-Lead Quad Plastic Chip Carrier (PJ) 1.5A 1 Continuous total power dissipation2 Operating temperature range Storage temperature range *May be part of top marking 1200W -40 to +85OC -65 to +150OC Lead temperature3 260OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Duty cycle is limited by the total power dissipated in the package. 2. For operation above 25C ambient derate linearly to maximum operating 3. temperature at 20mW/C. 4. 1.6mm (1/16 inch) from case for 10 seconds Recommended Operating Conditions Sym Parameter Min Max Units VDD Logic voltage supply 4.5 5.5 V VPP High voltage supply 8.0 80 V VIH Input high voltage VDD - 0.5 VDD V VIL Input low voltage 0 0.5 V fCLK Clock frequency 0 8.0 MHz TA Operating free-air temperature -40 +85 2 C O HV9308 Electrical Characteristics (V DC Characteristics Sym PP = 60V, VDD = 5.0V, TA = 25C) Parameter Min Max Units Conditions IPP VPP supply current - 100 A HVOUTPUTS high to low IDDQ IDD supply current (quiescent) - 100 A All inputs = VDD or GND IDD IDD supply current (operating) - 15 mA VDD = VDD max, fCLK = 8.0 MHz VOH (Data) Shift register output voltage VDD -0.5 - V IO = -100A VOL (Data) Shift register output voltage - 0.5 V IO = 100A IIH Current leakage, any input - 1.0 A Input = VDD IIL Current leakage, any input - -1.0 A Input = GND VOC HV output clamp diode voltage - -1.5 V IOC = -5.0mA VOH HV output when sourcing 52 - V IOH = -20mA, 0 to 70C VOL HV output when sinking - 4.0 V IOL = 5.0mA, 0 to 70C AC Characteristics Sym Min Max Units Conditions - 8.0 MHz --- Clock width, high or low 62 - ns --- tSU Setup time before CLK rises 25 - ns --- tH Hold time after CLK rises 10 - ns --- tDLH (Data) Data output delay after L to H CLK - 110 ns CL = 15pF tDHL (Data) Data output delay after H to L CLK - 110 ns CL = 15pF fCLK tWL or tWH Parameter Clock frequency tDLE LE delay after L to H CLK 50 - ns --- tWLE Width of LE pulse 50 - ns --- tSLE LE setup time before L to H CLK 50 - ns --- tON Delay from LE to HVOUT, L to H - 500 ns --- tOFF Delay from LE to HVOUT, H to L - 500 ns --- Power-Up Sequence 1. Connect ground 2. Apply VDD 3. Set all inputs (Data, CLK, Enable, etc.) to a known state 4. Apply VPP Power-down sequence should be the reverse of the above. The VPP should not drop below VDD during operations. 3 HV9308 Input and Output Equivalent Circuits VDD VPP VDD Data Out Input HVOUT GND GND GND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms Data Input Data Valid 50% tSU Clock 50% VIH 50% VIL tH VIH 50% 50% tWL 50% tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL tDLE VIH 50% 50% Latch Enable tWLE VOL tSLE 90% 10% HVOUT w/ S/R LOW VIL VOH VOL tOFF HVOUT w/ S/R HIGH 10% tON 4 90% VOH VOL HV9308 Function Tables Data Input Data Output Data Input LE OE HV Output H H X X L L L All HVOUT = low X L H Previous latched data H H H H L H H L X CLK No No change = low to high level transition. Pin Description Pin Function Function 1 HVOUT17 2 HVOUT16 3 HVOUT15 4 HVOUT14 5 HVOUT13 6 HVOUT12 7 HVOUT11 8 HVOUT10 9 HVOUT9 10 HVOUT8 11 HVOUT7 12 HVOUT6 13 HVOUT5 14 HVOUT4 15 HVOUT3 16 HVOUT2 17 HVOUT1 18 Data Out 19 N/C 20 N/C 21 N/C 22 CLK 23 GND Logic and high voltage ground. 24 VPP High voltage power rail. 25 VDD Low voltage logic power rail. High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to a GND, or to VPP rail levels. Serial data output Data output for cascading to the data input of the next device. No connect. Data shift register clock. Input are shifted into the shift register on the positive edge of the clock. 5 HV9308 Pin Function Function Latch enable input. 26 Latch Enable 27 Data In When LE is high, shift register data is transferred into a data latch. When LE is low, data is latched, and new data can be clocked into the shift register. Serial data input. Data needs to be present before each rising edge of the clock. Output enable input. 28 Output Enable 29 N/C 30 HVOUT32 31 HVOUT31 32 HVOUT30 33 HVOUT29 34 HVOUT28 35 HVOUT27 36 HVOUT26 37 HVOUT25 38 HVOUT24 39 HVOUT23 40 HVOUT22 41 HVOUT21 42 HVOUT20 43 HVOUT19 44 HVOUT18 When OE is low, all HV outputs are forced into a low state, regardless of data in each channel. When OE is high, all HV outputs reflect data latched. No connect. High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to a GND, or to VPP rail levels. 6 HV9308 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch D D1 1 44 .048/.042 x 45O 6 .150 MAX .056/.042 x 45O 40 Note 1 (Index Area) .075 MAX E1 E Note 2 .020max (3 Places) Top View Vertical Side View View B A Base Plane A2 Seating Plane e A1 b1 .020 MIN b Horizontal Side View View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036 .695 .656 .695 .656 e .050 BSC JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. This dimension is a non-JEDEC dimension. Drawings not to scale. Supertex Doc. #: DSPD-44PLCCPJ, Version D092408. Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. (c)2008 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV9308 A110308 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com