HV9308
Features
Processed with HVCMOS® technology
Low power level shifting
Shift register speed 8.0MHz
Latched data outputs
5.0V CMOS compatible inputs
Forward and reverse shifting options
Diode to VPP allows efficient power recovery
►
►
►
►
►
►
►
General Description
The HV9308 is a low voltage serial to high voltage parallel
converters with push-pull outputs. This device has been designed
for use as a driver for AC-electroluminescent displays.It can also
be used in any application requiring multiple output, high voltage
current sourcing and sinking capabilities such as driving plasma
panels, vacuum fluorescent, or large matrix LCD displays.
These devices consist of a 32-bit shift register, 32 latches, and
control logic to enable outputs. HVOUT1 is connected to the first
stage of the shift register through the Output Enable logic. Data is
shifted through the shift register on the low to high transition of the
clock. The HV9308 shifts in the clockwise direction when viewed
from the top of the package. A data output buffer is provided for
cascading devices. This output reflects the current status of the
last bit of the shift register (32). Operation of the shift register is
not affected by the LE (latch enable) or the OE (output enable)
inputs. Transfer of data from the shift register to the latch occurs
when the LE input is high. The data in the latch is retained when
LE is low.
Block Diagram
32-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
•
•
•
32 Outputs Total
•
•
•
Output Enable
Latch Enable
Clock
32 bit
Static Shift
Register
32 Latches
VPP
HVOUT1
Data Out
Data Input
HVOUT2
HVOUT32
HVOUT31
2
HV9308
Ordering Information
Device
Package Options
44-Lead Quad
Plastic Chip Carrier
.653inx.653in body
.180in height (max)
.050in pitch
HV9308 HV9308PJ-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Supply voltage, VDD -0.5V to +7.0V
Supply voltage, VPP -0.5V to +90V
Logic input levels -0.5V to VDD +0.5V
Ground current11.5A
Continuous total power dissipation2 1200W
Operating temperature range -40 to +85OC
Storage temperature range -65 to +150OC
Lead temperature3 260OC
Parameter Value
Sym Parameter Min Max Units
Recommended Operating Conditions
VDD Logic voltage supply 4.5 5.5 V
VPP High voltage supply 8.0 80 V
VIH Input high voltage VDD - 0.5 VDD V
VIL Input low voltage 0 0.5 V
fCLK Clock frequency 0 8.0 MHz
TAOperating free-air temperature -40 +85 OC
Pin Configurations
Notes:
Duty cycle is limited by the total power dissipated in the package.
For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C.
1.6mm (1/16 inch) from case for 10 seconds
1.
2.
3.
4.
144
640
Product Marking
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV9308PJ
LLLLLLLLLL
CCCCCCCCCCC
AAA
44-Lead Quad Plastic Chip Carrier (PJ)
44-Lead Quad Plastic Chip Carrier (PJ)
3
HV9308
Sym Parameter Min Max Units Conditions
Electrical Characteristics (VPP = 60V, VDD = 5.0V, TA = 25°C)
DC Characteristics
AC Characteristics
Sym Parameter Min Max Units Conditions
fCLK Clock frequency - 8.0 MHz ---
tWL or tWH Clock width, high or low 62 - ns ---
tSU Setup time before CLK rises 25 - ns ---
tHHold time after CLK rises 10 - ns ---
tDLH (Data) Data output delay after L to H CLK - 110 ns CL = 15pF
tDHL (Data) Data output delay after H to L CLK - 110 ns CL = 15pF
tDLE LE delay after L to H CLK 50 - ns ---
tWLE Width of LE pulse 50 - ns ---
tSLE LE setup time before L to H CLK 50 - ns ---
tON Delay from LE to HVOUT, L to H - 500 ns ---
tOFF Delay from LE to HVOUT, H to L - 500 ns ---
IPP VPP supply current - 100 µA HVOUTPUTS high to low
IDDQ IDD supply current (quiescent) - 100 µA All inputs = VDD or GND
IDD IDD supply current (operating) - 15 mA VDD = VDD max, fCLK = 8.0 MHz
VOH (Data) Shift register output voltage VDD -0.5 - V IO = -100µA
VOL (Data) Shift register output voltage - 0.5 V IO = 100µA
IIH Current leakage, any input - 1.0 µA Input = VDD
IIL Current leakage, any input - -1.0 µA Input = GND
VOC HV output clamp diode voltage - -1.5 V IOC = -5.0mA
VOH HV output when sourcing 52 - V IOH = -20mA, 0 to 70°C
VOL HV output when sinking - 4.0 V IOL = 5.0mA, 0 to 70°C
Power-Up Sequence
Connect ground
Apply VDD
Set all inputs (Data, CLK, Enable, etc.) to a known state
Apply VPP
Power-down sequence should be the reverse of the above.
The VPP should not drop below VDD during operations.
1.
2.
3.
4.
4
HV9308
Input and Output Equivalent Circuits
Switching Waveforms
VDD
Input
GND
VPP
GND
Logic Inputs
GND
Data Out
Logic Data Output High Voltage Outputs
VDD
HVOUT
Latch Enable
HVOUT
w/ S/R LOW
Data Valid50% 50%Data Input
Clock
Data Out
50% 50% 50%
tSU tH
tWL tWH
50%
50%
tDLH
tDHL
50%
tWLE
tDLE tSLE
50% 50%
tON
10%
HVOUT
w/ S/R HIGH
90%
90%
10%
tOFF
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
VIH
VOL
VOH
VOL
VOH
VOL
5
HV9308
Pin Description
Data Input LE OE HV Output
X X L All HVOUT = low
X L H Previous latched data
H H H H
L H H L
Function Tables
Data Input CLK Data Output
H H
L L
X No No change
= low to high level transition.
Pin Function Function
1 HVOUT17
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data, can drive
loads either to a GND, or to VPP rail levels.
2 HVOUT16
3 HVOUT15
4 HVOUT14
5 HVOUT13
6 HVOUT12
7 HVOUT11
8 HVOUT10
9 HVOUT9
10 HVOUT8
11 HVOUT7
12 HVOUT6
13 HVOUT5
14 HVOUT4
15 HVOUT3
16 HVOUT2
17 HVOUT1
18 Data Out
Serial data output
Data output for cascading to the data input of the next device.
19 N/C
No connect.20 N/C
21 N/C
22 CLK
Data shift register clock.
Input are shifted into the shift register on the positive edge of the clock.
23 GND Logic and high voltage ground.
24 VPP High voltage power rail.
25 VDD Low voltage logic power rail.
6
HV9308
Pin Function Function
26 Latch Enable
Latch enable input.
When LE is high, shift register data is transferred into a data latch. When LE is low, data is
latched, and new data can be clocked into the shift register.
27 Data In
Serial data input.
Data needs to be present before each rising edge of the clock.
28 Output Enable
Output enable input.
When OE is low, all HV outputs are forced into a low state, regardless of data in each
channel. When OE is high, all HV outputs reflect data latched.
29 N/C No connect.
30 HVOUT32
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data, can drive
loads either to a GND, or to VPP rail levels.
31 HVOUT31
32 HVOUT30
33 HVOUT29
34 HVOUT28
35 HVOUT27
36 HVOUT26
37 HVOUT25
38 HVOUT24
39 HVOUT23
40 HVOUT22
41 HVOUT21
42 HVOUT20
43 HVOUT19
44 HVOUT18
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
7
HV9308
Doc.# DSFP-HV9308
A110308
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
Symbol A A1 A2 b b1 D D1 E E1 e
Dimension
(inches)
MIN .165 .090 .062 .013 .026 .685 .650 .685 .650
.050
BSC
NOM .172 .105 - - - .690 .653 .690 .653
MAX .180 .120 .083 .021 .036†.695 .656 .695 .656
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension is a non-JEDEC dimension.
Drawings not to scale.
Supertex Doc. #: DSPD-44PLCCPJ, Version D092408.
.150 MAX
.048/.042 x 45O
1
.075 MAX
640
D
D1
E1 E
Top View
Horizontal Side View
View B
AA2
A1
Seating
Plane
e
b
Note 1
(Index Area)
.056/.042 x 45O
.020max
(3 Places)
.020 MIN
Vertical Side View
View B
Note 2
44
b1
Base
Plane
Notes:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Actual shape of this feature may vary.
1.
2.
