APPENDIX A INSTRUCTION SET DETAILS * Arithmetic MAC(su,uu) * Bit Field Manipulation * Program Control ABS NEG ADC NEGC ADD NORM ASL RND ASL4 SBC ASR SUB ASR4 SUBL ASR16 SWAP Tcc DOLoop Jcc CLR TFR DO FOREVER JMP CLR24 TFR2 JSR CMP ENDDO TST JScc CMPM BRKcc DEC TST2 DEC24 DIV ZERO * Logical BFTSTL Bcc BFTSTH BSR BFCLR BRA BFSET BScc BFCHG DEBUG * Loop * Move LEA MOVE DMAC AND MOVE(C) EXT ANDI MOVE(I) IMAC EOR MOVE(M) IMPY LSL MOVE(P) INC LSR MOVE(S) INC24 NOT MAC OR MACR ORI MPY ROL MPYR ROR DEBUGcc NOP REP REPcc RESET RTI RTS STOP SWI WAIT MPY(su,uu) MOTOROLA INSTRUCTION SET DETAILS A-1 SECTION CONTENTS SECTION A.1 APPENDIX A INTRODUCTION .................................................3 SECTION A.2 INSTRUCTION GUIDE ..............................................................3 SECTION A.3 NOTATION .................................................................................4 SECTION A.4 ADDRESSING MODES .............................................................10 A.4.1 Addressing Mode Modifiers ................................................................13 SECTION A.5 CONDITION CODE COMPUTATION ........................................14 SECTION A.6 PARALLEL MOVE DESCRIPTIONS .........................................15 SECTION A.7 INSTRUCTION DESCRIPTIONS ...............................................17 SECTION A.8 INSTRUCTION TIMING .............................................................224 SECTION A.9 INSTRUCTION SEQUENCE RESTRICTIONS ..........................235 A.9.1 Restrictions Near the End of DO Loops ..............................................236 A.9.2 Other DO Restrictions .........................................................................237 A.9.3 ENDDO Restrictions ...........................................................................237 A.9.4 RTI and RTS Restrictions ...................................................................238 A.9.5 SP and SSH/SSL Manipulation Restrictions .......................................238 A.9.6 R, N, and M Register Restrictions ......................................................240 A.9.7 Fast Interrupt Routines .......................................................................240 A.9.8 REP Restrictions .................................................................................241 SECTION A.10 INSTRUCTION ENCODING ....................................................241 A.10.1 Partial Encodings for Use in Instruction Encoding ............................242 A.10.2 Instruction Encoding for the Parallel Move Portion of an Instruction ....................................................................246 A.10.3 Instruction Encoding for Instructions Which Do Not Allow Parallel Moves .........................................................................248 A.10.4 Parallel Instruction Encoding of the Operation Code ........................259 A-2 INSTRUCTION SET DETAILS MOTOROLA APPENDIX A INTRODUCTION A.1 APPENDIX A INTRODUCTION This appendix contains detailed information about each instruction in the DSP56K instruction set. It presents an instruction guide to help the user understand the individual instruction descriptions and follows with sections on notation and addressing modes. The instructions are then discussed in alphabetical order. A.2 INSTRUCTION GUIDE The following information is included in each instruction description with the goal of making each description self-contained: 1. Name and Mnemonic: The mnemonic is highlighted in bold type for easy reference. 2. Assembler Syntax and Operation: For each instruction syntax, the corresponding operation is symbolically described. If there are several operations indicated on a single line in the operation field, those operations do not necessarily occur in the order shown but are generally assumed to occur in parallel. If a parallel data move is allowed, it will be indicated in parenthesis in both the assembler syntax and operation fields. If a letter in the mnemonic is optional, it will be shown in parenthesis in the assembler syntax field. 3. Description: A complete text description of the instruction is given together with any special cases and/or condition code anomalies of which the user should be aware when using that instruction. 4. Example: An example of the use of the instruction is given. The example is shown in DSP56K assembler source code format. Most arithmetic and logical instruction examples include one or two parallel data moves to illustrate the many types of parallel moves that are possible. The example includes a complete explanation, which discusses the contents of the registers referenced by the instruction (but not those referenced by the parallel moves) both before and after the execution of the instruction. Most examples are designed to be easily understood without the use of a calculator. 5. Condition Codes: The status register is depicted with the condition code bits which can be affected by the instruction highlighted in bold type. Not all bits in the status register are used. Those which are reserved are indicated with a double asterisk and are read as zeros. 6. Instruction Format: The instruction fields, the instruction opcode, and the instruction extension word are specified for each instruction syntax. When the extension MOTOROLA INSTRUCTION SET DETAILS A-3 NOTATION word is optional, it is so indicated. The values which can be assumed by each of the variables in the various instruction fields are shown under the instruction field's heading. Note that the symbols used in decoding the various opcode fields of an instruction are completely arbitrary. Furthermore, the opcode symbols used in one instruction are completely independent of the opcode symbols used in a different instruction. 7. Timing: The number of oscillator clock cycles required for each instruction syntax is given. This information provides the user a basis for comparison of the execution times of the various instructions in oscillator clock cycles. Refer to Table A-1 and Section A.8 for a complete explanation of instruction timing, including the meaning of the symbols "aio", "ap", "ax", "ay", "axy", "ea", "jx", "mv", "mvb", "mvc", "mvm", "mvp", "rx", "wio", "wp", "wx", and "wy". 8. Memory: The number of program memory words required for each instruction syntax is given. This information provides the user a basis for comparison of the number of program memory locations required for each of the various instructions in 24bit program memory words. Refer to Table A-1 and Section A.8 for a complete explanation of instruction memory requirements, including the meaning of the symbols "ea" and "mv". A.3 NOTATION Each instruction description contains symbols used to abbreviate certain operands and operations. Table A-1 lists the symbols used and their respective meanings. Depending on the context, registers refer to either the register itself or the contents of the register. A-4 INSTRUCTION SET DETAILS MOTOROLA NOTATION Table A-1 Instruction Description Notation Data ALU Registers Operands Xn Input Register X1 or X0 (24 Bits) Yn Input Register Y1 or Y0 (24 Bits) An Accumulator Registers A2, A1, A0 (A2 -- 8 Bits, A1 and A0 -- 24 Bits) Bn Accumulator Registers B2, B1, B0 (B2 -- 8 Bits, B1 and B0 -- 24 Bits) X Input Register X = X1: X0 (48 Bits) Y Input Register Y = Y1: Y0 (48 Bits) A Accumulator A = A2: A1: A0 (56 Bits)* B Accumulator B = B2: B1: B0 (56 BIts)* AB Accumulators A and B = A1: B1 (48 Bits)* BA Accumulators B and A = B1: A1 (48 Bits)* A10 Accumulator A = A1: A0 (48 Bits) B10 Accumulator B= B1:B0 (48 bits) * NOTE: In data move operations, shifting and limiting are performed when this register is specified as a source operand. When specified as a destination operand, sign extension and possibly zeroing are performed. Address ALU Registers Operands Rn Address Registers R0 - R7 (16 Bits) Nn Address Offset Registers N0 - N7 (16 Bits) Mn Address Modifier Registers M0 - M7 (16 Bits) MOTOROLA INSTRUCTION SET DETAILS A-5 NOTATION Table A-1 Instruction Description Notation (Continued) Program Control Unit Registers Operands PC Program Counter Register (16 Bits) MR Mode Register (8 Bits) CCR Condition Code Register (8 Bits) SR Status Register = MR:CCR (16 Bits) OMR Operating Mode Register (8 Bits) LA Hardware Loop Address Register (16 Bits) LC Hardware Loop Counter Register (16 Bits) SP System Stack Pointer Register (6 Bits) SSH Upper Portion of the Current Top of the Stack (16 Bits) SSL Lower Portion of the Current Top of the Stack (16 Bits) SS System Stack RAM = SSH: SSL (15 Locations by 32 Bits) Address Operands ea Effective Address eax Effective Address for X Bus eay Effective Address for Y Bus xxxx Absolute Address (16 Bits) xxx Short Jump Address (12 Bits) aa Absolute Short Address (6 Bits, Zero Extended) pp I/O Short Address (6 Bits, Ones Extended) <. . .> Specifies the Contents of the Specified Address X: X Memory Reference Y: Y Memory Reference L: Long Memory Reference = X:Y P: Program Memory Reference A-6 INSTRUCTION SET DETAILS MOTOROLA NOTATION Table A-1 Instruction Description Notation (Continued) Miscellaneous Operands S, Sn Source Operand Register D, Dn Destination Operand Register D [n] Bit n of D Destination Operand Register #n Immediate Short Data (5 Bits) #xx Immediate Short Data (8 Bits) #xxx Immediate Short Data (12 Bits) #xxxxxx Immediate Data (24 Bits) Unary Operators - Negation Operator -- Logical NOT Operator (Overbar) PUSH Push Specified Value onto the System Stack (SS) Operator PULL Pull Specified Value from the System Stack (SS) Operator READ Read the Top of the System Stack (SS) Operator PURGE Delete the Top Value on the System Stack (SS) Operator | Absolute Value Operator | Binary Operators + Addition Operator - Subtraction Operator * Multiplication Operator /, / Division Operator + Logical Inclusive OR Operator * Logical AND Operator Logical Exclusive OR Operator "Is Transferred To" Operator : Concatenation Operator MOTOROLA INSTRUCTION SET DETAILS A-7 NOTATION Table A-1 Instruction Description Notation (Continued) Addressing Mode Operators << I/O Short Addressing Mode Force Operator < Short Addressing Mode Force Operator > Long Addressing Mode Force Operator # Immediate Addressing Mode Operator #> Immediate Long Addressing Mode Force Operator #< Immediate Short Addressing Mode Force Operator Mode Register (MR) Symbols DM Double Precision Multiply Bit Indicating if the Chip is in Double Precision Multiply Mode LF Loop Flag Bit Indicating When a DO Loop is in Progress T Trace Mode Bit Indicating if the Tracing Function has been Enabled S1, S0 Scaling Mode Bits Indicating the Current Scaling Mode I1, I0 Interrupt Mask Bits Indicating the Current Interrupt Priority Level Condition Code Register (CCR) Symbols Standard Definitions (Table A-5 in Section A.5 Describes Exceptions) S Block Floating Point Scaling Bit Indicating Data Growth Detection L Limit Bit Indicating Arithmetic Overflow and/or Data Shifting/Limiting E Extension Bit Indicating if the Integer Portion of A or B is in Use U Unnormalized Bit Indicating if the A or B Result is Unnormalized N Negative Bit Indicating if Bit 55 of the A or B Result is Set Z Zero Bit Indicating if the A or B Result Equals Zero V Overflow Bit Indicating if Arithmetic Overflow has Occurred in A or B C Carry Bit Indicating if a Carry or Borrow Occurred in A or B Result A-8 INSTRUCTION SET DETAILS MOTOROLA NOTATION Table A-1 Instruction Description Notation (Continued) Instruction Timing Symbols aio Time Required to Access an I/O Operand ap Time Required to Access a P Memory Operand ax Time Required to Access an X Memory Operand ay Time Required to Access a Y Memory Operand axy Time Required to Access XY Memory Operands ea Time or Number of Words Required for an Effective Address jx Time Required to Execute Part of a Jump-Type Instruction mv Time or Number of Words Required for a Move-Type Operation mvb Time Required to Execute Part of a Bit Manipulation Instruction mvc Time Required to Execute Part of a MOVEC Instruction mvm Time Required to Execute Part of a MOVEM Instruction mvp Time Required to Execute Part of a MOVEP Instruction rx Time Required to Execute Part of an RTI or RTS Instruction wio Number of Wait States Used in Accessing External I/O wp Number of Wait States Used in Accessing External P Memory wx Number of Wait States Used in Accessing External X Memory wy Number of Wait States Used in Accessing External Y Memory Other Symbols () Optional Letter, Operand, or Operation (...) Any Arithmetic or Logical Instruction Which Allows Parallel Moves EXT Extension Register Portion of an Accumulator (A2 or B2) LS Least Significant LSP Least Significant Portion of an Accumulator (A0 or B0) MS Most Significant MSP Most Significant Portion of a n Accumulator (A1 or B1) r Rounding constant S/L Shifting and/or Limiting on a Data ALU Register Sign Ext Sign Extension of a Data ALU Register Zero Zeroing of a Data ALU Register MOTOROLA INSTRUCTION SET DETAILS A-9 ADDRESSING MODES A.4 ADDRESSING MODES The addressing modes are grouped into three categories: register direct, address register indirect, and special. These addressing modes are summarized in Table A-2. All address calculations are performed in the address ALU to minimize execution time and loop overhead. Addressing modes, which specify whether the operands are in registers, in memory, or in the instruction itself (such as immediate data), provide the specific address of the operands. The register direct addressing mode can be subclassified according to the specific register addressed. The data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0, A, and B. The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR. Address register indirect modes use an address register Rn (R0-R7) to point to locations in X, Y, and P memory. The contents of the Rn address register (Rn) is the effective address (ea) of the specified operand, except in the "indexed by offset" mode where the effective address (ea) is (Rn+Nn). Address register indirect modes use an address modifier register Mn to specify the type of arithmetic to be used to update the address register Rn. If an addressing mode specifies an address offset register Nn, the given address offset register is used to update the corresponding address register Rn. The Rn address register may only use the corresponding address offset register Nn and the corresponding address modifier register Mn. For example, the address register R0 may only use the N0 address offset register and the M0 address modifier register during actual address computation and address register update operations. This unique implementation allows the user to easily address a wide variety of DSP-oriented data structures. All address register indirect modes use at least one set of address registers (Rn, Nn, and Mn), and the XY memory reference uses two sets of address registers, one for the X memory space and one for the Y memory space. The special addressing modes include immediate and absolute addressing modes as well as implied references to the program counter (PC), the system stack (SSH or SSL), and program (P) memory. Addressing modes may also be categorized by the ways in which they can be used. Table A-2 and Table A-3 show the various categories to which each addressing mode belongs. These addressing mode categories may be combined so that additional, more restrictive classifications may be defined. For example, the instruction descriptions may use a memory alterable classification, which refers to addressing modes that are both memory addressing modes and alterable addressing modes. Thus, memory alterable addressing modes use address register indirect and absolute addressing modes. A - 10 INSTRUCTION SET DETAILS MOTOROLA ADDRESSING MODES Table A-2 DSP56K Addressing Modes Addressing Mode Uses Mn Modifier Operand Reference S C D A P X Y L XY Register Direct Data or Control Register No X X X Address Register Rn No X Address Modifier Register Mn No X Address Offset Register Nn No X Address Register Indirect No Update No X X X X X Postincrement by 1 Yes X X X X X Postdecrement by 1 Yes X X X X X Postincrement by Offset Nn Yes X X X X X Postdecrement by Offset Nn Yes X X X X Indexed by Offset Nn Yes X X X X Predecrement by 1 Yes X X X X X X X X X X Special Immediate Data No X Absolute Address No X Immediate Short Data No X Short Jump Address No X Absolute Short Address No X MOTOROLA INSTRUCTION SET DETAILS A - 11 ADDRESSING MODES Table A-3 DSP56K Addressing Mode Encoding Addressing Mode Mode MMM Reg RRR Addressing Categories U P M A Assembler Syntax Register Direct Data or Control Register -- -- X (See Table A-1) Address Register -- -- X Rn Address Offset Register -- -- X Nn Address Modifier Register -- -- X Mn Address Register Indirect No Update 100 Rn X X X (Rn) Postincrement by 1 011 Rn X X X X (Rn) + Postdecrement by 1 010 Rn X X X X (Rn) - Postincrement by Offset Nn 001 Rn X X X X (Rn) + Nn Postdecrement by Offset Nn 000 Rn X X X (RN) - Nn Indexed by Offset Nn 101 Rn X X (Rn + Nn) Predecrement by 1 111 Rn X X - (Rn) Special Immediate Data 110 100 X Absolute Address 110 000 X Immediate Short Data -- -- Short Jump Address -- -- X xxx Absolute Short Address -- -- X aa I/O Short Address -- -- X pp Implicit -- -- X Update Mode (U) Parallel Mode (P) Memory Mode (M) Alterable Mode (A) A - 12 #xxxxxx X xxxx #xx - Modifies address registers without any associated data move. - Used in instructions where two effective addresses are required. - Refers to operands in memory using an effective addressing field. - Refers to alterable or writable registers or memory. INSTRUCTION SET DETAILS MOTOROLA ADDRESSING MODES The address register indirect addressing modes require that the offset register number be the same as the address register number. The assembler syntax "N" may be used instead of "Nn" in the address register indirect memory addressing modes. If "N" is specified, the offset register number is the same as the address register number. A.4.1 Addressing Mode Modifiers The addressing mode selected in the instruction word is further specified by the contents of the address modifier register Mn. The addressing mode update modifiers (M0-M7) are shown in Table A-4. There are no restrictions on the use of modifier types with any address register indirect addressing mode. MOTOROLA INSTRUCTION SET DETAILS A - 13 ADDRESSING MODES Table A-4 Addressing Mode Modifier Summary A - 14 Binary M0-M7 Hex M0-M7 Addressing Mode Arithmetic 0000 0000 0000 0000 0000 Reverse Carry (Bit Reverse) 0000 0000 0000 0001 0001 Modulo 2 00000000 0000 0010 0002 Modulo 3 : : : 0111 1111 1111 1110 7FFE Modulo 32767 0111 1111 1111 1111 7FFF Modulo 32768 1000 0000 0000 0000 8000 Reserved 1000 0000 0000 0001 8001 Multiple Wrap-Around Modulo 2 1000 0000 0000 0010 8002 Reserved 1000 0000 0000 0011 8003 Multiple Wrap-Around Modulo 4 : : 1000 0000 0000 0111 8007 : : 1000 0000 0000 1111 800F : : 1000 0000 0001 1111 801F : : 1000 0000 0011 1111 803F : : 1000 0000 0111 1111 807F : : 1000 0000 1111 1111 80FF : : 1000 0001 1111 1111 81FF : : 1000 0011 1111 1111 83FF : : Multiple Wrap-Around Modulo 210 Reserved 1000 0111 1111 1111 87FF Multiple Wrap-Around Modulo 211 : : 1000 1111 1111 1111 8FFF : : Multiple Wrap-Around Modulo 212 Reserved 1001 1111 1111 1111 9FFF Multiple Wrap-Around Modulo 213 : : 1011 1111 1111 1111 BFFF : : 1111 1111 1111 1111 FFFF Reserved Multiple Wrap-Around Modulo 8 Reserved Multiple Wrap-Around Modulo 24 Reserved Multiple Wrap-Around Modulo 25 Reserved Multiple Wrap-Around Modulo 26 Reserved Multiple Wrap-Around Modulo 27 Reserved Multiple Wrap-Around Modulo 28 Reserved Multiple Wrap-Around Modulo 29 Reserved Reserved Reserved Multiple Wrap-Around Modulo 214 Reserved Linear (Modulo 215) INSTRUCTION SET DETAILS MOTOROLA CONDITION CODE COMPUTATION A.5 CONDITION CODE COMPUTATION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR The condition code register (CCR) portion of the status register (SR) consists of eight defined bits: S -- Scaling Bit N -- Negative Bit L -- Limit Bit Z -- Zero Bit E -- Extension Bit V -- Overflow Bit U -- Unnormalized Bit C -- Carry Bit The E, U, N, Z, V, and C bits are true condition code bits that reflect the condition of the result of a data ALU operation. These condition code bits are not latched and are not affected by address ALU calculations or by data transfers over the X, Y, or global data buses. The L bit is a latching overflow bit which indicates that an overflow has occurred in the data ALU or that data limiting has occurred when moving the contents of the A and/or B accumulators. The S bit is a latching bit used in block floating point operations to indicate the need to scale the number in A or B. See SECTION 5 - PROGRAM CONTROL UNIT for information on the MR portion of the status register. The standard definition of the condition code bits follows. Exceptions to these standard definitions are given in the notes which follow Table A-5. MOTOROLA INSTRUCTION SET DETAILS A - 15 CONDITION CODE COMPUTATION S (Scaling Bit) The scaling bit (S) is used to detect data growth, which is required in Block Floating Point FFT operation. Typically, the bit is tested after each pass of a radix 2 decimation-in-time FFT and, if it is set, the appropriate scaling mode should be activated in the next pass. The Block Floating Point FFT algorithm is described in the Motorola application note APR4/D, "Implementation of Fast Fourier Transforms on Motorola's DSP56000/ DSP56001 and DSP96002 Digital Signal Processors." This bit is computed according to the logical equations below when an instruction or a parallel move moves the result of accumulator A or B to XDB or YDB. It is a "sticky" bit, cleared only by an instruction that specifically clears it. The following logical equations are used to compute the scaling bit based upon the scaling mode bits: If S1=0 and S0=0 (no scaling) then S = (A46 XOR A45) OR (B46 XOR B45) If S1=0 and S0=1 (scale down) then S = (A47 XOR A46) OR (B47 XOR B46) If S1=1 and S0=0 (scale up) then S = (A45 XOR A44) OR (B45 XOR B44) If S1=1 and S0=1 (reserved) then the S flag is undefined. where Ai and Bi means bit i in accumulator A or B. L (Limit Bit) Set if the overflow bit V is set or if an instruction or a parallel move causes the data shifter/limiters to perform a limiting operation. Not affected otherwise. This bit is latched and must be reset by the user. E (Extension Bit) Cleared if all the bits of the signed integer portion of the A or B result are the same - i.e., the bit patterns are either 00 . . . 00 or 11 . . . 11. Set otherwise. The signed integer portion is defined by the scaling mode as shown in the following table: A - 16 INSTRUCTION SET DETAILS MOTOROLA CONDITION CODE COMPUTATION S1 S0 Scaling Mode Signed Integer Portion 0 0 1 0 1 0 No Scaling Scale Down Scale Up Bits 55, 54, . . . . 48, 47 Bits 55, 54, . . . . 49, 48 Bits 55, 54, . . . . 47, 46 Note that the signed integer portion of an accumulator IS NOT necessarily the same as the extension register portion of that accumulator. The signed integer portion of an accumulator consists of the MS 8, 9, or 10 bits of that accumulator, depending on the scaling mode being used. The extension register portion of an accumulator (A2 or B2) is always the MS 8 bits of that accumulator. The E bit refers to the signed integer portion of an accumulator and NOT the extension register portion of that accumulator. For example, if the current scaling mode is set for no scaling (i.e., S1=S0=0), the signed integer portion of the A or B accumulator consists of bits 47 through 55. If the A accumulator contained the signed 56-bit value $00:800000:000000 as a result of a data ALU operation, the E bit would be set (E=1) since the 9 MS bits of that accumulator were not all the same (i.e., neither 00 . . 00 nor 11 . . 11). This means that data limiting will occur if that 56-bit value is specified as a source operand in a move-type operation. This limiting operation will result in either a positive or negative, 24-bit or 48-bit saturation constant being stored in the specified destination. The only situation in which the signed integer portion of an accumulator and the extension register portion of an accumulator are the same is in the "Scale Down" scaling mode (i.e., S1=0 and S0=1). U (Unnormalized Bit) Set if the two MS bits of the MSP portion of the A or B result are the same. Cleared otherwise. The MSP portion is defined by the scaling mode. The U bit is computed as follows: S1 S0 Scaling Mode U Bit Computation 0 0 1 0 1 0 No Scaling Scale Down Scale Up U=(Bit 47 Bit 46) U=(Bit 48 Bit 47) U=(Bit 46 Bit 45) N (Negative Bit) Set if the MS bit 55 of the A or B result is set. Cleared otherwise. Z (Zero Bit) Set if the A or B result equals zero. Cleared otherwise. V (Overflow Bit) Set if an arithmetic overflow occurs in the 56-bit A or B result. This indicates that the result cannot be represented in the 56-bit accumulator; thus, the accumulator has overflowed. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 17 CONDITION CODE COMPUTATION C (Carry Bit) Set if a carry is generated out of the MS bit of the A or B result of an addition or if a borrow is generated out of the MS bit of the A or B result of a subtraction. The carry or borrow is generated out of bit 55 of the A or B result. Cleared otherwise. Table A-5 shows how each condition code bit is affected by each instruction. Exceptions to the standard definitions given above are indicated by a number or a "?". Consult the corresponding note for the special definition that applies in each particular case. Although many of the instructions allow optional parallel moves, Table A-5 applies when there are no parallel moves associated with an instruction. With this restriction, the states of the condition code bits are determined only by the execution of the instruction itself. However, the S and L bits may be determined differently than shown in the table when a parallel move is associated with the instruction. When using an optional parallel move, refer to the individual instruction's detailed description in Section A.7 to see how the S and L bits are determined. A - 18 INSTRUCTION SET DETAILS MOTOROLA CONDITION CODE COMPUTATION Table A-5 Condition Code Computations for Instructions (No Parallel Move) Mnemonic S L E U N Z V S L E U N Z V C ABS -- 1 9 1 11 LUA -- -- -- -- -- -- -- -- MAC -- -- -- ADDR -- -- 2 -- ADDL -- -- -- -- -- ADD LSR ADC C Notes -- -- -- -- AND -- -- -- -- 8 9 1 -- ANDI ? ? ? ? ? ? ? ? ASL -- 4 MOVEP -- -- 2 ASR 1 5 MPY BCHG ? ? ? ? ? ? ? ? 14 MPYR -- BCLR ? ? ? ? ? ? ? ? 14 NEG 3 Mnemonic MACR -- MOVE -- -- MOVEC ? ? ? ? ? ? ? ? 13 MOVEM ? ? ? ? ? ? ? ? 13 ? ? ? ? ? ? ? ? 13 -- 1 -- 1 -- -- -- -- -- -- -- -- BSET ? ? ? ? ? ? ? ? 14 NOP -- -- -- -- -- -- BTST ? ? -- -- -- -- -- ? 14 NORM -- 2 -- CLR -- -- NOT -- -- 8 9 1 -- OR -- -- -- -- 8 9 1 -- ORI ? ? ? ? ? ? ? ? CMP -- CMPM -- 1 -- DEBUG -- -- -- -- -- -- -- -- REP -- -- -- -- -- -- -- -- -- -- -- -- RESET -- -- -- -- -- -- -- -- RND -- -- -- -- DEBUGcc -- -- DEC -- DIV -- ROL -- -- -- -- 8 9 1 10 DO -- -- -- -- 2 7 -- -- -- -- -- -- ROR -- -- -- -- 8 9 1 11 ENDDO -- -- -- -- -- -- -- -- RTI ? ? ? ? ? ? ? ? EOR -- -- -- -- 8 9 1 -- RTS -- -- -- -- -- -- -- -- ILLEGAL -- -- -- -- -- -- -- -- SBC -- INC -- STOP -- -- -- -- -- -- -- Jcc -- -- -- -- -- -- -- -- ? ? -- -- -- -- -- -- JCLR 2 -- JMP -- -- -- -- -- -- -- -- SUBR -- JScc -- -- -- -- -- -- -- -- SWI -- -- -- -- -- -- -- -- JSCLR ? ? -- -- -- -- -- -- 14 Tcc -- -- -- -- -- -- -- -- JSET ? ? -- -- -- -- -- -- 14 TFR -- -- -- -- -- -- -- -- JSR -- -- -- -- -- -- -- -- TST -- -- 1 -- JSSET ? ? -- -- -- -- -- -- WAIT -- -- -- -- -- -- -- LSL -- -- -- -- 8 9 1 10 where: 14 14 Notes SUB -- SUBL -- -- 6 12 Set according to the standard definition of the operation -- Not affected by the operation ? or # Set according to a special definition (refer to the following notes) and can be a 0 or 1 The following notes apply to Table A-5: MOTOROLA INSTRUCTION SET DETAILS A - 19 PARALLEL MOVE DESCRIPTIONS 1. The bit is cleared. 2. V -- Set if an arithmetic overflow occurs in the 56-bit A or B result or if the MS bit of the destination operand is changed as a result of the left shift. Cleared otherwise. 3. For destination operand CCR, the bits are cleared if the corresponding bits in the immediate data are cleared. Otherwise they are not affected. For other destination operands, the bits are not affected. 4. C -- Set if bit 55 of the source operand was set prior to instruction execution. Cleared otherwise. 5. C -- Set if bit 0 of the source operand was set prior to instruction execution. Cleared otherwise. 6. For destination operand CCR, the bits are set if the corresponding bits in the immediate data are set. Otherwise, they are not affected. For other destination operands, the bits are not affected. 7. C -- Set if bit 55 of the result is cleared. Cleared otherwise. 8. N -- Set if bit 47 of the A or B result is set. Cleared otherwise. 9. Z -- Set if bits 47 - 24 of the A or B result are zero. Cleared otherwise. 10. C -- Set if bit 47 of the source operand was set prior to instruction execution. Cleared otherwise. 11. C -- Set if bit 24 of the source operand was set prior to instruction execution. Cleared otherwise. 12. Set according to the value pulled from the stack. 13. For destination operand SR, the bits are set according to the corresponding bit of the source operand. If SR is not specified as a destination operand, the L bit is set if data limiting occurred and the S bit is computed according to the definition. (See Section A.5.) Otherwise, the bits are unaffected. 14. Due to complexity, refer to the detailed description of the instruction. A.6 PARALLEL MOVE DESCRIPTIONS Many of the instructions in the DSP56K instruction set allow optional parallel data bus movement. Section A.7 indicates the parallel move option in the instruction syntax with the statement `"parallel move)". The MOVE instruction is equivalent to a NOP with parallel moves. Therefore, a detailed description of each parallel move is given with the MOVE instruction details in Section A.7, beginning on page A-160. A - 20 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS A.7 INSTRUCTION DESCRIPTIONS The following section describes each instruction in the DSP56K instruction set in complete detail. The format of each instruction description is given in Section A.2. Instructions which allow parallel moves include the notation "(parallel move)" in both the Assembler Syntax and the Operation fields. The example given with each instruction discusses the contents of all the registers and memory locations referenced by the opcode-operand portion of that instruction but not those referenced by the parallel move portion of that instruction. Refer to page A-160 for a complete discussion of parallel moves, including examples which discuss the contents of all the registers and memory locations referenced by the parallel move portion of an instruction. Note: Whenever an instruction uses an accumulator as both a destination operand for a data ALU operation and as a source for a parallel move operation, the parallel move operation occurs first and will use the data that exists in the accumulator before the execution of the data ALU operation has occurred. Whenever a bit in the condition code register is defined according to the standard definition given in Section A.5, a brief definition will be given in normal text in the Condition Code section of that instruction description. Whenever a bit in the condition code register is defined according to a special definition for some particular instruction, the special definition of that bit will be given in the Condition Code section of that instruction in bold text to alert the user to any special conditions concerning its use. The definition and thus the computation of both the E (extension) and U (unnormalized) bits of the condition code register (CCR) varies according to the scaling mode being used. Refer to Section A.5 for complete details. Note: The signed integer portion of an accumulator is NOT necessarily the same as either the A2 or B2 extension register portion of that accumulator. The signed integer portion of an accumulator is defined according to the scaling mode being used and can consist of the MS 8, 9, or 10 bits of an accumulator. Refer to Section A.5 for complete details. MOTOROLA INSTRUCTION SET DETAILS A - 21 INSTRUCTION DESCRIPTIONS ABS ABS Absolute Value Operation: | D | D (parallel move) Assembler Syntax: ABS D (parallel move) Description: Take the absolute value of the destination operand D and store the result in the destination accumulator. Example: : A1 : ABS #$123456,X0 A,Y0 ;take abs. value, set up X0, save value Before Execution A After Execution A $FF:FFFFFF:FFFFF2 $00:000000:00000E Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $FF:FFFFFF:FFFFF2. Since this is a negative number, the execution of the ABS instruction takes the twos complement of that value and returns $00:000000:00000E. Note: For the case in which the D operand equals $80:000000:000000 (-256.0), the ABS instruction will cause an overflow to occur since the result cannot be correctly expressed using the standard 56-bit, fixed-point, twos-complement data representation. Data limiting does not occur (i.e., A is not set to the limiting value of $7F:FFFFFF:FFFFFF). Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION. L -- Set if limiting (parallel move) or overflow has occurred in result E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Set if overflow has occurred in A or B result Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. A - 22 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ABS ABS Absolute Value Instruction Format: ABS D Opcode: 23 8 DATA BUS MOVE FIELD 7 4 0 0 1 0 3 0 d 1 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Dd A0 B1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 23 INSTRUCTION DESCRIPTIONS ADC ADC Add Long with Carry Operation: S+C+D D (parallel move) Assembler Syntax: ADC S,D (parallel move) Description: Add the source operand S and the carry bit C of the condition code register to the destination operand D and store the result in the destination accumulator. Long words (48 bits) may be added to the (56-bit) destination accumulator. Note: The carry bit is set correctly for multiple precision arithmetic using long-word operands if the extension register of the destination accumulator (A2 or B2) is the sign extension of bit 47 of the destination accumulator (A or B). Example: : MOVE L:<$0,X MOVE L:<$1,A MOVE L:<$2,Y ADD X,A L:<$3,B ADC Y,B A10,L:<$4 MOVE B10,L:<$5 : ;get a 48-bit LS long-word operand in X ;get other LS long word in A (sign ext.) ;get a 48-bit MS long-word operand in Y ;add LS words; get other MS word in B ;add MS words with carry, save LS sum ;save MS sum Before Execution A After Execution $FF:800000:000000 A $FF:000000:000000 X $800000:000000 X $800000:000000 B $00:000000:000001 B $00:000000:000003 Y $000000:000001 Y $000000:000001 Explanation of Example: This example illustrates long-word double-precision (96-bit) addition using the ADC instruction. Prior to execution of the ADD and ADC instructions, the double-precision 96-bit value $000000:000001:800000:000000 is loaded into the Y and X registers (Y:X), respectively. The other double-precision 96-bit value $000000:000001:800000:000000 is loaded into the B and A accumulators (B:A), respectively. Since the 48-bit value loaded into the A accumulator is automatically sign extended to 56 bits and the other 48-bit long-word operand is internally sign extended to 56 bits during instruction execution, the carry bit will be set correctly after the execution of the ADD X,A instruction. The ADC Y,B instruction then produces the correct MS 56-bit A - 24 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ADC ADC Add Long with Carry result. The actual 96-bit result is stored in memory using the A10 and B10 operands (instead of A and B) because shifting and limiting is not desired. Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if limiting (parallel move) or overflow has occurred in result E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Set if overflow has occurred in A or B result C -- Set if a carry (or borrow) occurs from bit 55 of A or B result. Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ADC S,D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 1 J 3 d 0 0 0 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S,D J d X,A X,B Y,A Y,B 00 01 10 11 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 25 INSTRUCTION DESCRIPTIONS ADD ADD Add Operation: S+DD (parallel move Assembler Syntax: ADD S,D (parallel move) Description: Add the source operand S to the destination operand D and store the result in the destination accumulator. Words (24 bits), long words (48 bits), and accumulators (56 bits) may be added to the destination accumulator. Note: The carry bit is set correctly using word or long-word source operands if the extension register of the destination accumulator (A2 or B2) is the sign extension of bit 47 of the destination accumulator (A or B). Thus, the carry bit is always set correctly using accumulator source operands, but can be set incorrectly if A1, B1, A10, or B10 are used as source operands and A2 and B2 are not replicas of bit 47. Example: : ADD X0,A A,X1 : A,Y:(R1)+l ;24-bit add, set up X1, save prev. result Before Execution X0 A $FFFFFF $00:000100:000000 After Execution X0 A $FFFFFF $00:0000FF:000000 Explanation of Example: Prior to execution, the 24-bit X0 register contains the value $FFFFFF and the 56-bit A accumulator contains the value $00:000100:000000. The ADD instruction automatically appends the 24-bit value in the X0 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, and adds the result to the 56-bit A accumulator. Thus, 24-bit operands are added to the MSP portion of A or B (A1 or B1) because all arithmetic instructions assume a fractional, twos complement data representation. Note that 24-bit operands can be added to the LSP portion of A or B (A0 or B0) by loading the 24-bit operand into X0 or Y0, forming a 48-bit word by loading X1 or Y1 with the sign extension of X0 or Y0 and executing an ADD X,A or ADD Y,A instruction. A - 26 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ADD ADD Add Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if limiting (parallel move) or overflow has occurred in result E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z -- Set if A or B result equals zero V -- Set if overflow has occurred in A or B result C -- Set if a carry (or borrow) occurs from bit 55 of A or B result. Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ADD S,D Opcode: 23 8 7 0 DATA BUS MOVE FIELD 4 J J J 3 d 0 0 0 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S,D J J J d B,A A,B X,A X,B Y,A Y,B 0010 0011 0100 0101 0110 0111 S,D JJJd S,D JJJd X0,A X0,B Y0,A Y0,B X1,A X1,B 1000 1001 1010 1011 1100 1101 Y1,A 1 1 1 0 Y1,B 1 1 1 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 27 INSTRUCTION DESCRIPTIONS ADDL Shift Left and Add Accumulators Operation: S+2DD (parallel move) ADDL Assembler Syntax: ADDL S,D (parallel move) Description: Add the source operand S to two times the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the addition operation. The carry bit is set correctly if the source operand does not overflow as a result of the left shift operation. The overflow bit may be set as a result of either the shifting or addition operation (or both). This instruction is useful for efficient divide and decimation in time (DIT) FFT algorithms. Example: : ADDL A,B #$0,R0 : ;A+2BB, set up addr. reg. R0 Before Execution A B After Execution $00:000000:000123 A $00:000000:000123 $00:005000:000000 B $00:00A000:000123 Explanation of Example: Prior to execution, the 56-bit accumulator contains the value $00:000000:000123, and the 56-bit B accumulator contains the value $00:005000:000000. The ADDL A,B instruction adds two times the value in the B accumulator to the value in the A accumulator and stores the 56-bit result in the B accumulator. A - 28 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ADDL ADDL Shift Left and Add Accumulators Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if limiting (parallel move) or overflow has occurred in result E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Set if overflow has occurred in A or B result or if the MS bit of the destination operand is changed as a result of the instruction's left shift C -- Set if a carry (or borrow) occurs from bit 55 of A or B result. Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ADDL S,D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 0 1 3 d 0 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S,D d B,A A,B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 29 INSTRUCTION DESCRIPTIONS ADDR Shift Right and Add Accumulators Operation: S+D / 2D (parallel move) ADDR Assembler Syntax: ADDR S,D (parallel move) Description: Add the source operand S to one-half the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the right while the MS bit of D is held constant prior to the addition operation. In contrast to the ADDL instruction, the carry bit is always set correctly, and the overflow bit can only be set by the addition operation and not by an overflow due to the initial shifting operation. This instruction is useful for efficient divide and decimation in time (DIT) FFT algorithms. Example: : ADDR B,A X0,X:(R1)+N1 Y0,Y:(R4)- : ;B+A / 2A, save X0 and Y0 Before Execution After Execution A $80:000000:2468AC A $C0:013570:123456 B $00:013570:000000 B $00:013570:000000 Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $80:000000:2468AC, and the 56-bit B accumulator contains the value $00:013570:000000. The ADDR B,A instruction adds one-half the value in the A accumulator to the value in the B accumulator and stores the 56-bit result in the A accumulator. A - 30 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ADDR ADDR Shift Right and Add Accumulators Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if limiting (parallel move) or overflow has occurred in result E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Set if overflow has occurred in A or B result C -- Set if a carry (or borrow) occurs from bit 55 of A or B result. Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ADDR S,D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 0 0 3 d 0 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S,D d B,A A,B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 31 INSTRUCTION DESCRIPTIONS AND AND Logical AND Operation: S * D[47:24]D[47:24] (parallel move) where *denotes the logical AND operator Assembler Syntax: AND S,D (parallel move) Description: Logically AND the source operand S with bits 47-24 of the destination operand D and store the result in bits 47-24 of the destination accumulator. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected. Example: : AND X0,A1 (R5)-N5 : ;AND X0 with A1, update R5 using N5 Before Execution After Execution X0 $FF0000 X0 $FF0000 A $00:123456:789ABC A $00:120000:789ABC Explanation of Example: Prior to execution, the 24-bit X0 register contains the value $FF0000, and the 56-bit A accumulator contains the value $00:123456:789ABC. The AND X0,A instruction logically ANDs the 24-bit value in the X0 register with bits 47-24 of the A accumulator (A1) and stores the result in the A accumulator with bits 55-48 and 23-0 unchanged. Condition Codes: 15 14 13 12 LF DM T ** MR 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U 3 2 1 0 N Z V C CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if limiting occurs during parallel move N -- Set if bit 47 of A or B result is set Z-- Set if bits 47-24 of A or B result are zero V -- Always cleared A - 32 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS AND AND Logical AND Instruction Format: AND S,D Opcode: 23 8 7 DATA BUS MOVE FIELD 4 0 1 J J 3 d 0 1 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S JJ X0 X1 Y0 Y1 00 10 01 11 Dd A 0 (only A1 is changed) B 1 (only B1 is changed) Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 33 INSTRUCTION DESCRIPTIONS ANDI AND Immediate with Control Register ANDI Operation: Assembler Syntax: #xx * DD AND(I) #xx,D where * denotes the logical AND operator Description: Logically AND the 8-bit immediate operand (#xx) with the contents of the destination control register D and store the result in the destination control register. The condition codes are affected only when the condition code register (CCR) is specified as the destination operand. Restrictions: The ANDI #xx,MR instruction cannot be used immediately before an ENDDO or RTI instruction and cannot be one of the last three instructions in a DO loop (at LA-2, LA-1, or LA). The ANDI #xx,CCR instruction cannot be used immediately before an RTI instruction. Example: : AND #$FE,CCR : ;clear carry bit C in cond. code register Before Execution CCR $31 After Execution CCR $30 Explanation of Example: Prior to execution, the 8-bit condition code register (CCR) contains the value $31. The AND #$FE,CCR instruction logically ANDs the immediate 8bit value $FE with the contents of the condition code register and stores the result in the condition code register. A - 34 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ANDI ANDI AND Immediate with Control Register Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR For CCR Operand: S -- Cleared if bit 7 of the immediate operand is cleared L -- Cleared if bit 6 of the immediate operand is cleared E -- Cleared if bit 5 of the immediate operand is cleared U -- Cleared if bit 4 of the immediate operand is cleared N -- Cleared if bit 3 of the immediate operand is cleared Z -- Cleared if bit 2 of the immediate operand is cleared V -- Cleared if bit 1 of the immediate operand is cleared C -- Cleared if bit 0 of the immediate operand is cleared For MR and OMR Operands: The condition codes are not affected using these operands. Instruction Format: AND(I) #xx,D Opcode: 23 0 16 15 0 0 0 0 0 0 0 i 8 i i i i i i i 7 1 0 0 1 1 1 0 E E Instruction Fields: #xx=8-bit Immediate Short Data -- i i i i i i i i D EE MR 0 0 CCR 0 1 OMR 1 0 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 35 INSTRUCTION DESCRIPTIONS ASL ASL Arithmetic Shift Accumulator Left 55 Operation: 47 23 0 C 0 (parallel move) Assembler Syntax: ASL D (parallel move) Description: Arithmetically shift the destination operand D one bit to the left and store the result in the destination accumulator. The MS bit of D prior to instruction execution is shifted into the carry bit C and a zero is shifted into the LS bit of the destination accumulator D. If a zero shift count is specified, the carry bit is cleared. The difference between ASL and LSL is that ASL operates on the entire 56 bits of the accumulator and therefore sets the V bit if the number overflowed. Example: : ASL A : (R3)- ;multiply A by 2, update R3 Before Execution A SR $A5:012345:012345 $0300 After Execution A $4A:02468A:02468A SR $0373 Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $A5:012345:012345. The execution of the ASL A instruction shifts the 56-bit value in the A accumulator one bit to the left and stores the result back in the A accumulator. A - 36 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ASL ASL Arithmetic Shift Accumulator Left Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if limiting (parallel move) or overflow has occurred in result E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Set if bit 55 of A or B result is changed due to left shift C -- Set if bit 55 of A or B was set prior to instruction execution Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ASL D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 1 1 3 d 0 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: D d A B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 37 INSTRUCTION DESCRIPTIONS ASR ASR Arithmetic Shift Accumulator Right 55 47 23 0 Operation: C (parallel move) Assembler Syntax: ASR D (parallel move) Description: Arithmetically shift the destination operand D one bit to the right and store the result in the destination accumulator. The LS bit of D prior to instruction execution is shifted into the carry bit C, and the MS bit of D is held constant. Example: : ASR B : X:-(R3),R3 ;divide B by 2, update R3, load R3 Before Execution After Execution B $A8:A86420:A86421 B $D4:543210:543210 SR $0300 SR $0329 Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $A8:A86420:A86421. The execution of the ASR B instruction shifts the 56-bit value in the B accumulator one bit to the right and stores the result back in the B accumulator. A - 38 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS ASR ASR Arithmetic Shift Accumulator Right Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if data limiting occurs during parallel move E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Always cleared C -- Set if bit 0 of A or B was set prior to instruction execution Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ASR D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 1 0 3 d 0 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: D d A B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 39 INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Operation: D[n] C; D[n] D[n] Assembler Syntax: BCHG #n,X:ea D[n] C; D[n] D[n] BCHG #n,X:aa D[n] C; D[n] D[n] BCHG #n,X:pp D[n] C; D[n] D[n] BCHG #n,Y:ea D[n] C; D[n] D[n] BCHG #n,Y:aa D[n] C; D[n] D[n] BCHG #n,Y:pp D[n] C; D[n] D[n] BCHG #n,D Description: Test the nth bit of the destination operand D, complement it, and store the result in the destination location. The state of the nth bit is stored in the carry bit C of the condition code register. The bit to be tested is selected by an immediate bit number from 0-23. This instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. This instruction provides a testand-change capability which is useful for synchronizing multiple processors using a shared memory. This instruction can use all memory alterable addressing modes. Example: : BCHG : #$7,X:<<$FFE2 ;test and change bit 7 in I/O Port B DDR Before Execution After Execution X:$FFE2 $000000 X;$FFE2 $000080 SR $0300 SR $0300 A - 40 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Explanation of Example: Prior to execution, the 24-bit X location X:$FFE2 (I/O port B data direction register) contains the value $000000. The execution of the BCHG #$7,X:<<$FFE2 instruction tests the state of the 7th bit in X:$FFE2, sets the carry bit C accordingly, and then complements the 7th bit in X:$FFE2. Condition Codes: 15 14 13 12 LF DM T ** MR 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U 3 2 1 0 N Z V C CCR CCR Condition Codes: For destination operand SR: C -- Changed if bit 0 is specified. Not affected otherwise. V -- Changed if bit 1 is specified. Not affected otherwise. Z -- Changed if bit 2 is specified. Not affected otherwise. N -- Changed if bit 3 is specified. Not affected otherwise. U -- Changed if bit 4 is specified. Not affected otherwise. E -- Changed if bit 5 is specified. Not affected otherwise. L -- Changed if bit 6 is specified. Not affected otherwise. S -- Changed if bit 7 is specified. Not affected otherwise. For destination operand A or B: S --Computed according to the definition. See Notes on page A-47. L -- Set if data limiting has occurred. See Notes on page A-47. E -- Not affected U -- Not affected N -- Not affected Z -- Not affected V -- Not affected C -- Set if bit tested is set. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 41 INSTRUCTION DESCRIPTIONS BCHG Bit Test and Change BCHG For other destination operands: S -- Not affected L -- Not affected E -- Not affected U -- Not affected N -- Not affected Z -- Not affected V -- Not affected C -- Set if bit tested is set. Cleared otherwise. MR Status Bits: For destination operand SR: I0 -- Changed if bit 8 is specified. Not affected otherwise. I1 -- Changed if bit 9 is specified. Not affected otherwise. S0 -- Changed if bit 10 is specified. Not affected otherwise. S1 -- Changed if bit 11 is specified. Not affected otherwise. T -- Changed if bit 13 is specified. Not affected otherwise. DM -- Changed if bit 14 is specified. Not affected otherwise LF -- Changed if bit 15 is specified. Not affected otherwise. For other destination operands: I0 -- Not affected I1 -- Not affected S0 -- Not affected S1 -- Not affected T -- Not affected DM -- Not affected LF -- Not affected A - 42 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,X:ea BCHG #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 1 M M M R R 7 R 0 0 S 0 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r r r r r r 0 r r r r r r r 0 0 1 Bit Number bbbbb 00000 * * * 10111 where "rrr" refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 43 INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,X:aa BCHG #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 1 0 8 0 a a a a a a 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 44 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,X:pp BCHG #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 8 0 p p p p p p 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 45 INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 1 D D D D D 8 7 D 0 0 1 0 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller registers 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 D T N F G D D T N F G Bit Number bbbbb D D T N F G 00000 * 10111 See Section A.10 and Table A-18 for specific register encodings. A - 46 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCHG Bit Test and Change BCHG Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4. The resulting 24 bit value is placed back into A1 or B1. A0 or B0 is cleared and the sign of A1 or B1 is extended into A2 or B2. 5. The bit test and change is performed on A1 or B1, and the C bit is set if the bit tested is set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 47 INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Operation: D[n] C; 0 D[n] Assembler Syntax: BCLR #n,X:ea D[n] C; 0 D[n] BCLR #n,X:aa D[n] C; 0 D[n] BCLR #n,X:pp D[n] C; 0 D[n] BCLR #n,Y:ea D[n] C; 0 D[n] BCLR #n,Y:aa D[n] C; 0 D[n] BCLR #n,Y:pp D[n] C; 0 D[n] BCLR #n,D Description: Test the nth bit of the destination operand D, clear it and store the result in the destination location. The state of the nth bit is stored in the carry bit C of the condition code register. The bit to be tested is selected by an immediate bit number from 0-23. This instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. This instruction provides a test-andclear capability which is useful for synchronizing multiple processors using a shared memory. This instruction can use all memory alterable addressing modes. Example: : BCLR : #$E,X:<<$FFE4 ;test and clear bit 14 in I/O Port B Data Reg. Before Execution A - 48 After Execution X:$FFE4 $FFFFFF X:$FFE4 $FFBFFF SR $0300 SR $0301 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Explanation of Example: Prior to execution, the 24-bit X location X:$FFE4 (I/O port B data register) contains the value $FFFFFF. The execution of the BCLR #$E,X:<<$FFE4 instruction tests the state of the 14th bit in X:$FFE4, sets the carry bit C accordingly, and then clears the 14th bit in X:$FFE4. Condition Codes: 15 14 13 12 LF DM T ** MR 11 10 9 8 7 6 5 4 3 2 1 0 S1 S0 I1 I0 S L E U N Z V C CCR CCR Condition Codes: For destination operand SR: C -- Cleared if bit 0 is specified. Not affected otherwise. V -- Cleared if bit 1 is specified. Not affected otherwise. Z -- Cleared if bit 2 is specified. Not affected otherwise. N -- Cleared if bit 3 is specified. Not affected otherwise. U -- Cleared if bit 4 is specified. Not affected otherwise. E -- Cleared if bit 5 is specified. Not affected otherwise. L -- Cleared if bit 6 is specified. Not affected otherwise. S -- Cleared if bit 7 is specified. Not affected otherwise. For destination operand A or B: S --Computed according to the definition. See Notes on page A-55. L -- Set if data limiting has occurred. See Notes on page A-55. E -- Not affected U -- Not affected N -- Not affected Z -- Not affected V -- Not affected C -- Set if bit tested is set. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 49 INSTRUCTION DESCRIPTIONS BCLR Bit Test and Clear BCLR For other destination operands: C -- Set if bit tested is set. Cleared otherwise. V -- Not affected Z -- Not affected N -- Not affected U -- Not affected E -- Not affected L -- Not affected S -- Not affected MR Status Bits: For destination operand SR: I0 -- Cleared if bit 8 is specified. Not affected otherwise. I1 -- Cleared if bit 9 is specified. Not affected otherwise. S0 -- Cleared if bit 10 is specified. Not affected otherwise. S1 -- Cleared if bit 11 is specified. Not affected otherwise. T -- Cleared if bit 13 is specified. Not affected otherwise. DM -- Cleared if bit 14 is specified. Not affected otherwise LF -- Cleared if bit 15 is specified. Not affected otherwise. For other destination operands: I0 -- Not affected I1 -- Not affected S0 -- Not affected S1 -- Not affected T -- Not affected DM -- Not affected LF -- Not affected A - 50 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,X:ea BCLR #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 8 1 M M M R R 7 R 0 0 S 0 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r r r r r r 0 r r r r r r r 0 0 1 Bit Number bbbbb 00000 * * * 10111 where "rrr" refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 51 INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,X:aa BCLR #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 0 0 8 0 a a a a a a 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 52 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,X:pp BCLR #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 0 p p p p p p 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 53 INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 1 D D D D D D 7 0 0 1 0 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller registers 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 D T N F G D D T N F G Bit Number bbbbb D D T N F G 00000 * 10111 See Section A.10 and Table A-18 for specific register encodings. A - 54 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BCLR Bit Test and Clear BCLR Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4. The resulting 24 bit value is placed back into A1 or B1. A0 or B0 is cleared and the sign of A1 or B1 is extended into A2 or B2. 5. The bit test and clear is performed on A1 or B1, and the C bit is set if the bit tested is set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 55 INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Operation: D[n] C; 1 D[n] Assembler Syntax: BSET #n,X:ea D[n] C; 1 D[n] BSET #n,X:aa D[n] C; 1 D[n] BSET #n,X:pp D[n] C; 1 D[n] BSET #n,Y:ea D[n] C; 1 D[n] BSET #n,Y:aa D[n] C; 1 D[n] BSET #n,Y:pp D[n] C; 1 D[n] BSET #n,D Description: Test the nth bit of the destination operand D, set it, and store the result in the destination location. The state of the nth bit is stored in the carry bit C of the condition code register. The bit to be tested is selected by an immediate bit number from 0-23. This instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. This instruction provides a test-andset capability which is useful for synchronizing multiple processors using a shared memory. This instruction can use all memory alterable addressing modes. Example: : BSET : #$0,X:<<$FFE5 ;test and clear bit 14 in I/O Port B Data Reg. Before Execution After Execution X:$FFE5 $000000 X:$FFE5 $000001 SR $0300 SR $0300 A - 56 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Explanation of Example: Prior to execution, the 24-bit X location X:$FFE5 (I/O port C data register) contains the value $000000. The execution of the BSET #$0,X:<<$FFE5 instruction tests the state of the 0th bit in X:$FFE5, sets the carry bit C accordingly, and then sets the 0th bit in X:$FFE5. Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR CCR Condition Codes: For destination operand SR: C -- Set if bit 0 is specified. Not affected otherwise. V -- Set if bit 1 is specified. Not affected otherwise. Z -- Set if bit 2 is specified. Not affected otherwise. N -- Set if bit 3 is specified. Not affected otherwise. U -- Set if bit 4 is specified. Not affected otherwise. E -- Set if bit 5 is specified. Not affected otherwise. L -- Set if bit 6 is specified. Not affected otherwise. S -- Set if bit 7 is specified. Not affected otherwise. For destination operand A or B: S --Computed according to the definition. See Notes on page A-63. L -- Set if data limiting has occurred. See Notes on page A-63. E -- Not affected U -- Not affected N -- Not affected Z -- Not affected V -- Not affected C -- Set if bit tested is set. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 57 INSTRUCTION DESCRIPTIONS BSET Bit Test and Set For other destination operands: C -- Set if bit tested is set. Cleared otherwise. V -- Not affected Z -- Not affected N -- Not affected U -- Not affected E -- Not affected L -- Not affected S -- Not affected MR Status Bits: For destination operand SR: I0 -- Set if bit 8 is specified. Not affected otherwise. I1 -- Set if bit 9 is specified. Not affected otherwise. S0 -- Set if bit 10 is specified. Not affected otherwise. S1 -- Set if bit 11 is specified. Not affected otherwise. T -- Set if bit 13 is specified. Not affected otherwise. DM -- Set if bit 14 is specified. Not affected otherwise LF -- Set if bit 15 is specified. Not affected otherwise. For other destination operands: I0 -- Not affected I1 -- Not affected S0 -- Not affected S1 -- Not affected T -- Not affected DM -- Not affected LF -- Not affected A - 58 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,X:ea BSET #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 8 1 M M M R R 7 R 0 0 S 1 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r r r r r r 0 r r r r r r r 0 0 1 Bit Number bbbbb 00000 * * * 10111 where "rrr" refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 59 INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,X:aa BSET #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 0 0 8 0 a a a a a a 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 60 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,X:pp BSET #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 0 p p p p p p 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 61 INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 1 D D D D D D 7 0 0 1 1 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller registers 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 D T N F G D D T N F G Bit Number bbbbb D D T N F G 00000 * 10111 See Section A.10 and Table A-18 for specific register encodings. A - 62 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4. The resulting 24 bit value is placed back into A1 or B1. A0 or B0 is cleared and the sign of A1 or B1 is extended into A2 or B2. 5. The bit test and set is performed on A1 or B1, and the C bit is set if the bit tested is set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 63 INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Operation: D[n] C; Assembler Syntax: BTST #n,X:ea D[n] C; BTST #n,X:aa D[n] C; BTST #n,X:pp D[n] C; BTST #n,Y:ea D[n] C; BTST #n,Y:aa D[n] C; BTST #n,Y:pp BTST #n,D D[n] C; th Description: Test the n bit of the destination operand D. The state of the nth bit is stored in the carry bit C of the condition code register. The bit to be tested is selected by an immediate bit number from 0-23. This instruction is useful for performing serial to parallel conversion when used with the appropriate rotate instructions. This instruction can use all memory alterable addressing modes. Example: : BTST ROL : #$0,X:<<$FFEE A ;read SSI serial input flag IF1 into C bit ;rotate carry bit C into LSB of A1 Before Execution X:$FFEE SR After Execution $000002 X:$FFEE $000002 $0300 SR $0301 Explanation of Example: Prior to execution, the 24-bit X location X:$FFEE (I/O SSI status register) contains the value $000002. The execution of the BTST #$1,X:<<$FFEE instruction tests the state of the 1st bit (serial input flag IF1) in X:$FFEE and sets the carry bit C accordingly. This instruction sequence illustrates serial to parallel conversion using the carry bit C and the 24-bit A1 register. A - 64 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR CCR Condition Codes: For destination operand A or B: C -- Set if bit tested is set. Cleared otherwise. V -- Not affected Z -- Not affected N -- Not affected U -- Not affected E -- Not affected L -- Set if data limiting has occurred. See Notes on page A-69. S -- Computed according to the definition. See Notes on page A-69. For other destination operands: C -- Set if bit tested is set. Cleared otherwise. V -- Not affected Z -- Not affected N -- Not affected U -- Not affected E -- Not affected L -- Not affected S -- Not affected MR Status bits are not affected. SP -- Stack Pointer: For destination operand SSH: SP -- Decrement by 1. For other destination operands: Not affected MOTOROLA INSTRUCTION SET DETAILS A - 65 INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,X:ea BTST #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 1 M M M R R 7 R 0 0 S 1 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r r r r r r 0 r r r r r r r 0 0 1 Bit Number bbbbb 00000 * * * 10111 where "rrr" refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 66 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,X:aa BTST #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 1 0 8 0 a a a a a a 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 67 INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,X:pp BTST #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 8 0 p p p p p p 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory * * 0 1 Bit Number bbbbb 00000 * 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 68 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 8 1 D D D D D D 7 0 0 1 1 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD, xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller registers 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 D T N F G D D T N F G Bit Number bbbbb D D T N F G 00000 * 10111 See Section A.10 and Table A-18 for specific register encodings. Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4. The bit test is performed on the resulting 24-bit value and the C bit is set if the bit tested is set. The original contents of A or B are not changed. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 69 INSTRUCTION DESCRIPTIONS CLR CLR Clear Accumulator Operation: 0 D (parallel move) Assembler Syntax: CLR D (parallel move) Description: Clear the destination accumulator. This is a 56-bit clear instruction. Example: : CLR A : #$7F,N ;clear A, set up N0 addr. reg. Before Execution After Execution A $12:345678:9ABCDE A $00:000000:000000 Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $12:345678:9ABCDE. The execution of the CLR A instruction clears the 56-bit A accumulator to zero. Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if data limiting has occurred during parallel move E -- Always cleared U -- Always set N -- Always cleared Z-- Always set V -- Always cleared A - 70 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS CLR CLR Clear Accumulator Instruction Format: CLR D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 0 1 3 d 0 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: D d A B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 71 INSTRUCTION DESCRIPTIONS CMP CMP Compare Operation: S2 - S1(parallel move) Assembler Syntax: CMP S1, S2 (parallel move) Description: Subtract the source one operand, S1, from the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored. Note: This instruction subtracts 56-bit operands. When a word is specified as S1, it is sign extended and zero filled to form a valid 56-bit operand. For the carry to be set correctly as a result of the subtraction, S2 must be properly sign extended. S2 can be improperly sign extended by writing A1 or B1 explicitly prior to executing the compare so that A2 or B2, respectively, may not represent the correct sign extension. This note particularly applies to the case where it is extended to compare 24-bit operands such as X0 with A1. Example: : CMP Y0,B : X0,X:(R6)+N6 Y1,Y:(R0)- Before Execution ;comp. Y0 and B, save X0, Y1 After Execution B $00:000020:000000 B Y0 $000024 Y0 $000024 SR $0300 SR $0319 $00:000020:000000 Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $00:000020:000000 and the 24-bit Y0 register contains the value $000024. The execution of the CMP Y0,B instruction automatically appends the 24-bit value in the Y0 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, subtracts the result from the 56-bit B accumulator and updates the condition code register. A - 72 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS CMP CMP Compare Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if limiting (parallel move) or overflow has occurred in result E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Set if overflow has occurred in A or B result C -- Set if a carry (or borrow) occurs from bit 55 of A or B result. Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: CMP S1, S2 Opcode: 23 8 7 0 DATA BUS MOVE FIELD 4 J J J 3 d 0 1 0 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S1,S2 JJJd B,A A,B X0,A X0,B Y0,A 0000 0001 1000 1001 1010 S1,S2 JJJd Y0,B X1,A X1,B Y1,A Y1,B 1011 1100 1101 1110 1111 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 73 INSTRUCTION DESCRIPTIONS CMPM CMPM Compare Magnitude Operation: |S2| - |S1|(parallel move) Assembler Syntax: CMPM S1, S2 (parallel move) Description: Subtract the absolute value (magnitude) of the source one operand, S1, from the absolute value of the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored. Note: This instruction subtracts 56-bit operands. When a word is specified as S1, it is sign extended and zero filled to form a valid 56-bit operand. For the carry to be set correctly as a result of the subtraction, S2 must be properly sign extended. S2 can be improperly sign extended by writing A1 or B1 explicitly prior to executing the compare so that A2 or B2, respectively, may not represent the correct sign extension. This note particularly applies to the case where it is extended to compare 24-bit operands such as X0 with A1. Example: : CMPM X1,A : BA,L:-(R4) ;comp. Y0 and B, save X0, Y1 Before Execution After Execution A $00:000006:000000 A X1 $FFFFF7 X1 $FFFFF7 SR $0300 SR $0319 $00:000006:000000 Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $00:000006:000000, and the 24-bit X1 register contains the value $FFFFF7. The execution of the CMPM X1,A instruction automatically appends the 24-bit value in the X1 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, takes the absolute value of the resulting 56-bit number, subtracts the result from the absolute value of the contents of the 56-bit A accumulator, and updates the condition code register. A - 74 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS CMPM CMPM Compare Magnitude Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S -- Computed according to the definition in A.5 CONDITION CODE COMPUTATION L -- Set if data limiting has occurred during a parallel move E -- Set if the signed integer portion of A or B result is in use U -- Set if A or B result is unnormalized N -- Set if bit 55 of A or B result is set Z-- Set if A or B result equals zero V -- Set if overflow has occurred in A or B result C -- Set if a carry (or borrow) occurs from bit 55 of A or B result. Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: CMPM S1, S2 Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 J J J 3 d 0 1 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S1,S2 J J J d B,A 0 0 0 0 A,B 0 0 0 1 X0,A 1 0 0 0 S1,S2 J J J d X0,B 1 0 0 1 Y0,A 1 0 1 0 Y0,B 1 0 1 1 S1,S2 J J J d X1,A X1,B Y1,A Y1,B 1100 1101 1110 1111 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 75 INSTRUCTION DESCRIPTIONS DEBUG DEBUG Enter Debug Mode Operation: Assembler Syntax: Enter the debug mode DEBUG Description: Enter the debug mode and wait for OnCE commands. Example: : DEBUG ;enter the debug mode : Explanation of Example: Upon executing the DEBUG instruction, the chip enters the debug mode after the instruction following the DEBUG instruction has entered the instruction latch. Entering the debug mode is acknowledged by the chip by pulsing low the DSO line. This informs the external command controller that the chip has entered the debug mode and is waiting for commands. Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR The condition codes are not affected by this instruction Instruction Format: DEBUG A - 76 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS DEBUG DEBUG Enter Debug Mode Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 1 0 7 0 0 0 0 0 0 0 0 0 Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 77 INSTRUCTION DESCRIPTIONS DEBUGcc DEBUGcc Enter Debug Mode Conditionally Operation: Assembler Syntax: If cc, then enter the debug mode DEBUGcc Description: If the specified condition is true, enter the debug mode and wait for OnCE commands. If the specified condition is false, continue with the next instruction. The term "cc" may specify the following conditions: "cc" Mnemonic -- carry clear (higher or same) -- carry set (lower) -- extension clear -- equal -- extension set -- greater than or equal -- greater than -- limit clear -- less than or equal -- limit set -- less than -- minus -- not equal -- normalized -- plus -- not normalized CC (HS) CS (LO) EC EQ ES GE GT LC LE LS LT MI NE NR PL NN Condition C=0 C=1 E=0 Z=1 E=1 N V=0 Z+(N V)=0 L=0 Z+(N V)=1 L=1 N V=1 N=1 Z=0 Z+(U*E)=1 N=0 Z+(U*E)=0 where U denotes the logical complement of U, + denotes the logical OR operator, * denotes the logical AND operator, and denotes the logical Exclusive OR operator Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR The condition codes are not affected by this instruction. A - 78 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS DEBUGcc DEBUGcc Enter Debug Mode Conditionally Example: : CMP Y0, DEBUGge B ; Compare register Y0 with the B accumulator. ; Enter the debug mode if ; the previous test result is "greater than". : Explanation of Example: The results of the comparison between Y0 and B will be recorded in the status register bits. The conditional debug instruction looks at the conditions (for greater than or equal in this case) and if they are met (N V=0) then the DEBUG instruction will be executed. The chip enters the debug mode after the instruction following the DEBUG instruction has entered the instruction latch. The chip pulses low the DSO line to inform the external command controller that it has entered the debug mode and that the chip is waiting for commands. Instruction Format: DEBUGcc Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 1 7 1 0 0 0 0 0 c c c c Instruction Fields: Mnemonic c c c c Mnemonic c c c c CC (HS) GE NE PL NN EC LC GT 0 0 0 0 0 0 0 0 CS (LO) LT EQ MI NR ES LS LE 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 79 INSTRUCTION DESCRIPTIONS DEC DEC Decrement by One Operation: D-1 D Assembler Syntax: DEC D Description: Decrement by one the specified operand and store the result in the destination accumulator. One is subtracted from the LSB of D. Example: : DEC A ;Decrement the content of A accumulator by one : Explanation of Example: One is subtracted from the content of the A accumulator. Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR L -- Set if overflow has occurred in result. Not affected otherwise E -- Set if the signed integer portion of result is in use U-- Set if result is unnormalized N -- Set if bit 55 of result is set Z -- Set if result equals zero V -- Set if overflow has occurred in result C -- Set if a borrow occurs from bit 55 of result A - 80 INSTRUCTION SET DETAILS MOTOROLA INSTRUCTION DESCRIPTIONS DEC DEC Decrement by One Instruction Format: DEC D Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 7 0 0 0 0 0 1 0 1 d Instruction Fields: D d A B 0 1 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 81