T6818-TUSY - Atmel Corporation

4530I–AUTO–05/12

Features

●Supply voltage up to 40V

●RDSon typically 0.5Ω at 25°C, maximum 1.1Ω at 150°C

●Up to 1.5A output current

●Three half-bridge outputs formed by three high-side and three low-side drivers

●Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors

and inductors

●No shoot-through current

●Very low quiescent current IS < 2µA in Standby Mode versus total temperature

range

●Outputs short-circuit protected

●Overtemperature protection for each switch and overtemperature prewarning

●Undervoltage protection

●Various diagnostic functions such as shorted output, open-load, overtemperature

and power-supply fail detection

●Serial data interface, Daisy Chain capable, up to 2MHz clock frequency

●SO14 power package

Atmel T6818

Triple Half- bridge DMOS Output Driver with Serial Input

Control

DATASHEET

2Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

1. Description

The Atmel® T6818 is a fully protected driver interface designed in 0.8-µm BCDMOS technology. They are used to control up to

3 different loads by a microcontroller in automotive and industrial applications.

Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A. The drivers are internally connected to

form 3 half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as

bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the application of H-bridges to

drive DC motors.

Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions

and a very low quiescent current in stand-by-mode opens a wide range of applications. Automotive qualification (protection

against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for

exacting requirements of automotive applications.

Figure 1-1. Block Diagram

CLK

INH

protection

Serial interface

Input register

Output register

Sn.n. n. n.n.n.

u. H

OUT3

VCC

Thermal

protection

Control

logic Power-on

reset

Charge

pump

OUT2 OUT1

n.n.

GND

u. u. u. u. u. u. u. 3

21213

GND

Fault

detect

Fault

detect

Fault

detect

Fault

detect Fault

detect

3Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

2. Pin Configuration

Figure 2-1. Pinning SO14

Table 2-1. Pin Description

Pin Symbol Function

1GND T6818: ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab

2OUT3

Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-side

switch 3 with internal reverse diodes; short circuit protection; overtemperature protection;

diagnosis for short and open load

3VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply

4CS Chip select input; 5-V CMOS logic level input with internal pull up;

low = serial communication is enabled, high = disabled

5DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from

the control device; DI expects a 16-bit control word with LSB being transferred first

6CLK Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input

interface and internal shift register (fmax = 2MHz)

7GND Ground; see pin 1

8GND Ground; see pin 1

9DO

Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends

16-bit status information to the microcontroller (LSB is transferred first); output will remain

tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data

output line only.

10 INH Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation

11 VCC Logic supply voltage (5V)

12 OUT2 Half-bridge output 2; see pin 2

13 OUT1 Half-bridge output 1; see pin 2

14 GND Ground; see pin 1

GND

OUT3

CLK

GND

OUT1

OUT2

VCC

INH

GND

4Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

3. Functional Description

3.1 Serial Interface

Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the

falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising

edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output

data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP)

is transferred first.

Figure 3-1. Data Transfer

Table 3-1. Input Data Protocol

Bit Input Register Function

0SRR Status register reset (high = reset; the bits PSF, OPL and SCD in the output data

1LS1 Controls output LS1 (high = switch output LS1 on)

2HS1 Controls output HS1 (high = switch output HS1 on)

3LS2 See LS1

4HS2 See HS1

5LS3 See LS1

6HS3 See HS1

7n. u. Not used

8n. u. Not used

9n. u. Not used

10 n. u. Not used

11 n. u. Not used

12 n. u. Not used

13 OCS Overcurrent shutdown (high = overcurrent shutdown is active)

14 n. u. Not used

15 n. u. Not used

SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u.

CLK

DO TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. SCD OPL PSF

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

5Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

Table 3-2. Output Data Protocol

Bit

Output (Status)

0TP Temperature prewarning: high = warning

1Status LS1 High = output is on, low = output is off; not affected by SRR

2Status HS1 High = output is on, low = output is off; not affected by SRR

3Status LS2 Description see LS1

4Status HS2 Description see HS1

5Status LS3 Description see LS1

6Status HS3 Description see HS1

7n. u. Not used

8n. u. Not used

9n. u. Not used

10 n. u. Not used

11 n. u. Not used

12 n. u. Not used

13 SCD

Short circuit detected: set high when at least one high-side or low-side switch is

switched off by a short-circuit condition. Bits 1 to 6 can be used to detect the shorted

switch.

14 OPL Open load detected: set high, when at least one active high-side or low-side switch

sinks/sources a current below the open load threshold current.

15 PSF Power-supply fail: undervoltage at pin VS detected

After power-on reset, the input register has the following status:

Bit 15 Bit 14 Bit 13

(OCS)

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

x x H x x x x x x L L L L L L L

The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal

operation.

Bit 15 Bit 14 Bit 13

(OCS)

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6

(HS3)

Bit 5

(LS3)

Bit 4

(HS2)

Bit 3

(LS2)

Bit 2

(HS1)

Bit 1

(LS1)

Bit 0

(SRR)

H H H H H L L L L L L L L L L L

H H H L L H H L L L L L L L L L

H H H L L L L H H L L L L L L L

6Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

3.2 Power-supply Fail

In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To

detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled

immediately when supply voltage recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the

input register.

3.3 Open-load Detection

If the current through a high-side or low-side switch in ON-state stays below the open-load detection threshold, the open-load

detection bit (OPL) in the output register is set.

The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open load, its duration has to last longer

than the open-load detection delay time tdSd.

3.4 Overtemperature Protection

If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, TjPW set, the temperature

prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset,

the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin

DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is

interrupted without affecting the status of input and output registers.

If the junction temperature of one or more output stages exceeds the thermal shutdown threshold, Tj switch off, all outputs are

disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the

temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis

of thermal prewarning and shutdown threshold avoids oscillations.

3.5 Short-circuit Protection

The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS bit in the

input register. When the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off

after a delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set

to low. For OCS = low the overcurrent shutdown is inactive. The SCD bit is also set if the current exceeds the overcurrent

limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD

bit is reset and the disabled outputs are enabled.

3.6 Inhibit

0 V applied to pin 10 (INH) inhibits the Atmel® T6818.

All output switches are then turned off and switched to tri-state. The data in the output register are deleted. The current

consumption is reduced to less than 5 µA at pin VS and less than 25µA at pin VCC. The output switches can be activated again

by switching pin 10 (INH) to 5V which initiates an internal power-on reset.

7Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

Note: 1. Threshold for undervoltage detection

4. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

All values refer to GND pins.

Parameters Pin Symbol Value Unit

Supply voltage 3 VVS –0.3 to +40 V

Supply voltage

t < 0.5 s; IS > –2 A 3 VVS –1 V

Logic supply voltage 11 VVCC –0.3 to +7 V

Logic input voltage 4 to 6, 10 VCS,VDI, VCLK, VINH –0.3 to VVCC+0.3 V

Logic output voltage 9 VDO –0.3 to VVCC+0.3 V

Input current 4 to 6, 10 ICS,IDI, ICLK, IINH –10 to +10 mA

Output current 9 IDO –10 to +10 mA

Output current 2, 12 and 13 IOut3, IOut2, IOut1 Internally limited, see output specification

Output voltage 2, 12 and 13 IOut3, IOut2, IOut1 –0.3 to +40 V

Reverse conducting current

(tpulse = 150 µs)

2, 12 and 13

towards pin 3 IOut3, IOut2, IOut1 17 A

Junction temperature range TJ–40 to +150 °C

Storage temperature range TSTG –55 to +150 °C

5. Thermal Resistance

Parameters Test Conditions Symbol Value Unit

T6818

Junction pin Measured to GND

Pins 1, 7, 8 and 14 RthJP 30 K/W

Junction ambient RthJA 65 K/W

6. Operating Range

Parameters Symbol Value Unit

Supply voltage VVS VUV(1) to 40 V

Logic supply voltage VVCC 4.75 to 5.25 V

Logic input voltage VCS,VDI, VCLK, VINH –0.3 to VVCC V

Serial interface clock frequency fCLK 2MHz

Junction temperature range Tj–40 to +150 °C

8Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

Note: 1. Test pulse 5: Vsmax = 40 V

7. Noise and Surge Immunity

Parameters Test Conditions Value

Conducted interferences ISO 7637-1 Level 4(1)

Interference suppression VDE 0879 Part 2 Level 5

ESD (Human Body Model) ESD S 5.1 2 kV

ESD (Machine Model) JEDEC A115A 200 V

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1Current Consumption

1.1 Quiescent current VS VVS < 20V, INH = low 3 IVS 1 2 µA A

1.2 Quiescent current

VCC

4.75V < VVCC < 5.25V,

INH = low 11 IVCC 15 25 µA A

1.3 Supply current VS

VVS < 20V normal

operating, all outputs

off

3 IVS 4 6 mA A

1.4 Supply current VCC 4.75V < VVCC < 5.25V,

normal operating 11 IVCC 350 500 µA A

1.5 Discharge current VS VVS = 32.5V,

INH = low 3 IVS 0.5 5.5 mA A

1.6 Discharge current VS VVS = 40V,

INH = low 3 IVS 2.5 10 mA A

2Undervoltage Detection, Power-on Reset

2.1 Power-on reset

threshold 11 VVCC 3.2 3.9 4.4 V A

2.2 Power-on reset

delay time After switching on VCC tdPor 30 95 190 µs A

2.3 Undervoltage-

detection threshold VCC = 5V 3 VUv 5.6 7.0 V A

2.4 Undervoltage-

detection hysteresis VCC = 5V 3 ΔVUv 0.6 V A

2.5 Undervoltage-

detection delay time tdUV 10 40 µs A

3Thermal Prewarning and Shutdown

3.1 Thermal prewarning

set TjPW set 120 145 170 °C B

3.2 Thermal prewarning

reset TjPW reset 105 130 155 °C B

3.3 Thermal prewarning

hysteresis ΔTjPW 15 °C B

3.4 Thermal shutdown off Tj switch off 150 175 200 °C B

3.5 Thermal shutdown on Tj switch on 135 160 185 °C B

3.6 Thermal shutdown

hysteresis ΔTj switch off 15 °C B

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of

final level. Device not in standby for t > 1 ms

9Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

3.7

Ratio thermal

shutdown off/thermal

prewarning set

Tj switch off/

TjPW set

1.05 1.2 B

3.8

Ratio thermal

shutdown on/thermal

prewarning reset

Tj switch on/

TjPW reset

1.05 1.2 B

4Output Specification (OUT1-OUT3)

4.1

On resistance

IOut 1-3 = –1.3A 2, 12,

13 RDSOn1-3 1.1 ΩA

4.2 IOut 1-3 = 1.3A 2, 12,

13 RDSOn1-3 1.1 ΩA

4.3 High-side output

leakage current

VOut 1-3 = 0V,

output stages off

2, 12,

13 IOut1-3 –15 µA A

4.4 Low-side output

leakage current

VOut 1-3 = VVS,

output stages off

2, 12,

13 IOut1-3 200 µA A

4.5

High-side switch

reverse diode forward

voltage

IOut 1-3 = 1.5A 2, 12,

13 VOut1-3

– VVS 1.5 V A

4.6

Low-side switch

reverse diode forward

voltage

IOut 1-3 = –1.5A 2, 12,

13 VOut 1-3 –1.5 V A

4.7

High-side overcurrent

limitation and

shutdown threshold

2, 12,

13 IOut1-3 –2.5 –2 –1.5 A A

4.8

Low-side overcurrent

limitation and

shutdown threshold

2, 12,

13 IOut1-3 1.5 22.5 A A

4.9 Overcurrent shutdown

delay time tdSd 10 40 µs A

4.10 High-side open-load

detection threshold

2, 12,

13 IOut1-3 –45 –30 –15 mA A

4.11 Low-side open-load

detection threshold

2, 12,

13 IOut1-3 15 30 45 mA A

4.12 Open-load detection

delay time tdSd 200 600 µs A

4.13 High-side output

switch on delay(1)

VVS = 13V

RLoad = 30Ωtdon 20 µs A

4.14 Low-side output switch

on delay(1)

VVS = 13 V

RLoad = 30Ωtdon 20 µs A

4.15 High-side output

switch off delay(1)

VVS = 13V

RLoad = 30Ωtdoff 20 µs A

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of

final level. Device not in standby for t > 1 ms

10Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

4.16 Low-side output switch

off delay(1)

VVS = 13 V

RLoad = 30Ωtdoff 3µs A

4.17

Dead time between

corresponding high-

and low-side switches

VVS = 13V

RLoad = 30Ωtdon – tdoff 1µs A

5Logic Inputs DI, CLK, CS, INH

5.1 Input voltage low-level

threshold

4-6,

10 VIL

0.3 ×

VVCC

V A

5.2 Input voltage high-

level threshold

4-6,

10 VIH

0.7 ×

VVCC

V A

5.3 Hysteresis of input

voltage

4-6,

10 ΔVI50 700 mV B

5.4 Pull-down current pin

DI, CLK, INH VDI, VCLK, VINH = VCC

5, 6,

10 IPD 10 65 µA A

5.5 Pull-up current

Pin CS VCS = 0V 4 IPU –65 –10 µA A

6Serial Interface – Logic Output DO

6.1 Output-voltage low

level IDOL = 2mA 9 VDOL 0.4 V A

6.2 Output-voltage high

level IDOL = –2mA 9 VDOH

VVCC –

0.7 V V A

6.3 Leakage current

(tri-state)

VCS = VCC

0V < VDO < VVCC

9 IDO –10 10 µA A

7Inhibit Input — Timing

7.1

Delay time from

standby to normal

operation

tdINH 100 µs A

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of

final level. Device not in standby for t > 1 ms

11Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

9. Serial Interface – Timing

No. Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type*

8.1 DO enable after

CS falling edge CDO = 100pF 9 1 tENDO 200 ns D

8.2 DO disable after

CS rising edge CDO = 100pF 9 2 tDISDO 200 ns D

8.3 DO fall time CDO = 100pF 9 – tDOf 100 ns D

8.4 DO rise time CDO = 100pF 9 – tDOr 100 ns D

8.5 DO valid time CDO = 100pF 910 tDOVal 200 ns D

8.6 CS setup time 4 4 tCSSethl 225 ns D

8.7 CS setup time 4 8 tCSSetlh 225 ns D

8.8 CS high time 4 9 tCSh 500 ns D

8.9 CLK high time 6 5 tCLKh 225 ns D

8.10 CLK low time 6 6 tCLKl 225 ns D

8.11 CLK period time 6 – tCLKp 500 ns D

8.12 CLK setup time 6 7 tCLKSethl 225 ns D

8.13 CLK setup time 6 3 tCLKSetlh 225 ns D

8.14 DI setup time 511 tDIset 40 ns D

8.15 DI hold time 512 tDIHold 40 ns D

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. See Figure 9-1 on page 12

12Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

Figure 9-1. Serial Interface Timing with Chart Numbers

1 2

CLK

10 12

Inputs DI, CLK, CS: High level = 0.7 V

, low level = 0.3 V

Output DO: High level = 0.8 V

, low level = 0.2 V

13Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

10. Application Circuit

Figure 10-1. Application Circuit

10.1 Application Notes

It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND

pins.

Recommended value for capacitors at VS:

Electrolytic capacitor C > 22µF in parallel with a ceramic capacitor C = 100nF. Value for electrolytic capacitor depends on

external loads, conducted interferences and reverse conducting current IOut1,2,3 (see “Absolute Maximum Ratings” on page 7).

Recommended value for capacitors at VCC:

Electrolytic capacitor C > 10µF in parallel with a ceramic capacitor C = 100nF. To reduce thermal resistance it is recommended

to place cooling areas on the PCB as close as possible to the GND pins. Negative spikes at the output pins (e.g. negative

spikes caused by an inductive load switched off with a high side driver) may activate the overtemperature protection function of

the Atmel® T6818. In this condition, all outputs will be switched off simultaneously. If this behavior is not acceptable or

compatible with your application functionally, it is necessary, that for switching on required outputs again, the SRR bit (Status

CLK

INH

CS UV

protection

Serial interface

Input register

Output register

Sn.n. n. n.n.n.

u. H

OUT3

VCC

Thermal

protection

Control

logic Power-on

reset

Charge

pump

OUT2 OUT1

n.n.

GND

u. u. u. u. u. u. u.

21213

GND

Fault

detect

Fault

detect

Fault

detect

Fault

detect

Fault

detect

Fault

detect

5 V

13 V

BYT41D

Batt

Microcontroller

U5021M

Watchdog

Reset

Trigger

Enable

14Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

12. Package Information

11. Ordering Information

Extended Type Number Package Remarks

T6818-TUSY SO14 Power package, tubed, lead-free

T6818-TUQY SO14 Power package, taped and reeled, lead-free

Package Drawing Contact:

packagedrawings@atmel.com

GPC DRAWING NO.

REV. TITLE

6.541-5053.01-4 1

04/13/12

Package: SO14

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN NOM MAXSymbol

Dimensions in mm

specifications

according to DIN

technical drawings

0.18 0.250.10A1

8.65 8.758.55D1)

Note1): Dimensions “D” and “E1” do not include Moldflash or protrusion.

(MAX. 0.15mm per side)

Bemerkung: ASE

6.00 6.205.80E

0.84 1.270.40L

1.27 BSC

3.90 4.003.80E1)

0.22 0.250.19C

0.42 0.510.33b

1.38 1.501.25A2

1.55 1.751.35A

14 8

15Atmel T6818 [DATASHEET]

4530I–AUTO–05/12

13. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this

document.

Revision No. History

4530I-AUTO-05/12 • Section 12 “Package Information” on page 14 changed

4530H-BCD-09/09

• Complete datasheet: ATA6828 part removed

• Features on page 1 changed

• Section 8 “Electrical Characteristics number 1.1 on page 8 changed

4530G-BCD-09/05

• Complete datasheet: T6828 changed in ATA6828

• Ordering Information on page 14 changed

• Package drawing on page 15 changed

4530F-BCD-03/05 • Lead-free Logo on page 1 added

• Table “Ordering Information” on page 14 changed

4530E-BCD-07/04 • Table “Ordering Information” on page 14 changed

4530D-BCD-04/04 • Features on page 1 changed

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