General Description
The MAX1533/MAX1537 are dual step-down, switch-
mode power-supply (SMPS) controllers with synchro-
nous rectification, intended for main 5V/3.3V power
generation in battery-powered systems. Fixed-frequen-
cy operation with optimal interleaving minimizes input
ripple current from the lowest input voltages up to the
26V maximum input. Optimal 40/60 interleaving allows
the input voltage to go down to 8.3V before duty-cycle
overlap occurs, compared to 180°out-of-phase regula-
tors where the duty-cycle overlap occurs when the
input drops below 10V. Output current sensing pro-
vides accurate current limit using a sense resistor.
Alternatively, power dissipation can be reduced using
lossless inductor current sensing.
Internal 5V and 3.3V linear regulators power the
MAX1533/MAX1537 and their gate drivers, as well as
external keep-alive loads, up to a total of 100mA. When
the main PWM regulators are in regulation, automatic
bootstrap switches bypass the internal linear regulators,
providing currents up to 200mA from each linear output.
An additional 5V to 23V adjustable internal 150mA linear
regulator is typically used with a secondary winding to
provide a 12V supply.
The MAX1533/MAX1537 include on-board power-up
sequencing, a power-good (PGOOD) output, digital
soft-start, and internal soft-shutdown output discharge
that prevents negative voltages on shutdown. The
MAX1533 is available in a 32-pin 5mm x 5mm thin QFN
package, and the MAX1537 is available in a 36-pin
6mm x 6mm thin QFN package. The exposed backside
pad improves thermal characteristics for demanding
linear keep-alive applications.
Applications
2 to 4 Li+ Cells Battery-Powered Devices
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
Features
♦Fixed-Frequency, Current-Mode Control
♦40/60 Optimal Interleaving
♦Accurate Differential Current-Sense Inputs
♦Internal 5V and 3.3V Linear Regulators with
100mA Load Capability
♦Auxiliary 12V or Adjustable 150mA Linear
Regulator (MAX1537 Only)
♦Dual-Mode™ Feedback—3.3V/5V Fixed or
Adjustable Output (Dual Mode) Voltages
♦200kHz/300kHz/500kHz Switching Frequency
♦Versatile Power-Up Sequencing
♦Adjustable Overvoltage and Undervoltage
Protection
♦6V to 26V Input Range
♦2V ±0.75% Reference Output
♦Power-Good Output
♦Soft-Shutdown
♦5µA (typ) Shutdown Current
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
________________________________________________________________ Maxim Integrated Products 1
32 31 30 29 28 27 26
9 101112131415
18
19
20
21
22
23
24
7
6
5
4
3
2
1
MAX1533
THIN QFN
5mm x 5mm
TOP VIEW
ON3
ON5
FSEL
ILIM3
ILIM5
REF
GND
8
VCC
SHDN
DH5
BST5
LX5
IN
CSH5
25
CSL5
FB5
LDO5
DL5
PGND
DL3
LDO3
FB3
17 CSL3
OVP
LX3
16
CSH3
BST3
DH3
UVP
PGOOD
PGDLY
SKIP
Pin Configurations
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1533ETJ
-40°C to +85°C
32 Thin QFN 5mm x 5mm
MAX1533ETJ+
-40°C to +85°C
32 Thin QFN 5mm x 5mm
MAX1537ETX
-40°C to +85°C
36 Thin QFN 6mm x 6mm
MAX1537ETX+
-40°C to +85°C
36 Thin QFN 6mm x 6mm
19-3501; Rev 0; 11/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Dual Mode is a trademark of Maxim Integrated Products, Inc. Pin Configurations continued at end of data sheet.
+Denotes lead-free package.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, SHDN, INA, LDOA to GND ...............................-0.3V to +30V
GND to PGND .......................................................-0.3V to +0.3V
LDO5, LDO3, VCC to GND .......................................-0.3V to +6V
ILIM3, ILIM5, PGDLY to GND...................................-0.3V to +6V
CSL3, CSH3, CSL5, CSH5 to GND ..........................-0.3V to +6V
ON3, ON5, FB3, FB5 to GND ..................................-0.3V to +6V
SKIP, OVP, UVP to GND...........................................-0.3V to +6V
PGOOD, FSEL, ADJA, ONA to GND ........................-0.3V to +6V
REF to GND................................................-0.3V to (VCC + 0.3V)
DL3, DL5 to PGND..................................-0.3V to (VLDO5 + 0.3V)
BST3, BST5 to PGND .............................................-0.3V to +36V
LX3 to BST3..............................................................-6V to +0.3V
DH3 to LX3 ..............................................-0.3V to (VBST3 + 0.3V)
LX5 to BST5..............................................................-6V to +0.3V
DH5 to LX5 ..............................................-0.3V to (VBST5 + 0.3V)
LDO3, LDO5 Short Circuit to GND .............................Momentary
REF Short Circuit to GND ...........................................Momentary
INA Shunt Current.............................................................+15mA
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFN (derate 21.3mW/°C above +70°C) .......1702mW
36-Pin TQFN (derate 26.3mW/°C above +70°C) .......2105mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
INPUT SUPPLIES (Note 1)
LDO5 in regulation 6 26
VIN Input Voltage Range VIN IN = LDO5, VOUT5 < 4.43V 4.5 5.5 V
VIN Operating Supply Current IIN LDO5 switched over to CSL5 15 35 µA
VIN Standby Supply Current
IIN
(
STBY
)
VIN = 6V to 26V, both SMPS off,
includes ISHDN
100
170 µA
VIN Shutdown Supply Current
IIN
(
SHDN
)
VIN = 6V to 26V, SHDN = GND 5 17 µA
Quiescent Power Consumption PQ
Both SMPS on, FB3 = FB5 = SKIP = GND,
VCSL3 = 3.5V, VCSL5 = 5.3V, VINA = 15V,
ILDOA = 0, PIN + PCSL3 + PCSL5 + PINA
3.5 4.5 mW
VCC Quiescent Supply Current ICC Both SMPS on, FB3 = FB5 = GND,
VCSL3 = 3.5V, VCSL5 = 5.3V 1.1 2.1 mA
MAIN SMPS CONTROLLERS
3.3V Output Voltage in Fixed
Mode VOUT3 VIN = 6V to 26V, SKIP = VCC (Note 2)
3.280 3.33 3.380
V
VOUT5 VIN = 6V to 26V, SKIP = VCC (Note 2)
4.975 5.05 5.125
V
Feedback Voltage in Adjustable
Mode VFB_ VIN = 6V to 26V, FB3 or FB5,
duty factor = 20% to 80% (Note 2)
0.990 1.005 1.020
V
Output-Voltage Adjust Range Either SMPS 1.0 5.5 V
FB3, FB5 Dual-Mode Threshold 0.1 0.2 V
VFB3 = VFB5 = 1.1V
-0.1 +0.1
µA
DC Load Regulation Either SMPS, SKIP = VCC,
ILOAD = 0 to full load
-0.1
%
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Line-Regulation Error Either SMPS, duty cycle = 10% to 90% 1 %
FSEL = GND
170 200
230
FSEL = REF
270 300
330
Operating Frequency (Note 1) fOSC
FSEL = VCC
425 500
575
kHz
FSEL = GND 91 93
FSEL = REF 91 93Maximum Duty Factor (Note 1) DMAX
FSEL = VCC 91 93
%
Minimum On-Time
tON
(
MIN
)
(Note 3) 200 ns
40 %
SMPS3 to SMPS5 Phase Shift SMPS5 starts after SMPS3
144
Deg
CURRENT LIMIT
ILIM_ Adjustment Range 0.5
VREF
V
Current-Sense Input Range CSH_, CSL_ 0 5.5 V
Current-Sense Input Leakage
Current CSH_, VCSH_ = 5.5V -1 +1 µA
Current-Limit Threshold (Fixed) VLIMIT_V
CSH_ - VCSL
_ , ILIM_ = VCC 70 75 80 mV
VILIM_ = 2.00V
170 200
230
VILIM_ = 1.00V 91
100
109
Current-Limit Threshold
(Adjustable)
VLIMIT_
VCSH_ - VCSL_
VILIM_ = 0.50V 42 50 58
mV
Current-Limit Threshold
(Negative) VNEG VCSH_ - VCSL_, SKIP = VCC, percent of
current limit
-120
%
Current-Limit Threshold (Zero
Crossing) VZX VPGND - VLX_, SKIP = GND, ILIM_ = VCC 3mV
ILIM_ = VCC 10 16 22 mV
Idle-Mode™ Threshold VIDLE VCSH_ - VCSL
_ With respect to current-
limit threshold (VLIMIT)
20 %
ILIM_ Leakage Current ILIM3 = ILIM5 = GND or VCC
-0.1 +0.1
µA
Soft-Start Ramp Time tSS Measured from the rising edge of ON_ to
full scale
512 /
fOSC
s
INTERNAL FIXED LINEAR REGULATORS
LDO5 Output Voltage VLDO5 ON3 = ON5 = GND, 6V < VIN < 26V,
0 < ILDO5 < 100mA
4.80 4.95 5.10
V
LDO5 Undervoltage-Lockout Fault
Threshold Rising edge, hysteresis = 1%
3.75
4.0
4.25
V
LDO5 Bootstrap Switch Threshold
Rising edge of CSL5, hysteresis = 1%
4.41 4.75
V
LDO5 Bootstrap Switch
Resistance
LDO5 to CSL5, VCSL5 = 5V,
ILDO5 = 50mA
0.75
3Ω
Idle Mode is a trademark of Maxim Integrated Products, Inc.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
LDO3 Output Voltage VLDO3 Standby mode, 6V < VIN < 26V,
0 < ILOAD < 100mA
3.20 3.35 3.42
V
LDO3 Bootstrap Switch Threshold
Rising edge of CSL3, hysteresis = 1%
2.83 3.10
V
LDO3 Bootstrap Switch
Resistance
LDO3 to CSL3, VCSL3 = 3.2V,
ILDO3 = 50mA 13Ω
Short-Circuit Current LDO3 = LDO5 = GND,
CSL3 = CSL5 = GND
150
220 mA
Short-Circuit Current (Switched
Over to CSL_)
LDO3 = LDO5 = GND, VCSL3 > 3.1V,
VCSL5 > 4.7V
250
mA
AUXILIARY LINEAR REGULATOR (MAX1537 ONLY)
LDOA Voltage Range VLDOA 523V
INA Voltage Range VINA 624V
LDOA Regulation Threshold,
Internal Feedback
ADJA = GND, 0 < ILDOA < 120mA,
VINA > 13V
11.4 12.0 12.4
V
ADJA Regulation Threshold,
External Feedback VADJA 0 < ILDOA < 120mA, VLDOA > 5.0V and
VINA > VLDOA + 1V
1.94 2.00 2.06
V
ADJA Dual-Mode Threshold 0.1
0.15
0.2 V
ADJA Leakage Current VADJA = 2.1V
-0.1 +0.1
µA
LDOA Current Limit
VLDOA forced to VINA - 1V, VADJA = 1.9V,
VINA > 6V
150
mA
Secondary Feedback Regulation
Threshold VINA - VLDOA
0.65
0.8
0.95
V
DL Duty Factor VINA - VLDOA < 0.7V, pulse width with
respect to switching period 33 %
INA Quiescent Current IINA VINA = 24V, ILDOA = no load 50 165 µA
INA Shunt Sink Current VINA = 28V 10 mA
INA Leakage Current
IINA
(
SHDN
)
VINA = 5V, LDOA disabled 30 µA
REFERENCE (REF)
Reference Voltage VREF VCC = 4.5V to 5.5V, IREF = 0
1.985 2.00 2.015
V
Reference Load Regulation IREF = -10µA to +100µA
1.980 2.020
V
REF Lockout Voltage
VREF
(
UVLO
)
Rising edge, hysteresis = 350mV
1.95
V
FAULT DETECTION
Output Overvoltage Trip
Threshold
OVP = GND, with respect to error-
comparator threshold 81115%
Output Overvoltage Fault-
Propagation Delay tOVP 50mV overdrive 10 µs
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold
65 70 75 %
Output Undervoltage Fault-
Propagation Delay tUVP 50mV overdrive 10 µs
Output Undervoltage-Protection
Blanking Time tBLANK From rising edge of ON_
6144 /
fOSC
s
PGOOD Lower Trip Threshold With respect to error-comparator
threshold, hysteresis = 1% -14 -10
-7.5
%
PGOOD Propagation Delay
tPGOOD_
Falling edge, 50mV overdrive 10 µs
PGOOD Output Low Voltage ISINK = 4mA 0.4 V
PGOOD Leakage Current
IPGOOD_
High state, PGOOD forced to 5.5V 1 µA
PGDLY Pullup Current PGDLY = GND 4 5 6 µA
PGDLY Pulldown Resistance 10 25 Ω
PGDLY Trip Threshold REF-
0.2
REF
REF+
0.2 V
Thermal-Shutdown Threshold TSHDN Hysteresis = 15°C
+160
°C
GATE DRIVERS
DH_ Gate-Driver On-Resistance RDH BST_ - LX_ forced to 5V 1.5 5 Ω
DL_, high state 1.7 5
DL_ Gate-Driver On-Resistance RDL DL_, low state 0.6 3 Ω
DH_ Gate-Driver Source/Sink
Current IDH DH_ forced to 2.5V,
BST_ - LX_ forced to 5V 2A
DL_ Gate-Driver Source Current IDL DL_ forced to 2.5V 1.7 A
DL_ Gate-Driver Sink Current
IDL
(
SINK
)
DL_ forced to 2.5V 3.3 A
DL_ rising 35
Dead Time tDEAD DH_ rising 26 ns
LX_, BST_ Leakage Current VBST_ = VLX_ = 26V <2 20 µA
INPUTS AND OUTPUTS
High 2.4
Logic Input Voltage SKIP, hysteresis = 600mV Low 0.8 V
High 0.7 x
VCC
Fault Enable Logic Input Voltage
OVP, UVP, ONA
Low 0.4
V
Logic Input Current OVP, UVP, SKIP, ONA -1 +1 µA
Rising trip level
1.10
1.6
2.20
SHDN Input Trip Level Falling trip level
0.96
1
1.04
V
Clear fault level/SMPS off level 0.8
Delay start level (REF) 1.9 2.1ON_ Input Voltage
SMPS on level 2.4
V
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
High VCC - 0.2
REF 1.7 2.3FSEL Three-Level Input Logic
GND 0.4
V
OVP, UVP, SKIP, ONA, ON3, ON5 = GND
or VCC -1 +1
SHDN, 0V or 26V -1 +1
Input Leakage Current
FSEL = GND or VCC -3 +3
µA
CSL_ Discharge-Mode
On-Resistance
RDISCHARGE
10 25 Ω
CSL_ Synchronous-Rectifier
Discharge-Mode Turn-On Level 0.2 0.3 0.4 V
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
UNITS
INPUT SUPPLIES (Note 1)
LDO5 in regulation 6 26
VIN Input Voltage Range VIN IN = LDO5, VOUT5 < 4.4V 4.5 5.5 V
VIN Operating Supply Current IIN LDO5 switched over to CSL5,
either SMPS on 35 µA
VIN Standby Supply Current
IIN
(
STBY
)
VIN = 6V to 26V, both SMPS off,
includes ISHDN 170 µA
VIN Shutdown Supply Current
IIN
(
SHDN
)
VIN = 6V to 26V 17 µA
Quiescent Power Consumption PQ
Both SMPS on, FB3 = FB5 = SKIP = GND,
VCSL3 = 3.5V, VCSL5 = 5.3V, VINA = 15V,
ILDOA = 0, PIN + PCSL3 + PCSL5 + PINA
4.5 mW
VCC Quiescent Supply Current ICC Both SMPS on, FB3 = FB5 = GND,
VCSL3 = 3.5V, VCSL5 = 5.3V 2.5 mA
MAIN SMPS CONTROLLERS
3.3V Output Voltage in
Fixed Mode VOUT3 VIN = 6V to 26V, SKIP = VCC (Note 2)
3.28 3.38
V
5V Output Voltage in Fixed Mode
VOUT5 VIN = 6V to 26V, SKIP = VCC (Note 2)
4.975 5.125
V
Feedback Voltage in
Adjustable Mode
VFB3, VFB5
VIN = 6V to 26V, FB3 or FB5,
duty factor = 20% to 80% (Note 2)
0.982 1.018
V
Output-Voltage Adjust Range Either SMPS 1.0 5.5 V
FB3, FB5 Adjustable-Mode
Threshold Voltage Dual-mode comparator 0.1 0.2 V
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
UNITS
FSEL = GND
170
230
FSEL = REF
240
330Operating Frequency (Note 1) fOSC
FSEL = VCC
375
575
kHz
FSEL = GND 91
FSEL = REF 91
Maximum Duty Factor (Note 1) DMAX
FSEL = VCC 91
%
Minimum On-Time
tON
(
MIN
)
250 ns
CURRENT LIMIT
ILIM_ Adjustment Range 0.5
VREF
V
Current-Limit Threshold (Fixed)
VLIMIT_
VCSH_ - VCSL
_ , ILIM_ = VCC 67 83 mV
VILIM_ = 2.00V
170
230
VILIM_ = 1.00V 90 110
Current-Limit Threshold
(Adjustable)
VLIMIT_
VCSH_ - VCSL
_
VILIM_ = 0.50V 40 60
mV
INTERNAL FIXED LINEAR REGULATORS
LDO5 Output Voltage VLDO5 ON3 = ON5 = GND, 6V < VIN < 26V,
0 < ILDO5 < 100mA 4.8 5.1 V
LDO5 Undervoltage-Lockout
Fault Threshold Rising edge, hysteresis = 1%
3.75 4.30
V
LDO3 Output Voltage VLDO3 Standby mode, 6V < VIN < 28V,
0 < ILOAD < 100mA
3.20 3.43
V
AUXILIARY LINEAR REGULATOR (MAX1537 ONLY)
LDOA Voltage Range VLODA 523V
INA Voltage Range VINA 624V
LDOA Regulation Threshold,
Internal Feedback
ADJA = GND, 0 < ILDOA < 120mA,
VINA > 13V
11.40 12.55
V
ADJA Regulation Threshold,
External Feedback VADJA 0 < ILDOA < 120mA, VLDOA > 5.0V and
VINA > VLDOA + 1V
1.94 2.08
V
ADJA Dual-Mode Threshold ADJA
0.10 0.25
V
Secondary Feedback
Regulation Threshold VINA - VLDOA
0.63 0.97
V
INA Quiescent Current IINA VINA = 24V, ILDOA = no load 165 µA
REFERENCE (REF)
Reference Voltage VREF VCC = 4.5V to 5.5V, IREF = 0
1.97 2.03
V
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, both SMPS enabled, VCC = 5V, FSEL = REF, SKIP = GND, VILIM_ = VLDO5, VINA = 15V, VLDOA = 12V,
ILDO5 = ILDO3 = ILDOA = no load, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
FAULT DETECTION
Output Overvoltage Trip
Threshold
OVP = GND, with respect to error-
comparator threshold +8
+15
%
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold +65 +75
%
PGOOD Lower Trip Threshold With respect to error-comparator threshold,
hysteresis = 1%
-14.0 -7.0
%
PGOOD Output Low Voltage ISINK = 4mA 0.4 V
PGDLY Pulldown Resistance 25 Ω
PGDLY Trip Threshold REF-
0.2
REF+
0.2 V
GATE DRIVERS
DH_ Gate-Driver On-Resistance RDH BST_ - LX_ forced to 5V 5 Ω
DL_, high state 5
DL_ Gate-Driver On-Resistance RDL DL_, low state 3 Ω
INPUTS AND OUTPUTS
High 2.4
Logic Input Voltage SKIP, hysteresis = 600mV Low 0.8 V
High
0.7 x
VCC
Fault Enable Logic Input Voltage
OVP, UVP, ONA
Low 0.4
V
Rising trip level 1.1 2.2
SHDN Input Trip Level Falling trip level
0.95 1.05
V
Clear fault level 0.8
SMPS off level 1.6
Delay start level (REF) 1.9 2.1
ON_ Input Voltage
SMPS on level 2.4
V
High VCC - 0.2
REF 1.7 2.3FSEL Three-Level Input Logic
GND 0.4
V
Note 1: The MAX1533/MAX1537 cannot operate over all combinations of frequency, input voltage (VIN), and output voltage. For
large input-to-output differentials and high-switching frequency settings, the required on-time may be too short to maintain
the regulation specifications. Under these conditions, a lower operating frequency must be selected. The minimum on-time
must be greater than 150ns, regardless of the selected switching frequency. On-time and off-time specifications are mea-
sured from 50% point to 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V, and a 250pF capacitor connected from DH_
to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator
threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regula-
tion level higher than the trip level by approximately 1% due to slope compensation.
Note 3: Specifications are guaranteed by design, not production tested.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 9
PWM5 EFFICIENCY vs. LOAD CURRENT
(VOUT5 = 5.0V)
MAX1533 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
10.1
60
70
80
90
100
50
0.01 10
VIN = 20V
VIN = 12V
VIN = 7V
SKIP = GND
SKIP = VCC
5V OUTPUT VOLTAGE (OUT5)
vs. LOAD CURRENT
MAX1533/37 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
45231
4.96
5.00
5.04
5.08
5.12
4.88
4.92
06
SKIP = GND
SKIP = VCC
5V OUTPUT VOLTAGE (OUT5)
vs. INPUT VOLTAGE
MAX1533/37 toc03
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2515 2010
4.96
5.00
5.04
5.08
5.12
4.88
4.92
530
SKIP = GND
SKIP = VCC
NO LOAD
PWM3 EFFICIENCY vs. LOAD CURRENT
(VOUT3 = 3.3V)
MAX1533/37 toc04
LOAD CURRENT (A)
EFFICIENCY (%)
10.1
60
70
80
90
100
50
0.01 10
VIN = 20V
VIN = 12V
VIN = 5V
SKIP = GND
SKIP = VCC
3.3V OUTPUT VOLTAGE (OUT3)
vs. LOAD CURRENT
MAX1533/37 toc05
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
45231
3.27
3.30
3.33
3.36
3.39
3.21
3.24
06
SKIP = GND
SKIP = VCC
3.3V OUTPUT VOLTAGE (OUT3)
vs. INPUT VOLTAGE
MAX1533/37 toc06
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2515 2010
3.27
3.30
3.33
3.36
3.39
3.21
3.24
530
SKIP = GND
SKIP = VCC
NO LOAD
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (FULLY ENABLED)
MAX1533/37 toc07
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
2515 2010
16
20
24
28
32
0
12
8
4
05 30
SKIP = GND
SKIP = VCC
ON3 = ON5 = VCC
0.22mA (VIN = 12V)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (STANDBY MODE)
MAX1533/37 toc08
INPUT VOLTAGE (V)
STANDBY SUPPLY CURRENT (mA)
2515 2010
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.3
0.2
0.1
05 30
ON3 = ON5 = GND
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX1533/37 toc09
INPUT VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (µA)
2515 2010
2
4
6
8
10
0
05 30
SHDN = GND
Typical Operating Characteristics
(MAX1537 circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX1537 circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
IDLE-MODE CURRENT
vs. INPUT VOLTAGE
MAX1533/37 toc10
INPUT VOLTAGE (V)
PEAK CURRENT (A)
2515 2010
1.5
1.0
0.5
2.0
2.5
3.0
3.5
0
05 30
DUTY CYCLE
LIMITED
5V OUTPUT
2.0V REFERENCE LOAD REGULATION
MAX1533 toc11
REF LOAD CURRENT (µA)
REF VOLTAGE (V)
80600 20 40
1.99
2.00
2.01
2.02
1.98
-20 100
LINEAR-REGULATOR
LOAD REGULATION
MAX1533/37 toc12
LDO LOAD CURRENT (mA)
LDO DEVIATION VOLTAGE (mV)
12010080604020
-150
-100
-50
0
50
-200
0 140
LDO3
LDO5
VIN = 6V
ON3 = ON5 = GND
AUXILIARY LINEAR-REGULATOR
LOAD REGULATION
MAX1533/37 toc13
LDOA LOAD CURRENT (mA)
AUX LDO VOLTAGE (V)
1601208040
11.8
11.9
12.0
12.1
11.7
0200
INTERLEAVED OPERATION
MAX1533/37 toc14
2.0µs/div
12V
0
A
B
C
D
E
F
5V
0
12V
0
3.3V
0
A. LX5, 10V/div
B. 5V OUTPUT, 100mV/div
C. PWM5 INDUCTOR CURRENT, 5A/div
D. LX3, 10V/div
E. 3.3V OUTPUT, 100mV/div
F. PWM3 INDUCTOR CURRENT, 5A/div
LINEAR-REGULATOR
STARTUP WAVEFORMS
MAX1533/37 toc15
400µs/div
5V
4V
0
A
B
C
D
2V
0
2V
0
2V
0
B. LDO5, 2V/div
C. LDO3, 2V/div
D. REF, 2V/div
100Ω LOAD ON LDO5 AND LDO3
A. SHDN, 5V/div
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 11
DELAYED STARTUP WAVEFORM
(LIGHT LOAD)
MAX1533/37 toc16
2ms/div
3.3V
5V
0A
B
C
D
0
3.3V
0
0
A. ON5, 5V/div
B. 5V OUTPUT, 2V/div
C. 3.3V OUPUT, 2V/div
D. PGOOD, 2V/div
100Ω LOAD ON OUT5 AND OUT3, ON3 = REF
STARTUP WAVEFORM (HEAVY LOAD)
MAX1533/37 toc17
400µs/div
3.3V
0
4V
A
B
C
D
E
2V
0
2.5A
0
5V
0
A. ON5, 5V/div
B. 5V OUTPUT, 2V/div
C. INDUCTOR CURRENT, 5A/div
D. LDO5, 1V/div
E. DL5, 5V/div
1.0Ω LOAD
SHUTDOWN WAVEFORM (NO LOAD)
MAX1533/37 toc18
2ms/div
2V
0
5V
A
B
C
D
E
F
5V
0
0
3.3V
0
5V
0
0
D. 3.3V OUTPUT, 5V/div
E. DL3, 5V/div
F. PGOOD, 5V/div
B. 5V OUTPUT, 5V/div
C. DL5, 5V/div
A. SHDN, 5V/div
ON3 = ON5 = VCC, OVP = GND
SHUTDOWN WAVEFORM (1Ω LOAD)
MAX1533/37 toc19
100µs/div
2V
0
5V
A
B
C
D
E
5V
5A
0
5V
0
B. LDO5, 2V/div
C. 5V OUTPUT, 2V/div
D. INDUCTOR CURRENT, 5A/div
E. DL5, 5V/div
ON3 = ON5 = VCC, OVP = GND
A. SHDN, 5V/div
5V OUTPUT LOAD TRANSIENT
(FORCED-PWM)
MAX1533/37 toc20
40µs/div
4A
0A
B
C
D
5V
4A
0
12V
0
B. VOUT5 = 5.0V, 100mV/div
C. INDUCTOR CURRENT, 5A/div
D. LX5, 10V/div
A. IOUT5 = 0.2A TO 4A, 5A/div
SKIP = VCC
3.3V OUTPUT LOAD TRANSIENT
(FORCED-PWM)
MAX1533/37 toc21
40µs/div
4A
0A
B
C
D
3.3V
4A
0
12V
0
B. VOUT3 = 3.3V, 100mV/div
C. INDUCTOR CURRENT, 5A/div
D. LX3, 10V/div
A. IOUT3 = 0.2A TO 4A, 5A/div
SKIP = VCC
Typical Operating Characteristics (continued)
(MAX1537 circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
12 ______________________________________________________________________________________
3.3V OUTPUT LOAD TRANSIENT
(PULSE SKIPPING)
MAX1533/37 toc22
40µs/div
4A
0A
B
C
D
3.3V
4A
0
12V
0
B. VOUT3 = 3.3V, 100mV/div
C. INDUCTOR CURRENT, 5A/div
D. LX3, 10V/div
A. IOUT3 = 0.2A TO 4A, 5A/div
SKIP = GND
OUTPUT OVERLOAD
(UVP ENABLED)
MAX1533/37 toc23
4µs/div
5V
0
A
B
C
3.3V
0
7A
12V
B. 3.3V OUTPUT, 3.3V/div
C. LOAD (0 TO 30A), 20A/div
A. PGOOD2, 5V/div
D
E
30A
0
0
0
D. INDUCTOR CURRENT, 10A/div
E. LX3, 20V/div
LDO5 LOAD TRANSIENT
MAX1533/37 toc24
20µs/div
5V
0
A
B
C
100mA
0
5.0V
4.95V
B. ILDO5 = 1mA TO 100mA, 100mA/div
C. LDO5, 50m/div
ON3 = ON5 = GND
A. CONTROL SIGNAL, 5V/div
LDO5 LINE TRANSIENT
MAX1533/37 toc25
20µs/div
20V
A
B
15V
4.95V
B. LDO5 OUTPUT VOLTAGE, 50mV/div
A. INPUT VOLTAGE (VIN = 7V TO 20V), 5V/div
10V
5.05V
5.00V
ON3 = ON5 = GND, ILDO5 = 20mA
5V
AUXILIARY LINEAR-REGULATOR
LOAD TRANSIENT
MAX1533/37 toc26
100µs/div
120mA A
B
10mA
11.90V
B. INA, 1V/div
A. ILDOA = 10mA TO 100mA, 100mA/div
14V
13V
11.96V
C. LDOA, 50mV/div
C
INA = VOLTAGE GENERATED BY SECONDARY
TRANSFORMER WINDING
Typical Operating Characteristics (continued)
(MAX1537 circuit of Figure 1, VIN = 12V, LDO5 = VCC = 5V, SKIP = GND, FSEL = REF, TA = +25°C, unless otherwise noted.)
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 13
Pin Description
PIN
MAX1533
MAX1537
NAME FUNCTION
— 1 ADJA
Auxiliary Feedback Input. Connect a resistive voltage-divider from LDOA to analog
ground to adjust the auxiliary linear-regulator output voltage. ADJA regulates at 2V.
Connect ADJA to GND for nominal 12V output using internal feedback.
1 2 ON5
5V SMPS Enable Input. The 5V SMPS is enabled if ON5 is greater than the SMPS on
level and disabled if ON5 is less than the SMPS off level. If ON5 is connected to REF,
the 5V SMPS starts after the 3.3V SMPS reaches regulation (delay start). Drive ON5
below the clear fault level to reset the fault latches.
2 3 ON3
3.3V SMPS Enable Input. The 3.3V SMPS is enabled if ON3 is greater than the SMPS
on level and disabled if ON3 is less than the SMPS off level. If ON3 is connected to
REF, the 3.3V SMPS starts after the 5V SMPS reaches regulation (delay start). Drive
ON3 below the clear fault level to reset the fault latches.
— 4 ONA
LDOA Enable Input. When ONA is low, LDOA is high impedance and the secondary
winding control is off. When ONA is high, LDOA is on. Connect to LDO3, LDO5,
CSL3, CSL5, or other output for desired automatic startup sequencing.
3 5 FSEL
Frequency-Select Input. This three-level logic input sets the controller’s switching
frequency. Connect to GND, REF, or VCC to select the following typical switching
frequencies:
VCC = 500kHz, REF = 300kHz, GND = 200kHz
4 6 ILIM3
3.3V SMPS Peak Current-Limit Threshold Adjustment. The current-limit threshold
defaults to 75mV if ILIM3 is connected to VCC. In adjustable mode, the current-limit
threshold across CSH3 and CSL3 is precisely 1/10th the voltage seen at ILIM3 over a
500mV to 2.0V range. The logic threshold for switchover to the 75mV default value is
approximately VCC - 1V.
5 7 ILIM5
5V S M P S P eak C ur r ent- Li m i t Thr eshol d . The cur r ent- l i m i t thr eshol d d efaul ts to 75m V i f
ILIM 5 i s connected to V
C C
. In ad j ustab l e m od e, the cur r ent- l i m i t thr eshol d acr oss C S H 5
and C S L5 i s p r eci sel y 1/10th the vol tag e seen at ILIM 5 over a 500m V to 2.0V r ang e. The
l og i c thr eshol d for sw i tchover to the 75m V d efaul t val ue i s ap p r oxi m atel y V
C C
- 1V .
6 8 REF
2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater
ceramic capacitor. The reference can source up to 100µA for external loads. Loading
REF degrades output-voltage accuracy according to the REF load-regulation error.
The reference shuts down when SHDN is low.
7 9 GND Analog Ground. Connect the backside pad to GND.
810 V
CC
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through
a series 20Ω resistor. Bypass VCC to analog ground with a 1µF or greater ceramic
capacitor.
9 11 PGDLY
Power-Good One-Shot Delay. Place a timing capacitor on PGDLY to delay PGOOD
going high. PGDLY has a 5µA pullup current and a 10Ω pulldown. The pulldown is
activated when power is not good. When power is good, the pulldown is shut off and
the 5µA pullup is activated. When PGDLY crosses REF, PGOOD is enabled.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
14 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1533
MAX1537
NAME FUNCTION
10 12 PGOOD
Open-Drain Power-Good Output. PGOOD is low if either output is more than 10%
(typ) below the normal regulation point, during soft-start, and in shutdown. PGOOD is
delayed on the rising edge by the PGDLY one-shot timer. PGOOD becomes high
impedance when both SMPS outputs are in regulation.
11 13 UVP
Undervoltage Fault-Protection Control. Connect UVP to GND to select the default
overvoltage threshold of 70% of nominal. Connect to VCC to disable undervoltage
protection and clear the undervoltage fault latch.
12 14 DH3 High-Side Gate-Driver Output for 3.3V SMPS. DH3 swings from LX3 to BST3.
13 15 BST3
Boost Flying-Capacitor Connection for 3.3V SMPS. Connect to an external capacitor
and diode as shown in Figure 6. An optional resistor in series with BST3 allows the
DH3 pullup current to be adjusted.
14 16 LX3 Inductor Connection for 3.3V SMPS. Connect LX3 to the switched side of the
inductor. LX3 serves as the lower supply rail for the DH3 high-side gate driver.
15 17 OVP
Overvoltage Fault-Protection Control. Connect OVP to GND to select the default
overvoltage threshold of +11% above nominal. Connect to VCC to disable
overvoltage protection and clear the overvoltage fault latch.
16 18 CSH3 Positive Current-Sense Input for 3.3V SMPS. Connect to the positive terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
17 19 CSL3
Negative Current-Sense Input for 3.3V SMPS. Connect to the negative terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
CSL3 also serves as the bootstrap input for LDO3.
18 20 FB3 Feedback Input for 3.3V SMPS. Connect to GND for fixed 3.3V output. In adjustable
mode, FB3 regulates to 1V.
19 21 LDO3
3.3V Internal Linear-Regulator Output. Bypass with 2.2µF (min) (1µF/20mA). Provides
100mA (min). Power is taken from LDO5. If CSL3 is greater than 3V, the linear
regulator shuts down and LDO3 connects to CSL3 through a 1Ω switch rated for
loads up to 200mA.
20 22 DL3 Low-Side Gate-Driver Output for 3.3V SMPS. DL3 swings from PGND to LDO5.
21 23 PGND Power Ground
22 24 DL5 Low-Side Gate-Driver Output for 5V SMPS. DL5 swings from PGND to LDO5.
23 25 LDO5
5V Internal Linear-Regulator Output. Bypass with 2.2µF (min) (1µF/20mA). Provides
power for the DL_ low-side gate drivers, the DH_ high-side drivers through the BST
diodes, the PWM controller, logic, and reference through the VCC pin, as well as the
LDO3 internal 3.3V linear regulator. Provides 100mA (min) for external loads (+25mA
for gate drivers). If CSL5 is greater than 4.5V, the linear regulator shuts down and
LDO5 connects to CSL5 through a 0.75Ω switch rated for loads up to 200mA.
24 26 FB5 Feedback Input for 5V SMPS. Connect to GND for fixed 5V output. In adjustable
mode, FB5 regulates to 1V.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 15
Pin Description (continued)
PIN
MAX1533
MAX1537
NAME FUNCTION
25 27 CSL5
Negative Current-Sense Input for 5V SMPS. Connect to the negative terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
CSL5 also serves as the bootstrap input for LDO5.
26 28 CSH5 Positive Current-Sense Input for 5V SMPS. Connect to the positive terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
27 29 IN Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to
PGND with 0.22µF close to the IC.
28 30 LX5 Inductor Connection for 5V SMPS. Connect LX5 to the switched side of the inductor.
LX5 serves as the lower supply rail for the DH5 high-side gate driver.
29 31 BST5
Boost Flying-Capacitor Connection for 5V SMPS. Connect to an external capacitor
and diode as shown in Figure 6. An optional resistor in series with BST5 allows the
DH5 pullup current to be adjusted.
30 32 DH5 High-Side Gate-Driver Output for 5V SMPS. DH5 swings from LX5 to BST5.
31 33 SKIP Pulse-Skipping Control Input. Connect to VCC for low-noise forced-PWM mode.
Connect to GND for high-efficiency pulse-skipping mode at light loads.
32 34 SHDN
Shutdown Control Input. The device enters its 5µA supply-current shutdown mode if
VSHDN is less than the SHDN input falling-edge trip level and does not restart until
VSHDN is greater than the SHDN input rising-edge trip level. Connect SHDN to VIN for
automatic startup. SHDN can be connected to VIN through a resistive voltage-divider
to implement a programmable undervoltage lockout.
— 35 INA Supply Voltage Input for the Auxiliary LDOA Linear Regulator. INA is clamped with an
internal shunt to 26V.
— 36 LDOA
Adjustable (12V Nominal) 150mA Auxiliary Linear-Regulator Output. Input supply
comes from INA. Bypass LDOA to GND with 2.2µF (min) (1µF/20mA). Secondary
feedback threshold is set at INA - LDOA = 0.8V, and triggers the DL5 on the 5V
SMPS only. ONA high enables regulator output and secondary regulation. PGOOD is
not affected by the state of LDOA.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
16 ______________________________________________________________________________________
COMPONENT 5A/300kHz 5A/500kHz
Input Voltage VIN = 7V to 24V VIN = 7V to 24V
CIN_, Input Capacitor (2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
COUT5, Output Capacitor 150µF, 6.3V, 40mΩ, low-ESR capacitor
Sanyo 6TPB150ML
150µF, 6.3V, 40mΩ, low-ESR capacitor
Sanyo 6TPB150ML
COUT3, Output Capacitor 220µF, 4V, 40mΩ, low-ESR capacitor
Sanyo 4TPB220ML
220µF, 4V, 40mΩ, low-ESR capacitor
Sanyo 4TPB220ML
NH_ High-Side MOSFET Fairchild Semiconductor FDS6612A
International Rectifier IRF7807V
Fairchild Semiconductor FDS6612A
International Rectifier IRF7807V
NL_ Low-Side MOSFET Fairchild Semiconductor FDS6670S
International Rectifier IRF7807VD1
Fairchild Semiconductor FDS6670S
International Rectifier IRF7807VD1
DL_ Schottky Rectifier
(if needed)
2A, 30V, 0.45Vf
Nihon EC21QS03L
2A, 30V, 0.45Vf
Nihon EC21QS03L
Inductor/Transformer T1 = 6.8µH, 1:2 turns Sumida 4749-T132
L1 = 5.8µH, 8.6A Sumida CDRH127-5R8NC
3.9µH
Sumida CDRH124-3R9NC
RCS
10mΩ ±1%, 0.5W resistor
IRC LR2010-01-R010F or
Dale WSL-2010-R010F
10mΩ ±1%, 0.5W resistor
IRC LR2010-01-R010F or
Dale WSL-2010-R010F
SUPPLIER WEBSITE
AVX www.avx.com
Central Semiconductor www.centralsemi.com
Coilcraft www.coilcraft.com
Coiltronics www.coiltronics.com
Fairchild Semiconductor www.fairchildsemi.com
International Rectifier www.irf.com
Kemet www.kemet.com
Detailed Description
The MAX1533/MAX1537 standard application circuit
(Figure 1) generates the 5V/5A and 3.3V/5A typical of the
main supplies in a notebook computer. The input supply
range is 7V to 24V. See Table 1 for component selections
and Table 2 for component manufacturers.
The MAX1533/MAX1537 contain two interleaved fixed-
frequency step-down controllers designed for low-
voltage power supplies. The optimal interleaved archi-
tecture guarantees out-of-phase operation, reducing
the input capacitor ripple. Two internal LDOs generate
the keep-alive 5V and 3.3V power. The MAX1537 has
an auxiliary LDO that can be configured to the preset
12V output or an adjustable output.
Fixed Linear Regulators (LDO5 and LDO3)
Two internal linear regulators produce preset 5V (LDO5)
and 3.3V (LDO3) low-power outputs. LDO5 powers
LDO3, the gate drivers for the external MOSFETs, and
provides the bias supply (VCC) required for the SMPS
analog control, reference, and logic blocks. LDO5
supplies at least 100mA for external and internal loads,
including the MOSFET gate drive, which typically varies
from 5mA to 50mA, depending on the switching frequen-
cy and external MOSFETs selected. LDO3 also supplies
at least 100mA for external loads. Bypass LDO5 and
LDO3 with a 2.2µF or greater output capacitor, using an
additional 1.0µF per 20mA of internal and external load.
Table 1. Component Selection for Standard Applications
Table 2. Component Suppliers
SUPPLIER WEBSITE
Panasonic www.panasonic.com/industrial
Sanyo www.secc.co.jp
Sumida www.sumida.com
Taiyo Yuden www.t-yuden.com
TDK www.component.tdk.com
TOKO www.tokoam.com
Vishay (Dale, Siliconix) www.vishay.com
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 17
Figure 1. MAX1533/MAX1537 Standard Application Circuit
R3
60.4kΩ
R4
100kΩ
R5
60.4kΩ
LDO5
DH3
BST3
DL3
LX3
CSH3
ILIM5
CBST
0.1µF
NH2
DL2
RCS2
10mΩ
COUT2
150µF
40mΩ
REF (300kHz)
CONNECT
TO LDO5
POWER-GOOD
3.3V LDO
OUTPUT
NL2
CBST
0.1µF
NH1
NL1
RCS1
10mΩ
COUT1
220µF
40mΩ
DL1
L1
5.8µH
DBST DBST
C1
10µF
5V LDO
OUTPUT
3.3V PWM
OUTPUT
CREF
0.22µF
INPUT (VIN)
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS
SHDN
FB3
OVP
POWER GROUND
ANALOG GROUND
MAX1533
MAX1537
REF
CIN
(2) 10µF
ON OFF
12V LDO
OUTPUT
MAX1537 ONLY
ON3
ON5
INA
ONA
R2
100kΩ
BST5
LX5
DL5
PGND
GND
CSH5
CSL5
FB5
UVP
SKIP
DH5
IN
ILIM3
CSL3
ON OFF
SECONDARY
OUTPUT
ON OFF
C5
22µF
D1
5V PWM
OUTPUT
SECONDARY
OUTPUT
T1
1:2 TURNS
LP = 6.8µH
FSEL
VCC
PGOOD
PGDLY
R1
20Ω
C2
1µFR8
100kΩ
LDO3
C3
10µF
R7
0Ω
C4
10µF
LDOA
ADJA
R6
OPEN
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
18 ______________________________________________________________________________________
SMPS to LDO Bootstrap Switchover
When the 5V main output voltage is above the LDO5
bootstrap-switchover threshold, an internal 0.75Ω(typ)
p-channel MOSFET shorts CSL5 to LDO5 while simulta-
neously shutting down the LDO5 linear regulator.
Similarly, when the 3.3V main output voltage is above
the LDO3 bootstrap-switchover threshold, an internal
1Ω(typ) p-channel MOSFET shorts CSL3 to LDO3 while
simultaneously shutting down the LDO3 linear regula-
tor. These actions bootstrap the device, powering the
internal circuitry and external loads from the output
SMPS voltages, rather than through linear regulators
from the battery. Bootstrapping reduces power dissipa-
tion due to gate charge and quiescent losses by pro-
viding power from a 90%-efficient switch-mode source,
rather than from a much-less-efficient linear regulator.
The output current limit increases to 200mA when the
LDO_ outputs are switched over.
SMPS 5V Bias Supply (LDO5 and VCC)
The A switch-mode power supplies (SMPS) require a
5V bias supply in addition to the high-power input sup-
ply (battery or AC adapter). This 5V bias supply is gen-
erated by the MAX1533/MAX1537s’ internal 5V linear
regulator (LDO5). This bootstrapped LDO allows the
MAX1533/MAX1537 to power-up independently. The
gate-driver input supply is connected to the fixed 5V
linear-regulator output (LDO5). Therefore, the 5V LDO
supply must provide VCC (PWM controller) and the
gate-drive power, so the maximum supply current
required is:
IBIAS = ICC + fSW (QG(LOW) + QG(HIGH))
= 5mA to 50mA (typ)
where ICC is 1mA (typ), fSW is the switching frequency,
and QG(LOW) and QG(HIGH) are the MOSFET data
sheet’s total gate-charge specification limits at VGS = 5V.
Reference (REF)
The 2V reference is accurate to ±1% over temperature
and load, making REF useful as a precision system ref-
erence. Bypass REF to GND with a 0.22µF or greater
ceramic capacitor. The reference sources up to 100µA
and sinks 10µA to support external loads. If highly
accurate specifications (±0.5%) are required for the
main SMPS output voltages, the reference should not
be loaded. Loading the reference reduces the LDO5,
LDO3, OUT5, and OUT3 output voltages slightly
because of the reference load-regulation error.
System Enable/Shutdown (
SHDN
)
Drive SHDN below the precise SHDN input falling-edge
trip level to place the MAX1533/MAX1537 in their low-
power shutdown state. The MAX1533/MAX1537 con-
sume only 5µA of quiescent current while in shutdown
mode. When shutdown mode activates, the reference
turns off, making the threshold to exit shutdown less
accurate. To guarantee startup, drive SHDN above
2.2V (SHDN input rising-edge trip level). For automatic
shutdown and startup, connect SHDN to VIN. The accu-
rate 1V falling-edge threshold on SHDN can be used to
detect a specific input-voltage level and shut the
device down. Once in shutdown, the 1.6V rising-edge
threshold activates, providing sufficient hysteresis for
most applications.
SMPS Detailed
Description
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above
approximately 1V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled
low if OVP is disabled (OVP = VCC), or driven high if
OVP is enabled (OVP = GND) until the SMPS con-
trollers are activated.
The VCC input undervoltage-lockout (UVLO) circuitry
inhibits switching if the 5V bias supply (LDO5) is below
the 4V input UVLO threshold. Once the 5V bias supply
(LDO5) rises above this input UVLO threshold and the
controllers are enabled, the SMPS controllers start
switching and the output voltages begin to ramp up
using soft-start.
The internal digital soft-start gradually increases the
internal current-limit level during startup to reduce the
input surge currents. The MAX1533/MAX1537 divide the
soft-start period into five phases. During the first phase,
each controller limits its current limit to only 20% of its
full current limit. If the output does not reach regulation
within 128 clock cycles (1 / fOSC), soft-start enters the
second phase and the current limit is increased by
another 20%. This process repeats until the maximum
current limit is reached after 512 clock cycles (1 / fOSC)
or when the output reaches the nominal regulation volt-
age, whichever occurs first (see the startup waveforms
in the Typical Operating Characteristics).
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 19
Figure 2. MAX1533/MAX1537 Functional Diagram
VCC
REF
R
R
FB3
2.0V
REF
DH5
BST5
LX5
LDO5
DL5
PWM5
CONTROLLER
(FIGURE 3)
DH3
BST3
DL3
LDO5
LX3
PWM3
CONTROLLER
(FIGURE 3)
PGND
FB
DECODE
(FIGURE 5)
ON3
IN
FSEL
FB DECODE
(FIGURE 5) FB5
ON5
ILIM5
CSH5
CSL5
ILIM3
CSH3
CSL3
OVP
PGOOD
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
INTERNAL
FB
FAULT
ADJA
LDOA
INA
ONA
SKIP
UVP
5V LINEAR
REGULATOR
3.3V LINEAR
REGULATOR LDO5
PGDLY MAX1537
AUXILIARY
LINEAR
REGULATOR
(FIGURE 8)
GND
LDO3
LDO BYPASS
CIRCUITRY
LDO BYPASS
CIRCUITRY
OSC
SHDN
SECONDARY
FEEDBACK
MAX1533/MAX1537
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
20 ______________________________________________________________________________________
SMPS Enable Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs. Driving ON_ below 0.8V clears the
overvoltage, undervoltage, and thermal fault latches.
SMPS Power-Up Sequencing
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation
and starts after that output regulates. The second SMPS
remains on until the first SMPS turns off, the device
shuts down, a fault occurs, or LDO5 goes into undervolt-
age lockout. Both supplies begin their power-down
sequence immediately when the first supply turns off.
Output Discharge (Soft-Shutdown)
When output discharge is enabled (OVP pulled low)
and the switching regulators are disabled—by transi-
tions into standby or shutdown mode, or when an
output undervoltage fault occurs—the controller dis-
charges both outputs through internal 12Ωswitches,
until the output voltages decrease to 0.3V. This slowly
discharges the output capacitance, providing a soft-
damped shutdown response. This eliminates the slight-
ly negative output voltages caused by quickly
discharging the output through the inductor and low-
side MOSFET. When an SMPS output discharges to
0.3V, its low-side driver (DL_) is forced high, clamping
the respective SMPS output to GND. The reference
remains active to provide an accurate threshold and to
provide overvoltage protection. Both SMPS controllers
contain separate soft-shutdown circuits.
When output discharge is disabled (OVP = VCC), the low-
side drivers (DL_) and high-side drivers (DH_) are both
pulled low, forcing LX into a high-impedance state. Since
the outputs are not actively discharged by the SMPS con-
trollers, the output-voltage discharge rate is determined
only by the output capacitance and load current.
Fixed-Frequency, Current-Mode
PWM Controller
The heart of each current-mode PWM controller is a multi-
input, open-loop comparator that sums two signals: the
output-voltage error signal with respect to the reference
voltage and the slope-compensation ramp (Figure 3).
The MAX1533/MAX1537 use a direct-summing configu-
ration, approaching ideal cycle-to-cycle control over the
output voltage without a traditional error amplifier and the
phase shift associated with it. The MAX1533/MAX1537
use a relatively low loop gain, allowing the use of low-
cost output capacitors. The low loop gain results in the
-0.1% typical load-regulation error and helps reduce
the output capacitor size and cost by shifting the unity-
gain crossover frequency to a lower level.
Table 3. Operating Modes
INPUTS* OUTPUTS
MODE SHDN ON5 ON3 LDO5 LDO3 5V SMPS 3V SMPS
Shutdown Mode LOW X X OFF OFF OFF OFF
Standby Mode HIGH LOW LOW ON ON OFF OFF
Normal Operation HIGH HIGH HIGH ON ON ON ON
3.3V SMPS Active HIGH LOW HIGH ON ON OFF ON
5V SMPS Active HIGH HIGH LOW ON ON ON OFF
Normal Operation
(Delayed 5V SMPS
Startup)
HIGH REF HIGH ON ON
ON
Power-up after
3.3V SMPS is in
regulation
ON
Normal Operation
(Delayed 3.3V
SMPS Startup)
HIGH HIGH REF ON ON ON
ON
Power-up after 5V
SMPS is in
regulation
*
SHDN
is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3
and ON5 are 3-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the mid-
dle logic level is between 1.9V and 2.1V (see the Electrical Characteristics table).
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 21
Figure 3: PWM-Controller Functional Diagram
S
R
Q
R
S
QDH DRIVER
DL DRIVER
SLOPE COMP
DACCOUNTER
SOFT-START
CURRENT
LIMIT
ON
OSC
FROM FB
REF / 2
CSL
CSH
IDLE-
MODE
CURRENT
0.2 x VLIMIT
SECONDARY
FEEDBACK
0.8V
ONE-SHOT
-1.2 x VLIMIT
LX
PGND
MAX1537 ONLY
AGND
(SEE FIGURE 5)
SKIP
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
22 ______________________________________________________________________________________
Frequency Selection (FSEL)
The FSEL input selects the PWM-mode switching fre-
quency. Table 4 shows the switching frequency based
on FSEL connection. High-frequency (500kHz) operation
optimizes the application for the smallest component
size, trading off efficiency due to higher switching losses.
This may be acceptable in ultra-portable devices where
the load currents are lower. Low-frequency (200kHz)
operation offers the best overall efficiency at the expense
of component size and board space.
Forced-PWM Mode
The low-noise forced-PWM mode disables the zero-
crossing comparator, which controls the low-side switch
on-time. This forces the low-side gate-drive waveform to
constantly be the complement of the high-side gate-
drive waveform, so the inductor current reverses at light
loads while DH_ maintains a duty factor of VOUT / VIN.
The benefit of forced-PWM mode is to keep the switch-
ing frequency fairly constant. However, forced-PWM
operation comes at a cost: the no-load 5V supply current
remains between 15mA and 50mA, depending on the
external MOSFETs and switching frequency.
Forced-PWM mode is most useful for avoiding audio-
frequency noise and improving load-transient
response. Since forced-PWM operation disables the
zero-crossing comparator, the inductor current revers-
es under light loads.
Light-Load Operation Control (
SKIP
)
The MAX1533/MAX1537 include a light-load operating-
mode control input (SKIP) used to independently
enable or disable the zero-crossing comparator for
both controllers. When the zero-crossing comparator is
enabled, the controller forces DL_ low when the cur-
rent-sense inputs detect zero inductor current. This
keeps the inductor from discharging the output capaci-
tors and forces the controller to skip pulses under light-
load conditions to avoid overcharging the output. When
the zero-crossing comparator is disabled, the controller
is forced to maintain PWM operation under light-load
conditions (forced-PWM).
Idle-Mode Current-Sense Threshold
The on-time of the step-down controller terminates
when the output voltage exceeds the feedback thresh-
old and when the current-sense voltage exceeds the
idle-mode current-sense threshold. Under light-load
conditions, the on-time duration depends solely on the
idle-mode current-sense threshold, which is approxi-
mately 20% of the full-load current-limit threshold set by
ILIM_. This forces the controller to source a minimum
amount of power with each cycle. To avoid overcharg-
ing the output, another on-time cannot begin until the
output voltage drops below the feedback threshold.
Since the zero-crossing comparator prevents the
switching regulator from sinking current, the controller
must skip pulses. Therefore, the controller regulates the
valley of the output ripple under light-load conditions.
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads (Figure 4). This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The zero-crossing comparator senses the inductor cur-
rent across the low-side MOSFET (PGND to LX_). Once
VPGND - VLX_ drops below the 3mV zero-crossing cur-
rent-sense threshold, the comparator forces DL_ low
(Figure 3). This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
tinuous and discontinuous inductor-current operation
(also known as the “critical conduction” point). The
load-current level at which PFM/PWM crossover
occurs, ILOAD(SKIP), is given by:
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
IVVV
Vf L
LOAD SKIP OUT IN OUT
IN SW
()
( )
=×× ×
−
2
Table 4. FSEL Configuration Table
FSEL SWITCHING FREQUENCY
VCC 500kHz
REF 300kHz
GND 200kHz
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 23
Output Voltage
DC output accuracy specifications in the Electrical
Characteristics table refer to the error-comparator’s
threshold. When the inductor continuously conducts,
the MAX1533/MAX1537 regulate the peak of the output
ripple, so the actual DC output voltage is lower than the
slope-compensated trip level by 50% of the output rip-
ple voltage. For PWM operation (continuous conduc-
tion), the output voltage is accurately defined by the
following equation:
where VNOM is the nominal output voltage, ASLOPE
equals 1%, and VRIPPLE is the output ripple voltage
(VRIPPLE = ESR x ∆IINDUCTOR as described in the
Output Capacitor Selection section).
In discontinuous conduction (IOUT < ILOAD(SKIP)), the
MAX1533/MAX1537 regulate the valley of the output
ripple, so the output voltage has a DC regulation level
higher than the error-comparator threshold. For PFM
operation (discontinuous conduction), the output volt-
age is approximately defined by the following equation:
where VNOM is the nominal output voltage, fOSC is the
maximum switching frequency set by the internal oscil-
lator, fSW is the actual switching frequency, and IIDLE is
the idle-mode inductor current when pulse skipping.
Adjustable/Fixed Output Voltages
(Dual-Mode Feedback)
Connect FB3 and FB5 to GND to enable the fixed
SMPS output voltages (3.3V and 5V, respectively), set
by a preset, internal resistive voltage-divider connected
between CSL_ and analog ground. Connect a resistive
voltage-divider at FB_ between CSL_ and GND to
adjust the respective output voltage between 1V and
5.5V (Figure 5). Choose R2 (resistance from FB to
GND) to be about 10kΩand solve for R1 (resistance
from OUT to FB) using the equation:
where VFB_ = 1V nominal.
RR
V
V
OUT
FB
12 1
_
_
=⎛
⎝
⎜⎞
⎠
⎟
−
VV
f
fI ESR
OUT PFM NOM SW
OSC IDLE() =+
⎛
⎝
⎜⎞
⎠
⎟×
1
2
VV
AV
V
V
OUT PWM NOM SLOPE NOM
IN
RIPPLE
()
=⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
12
- -
tON(SKIP) ≥ IIDLEL
VIN - VOUT
INDUCTOR CURRENT
ILOAD(SKIP)
TIME
ON-TIME
0
CSL
TO ERROR
AMPLIFIER
REF
(2.0V)
R
12R
FB
FIXED OUTPUT
FB = GND
ADJUSTABLE
OUTPUT
Figure 4. Pulse-Skipping/Discontinuous Crossover Point Figure 5. Dual-Mode Feedback Decoder
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
24 ______________________________________________________________________________________
When adjusting both output voltages, set the 3.3V
SMPS lower than the 5V SMPS. LDO5 connects to the
5V output (CSL5) through an internal switch only when
CSL5 is above the LDO5 bootstrap threshold (4.56V).
Similarly, LDO3 connects to the 3.3V output (CSL3)
through an internal switch only when CSL3 is above the
LDO3 bootstrap threshold (2.91V). Bootstrapping works
most effectively when the fixed output voltages are
used. Once LDO_ is bootstrapped from CSL_, the inter-
nal linear regulator turns off. This reduces internal
power dissipation and improves efficiency at higher
input voltage.
Current-Limit Protection (ILIM_)
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor cur-
rent. If the magnitude of the current-sense signal
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). At the next
rising edge of the internal oscillator, the PWM controller
does not initiate a new cycle unless the current-sense
signal drops below the current-limit threshold. The
actual maximum load current is less than the peak cur-
rent-limit threshold by an amount equal to half of the
inductor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
(VOUT / VIN).
In forced-PWM mode, the MAX1533/MAX1537 also
implement a negative current limit to prevent excessive
reverse inductor currents when VOUT is sinking current.
The negative current-limit threshold is set to approxi-
mately 120% of the positive current limit and tracks the
positive current limit when ILIM_ is adjusted.
Connect ILIM_ to VCC for the 75mV default threshold, or
adjust the current-limit threshold with an external resis-
tor-divider at ILIM_. Use a 2µA to 20µA divider current
for accuracy and noise immunity. The current-limit
threshold adjustment range is from 50mV to 200mV. In
the adjustable mode, the current-limit threshold voltage
equals precisely 1/10th the voltage seen at ILIM_. The
logic threshold for switchover to the 75mV default value
is approximately VCC - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the dif-
ferential current-sense signals seen by CSH_ and
CSL_. Place the IC close to the sense resistor with
short, direct traces, making a Kelvin-sense connection
to the current-sense resistor.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large VIN -
VOUT differential exists. The high-side gate drivers
(DH_) source and sink 2A, and the low-side gate dri-
vers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
diode-capacitor charge pumps at BST_ (Figure 6) while
the DL_ synchronous-rectifier drivers are powered
directly by the fixed 5V linear regulator (LDO5).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly;
otherwise, the sense circuitry in the MAX1533/
MAX1537 interprets the MOSFET gates as “off” while
charge actually remains. Use very short, wide traces (50
to 100 mils wide if the MOSFET is 1 inch from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω(typ) on-resistance. This helps pre-
vent DL_ from being pulled up due to capacitive cou-
pling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX_) quickly switch-
es from ground to VIN. Applications with high input volt-
ages and long inductive driver traces may require
additional gate-to-source capacitance to ensure fast-
rising LX_ edges do not pull up the low-side MOSFETs’
gate, causing shoot-through currents. The capacitive
coupling between LX_ and DL_ created by the
MOSFET’s gate-to-drain capacitance (CRSS), gate-to-
source capacitance (CISS - CRSS), and additional
board parasitics should not exceed the following
minimum threshold:
Lot-to-lot variation of the threshold voltage may cause
problems in marginal designs. Alternatively, adding a
resistor less than 10Ωin series with BST_ may remedy
the problem by increasing the turn-on time of the high-
side MOSFET without degrading the turn-off time
(Figure 6).
VV
C
C
GS TH IN RSS
ISS
()
>⎛
⎝
⎜⎞
⎠
⎟
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 25
Power-Good Output (PGOOD)
PGOOD is the open-drain output of a comparator that
continuously monitors both SMPS output voltages for
undervoltage conditions. PGOOD is actively held low in
shutdown (SHDN or ON3 or ON5 = GND), soft-start,
and soft-shutdown. Once the digital soft-start termi-
nates, PGOOD becomes high impedance as long as
both outputs are above 90% of the nominal regulation
voltage set by FB_. PGOOD goes low once either
SMPS output drops 10% below its nominal regulation
point, an output overvoltage fault occurs, or either
SMPS controller is shut down. For a logic-level PGOOD
output voltage, connect an external pullup resistor
between PGOOD and VCC. A 100kΩpullup resistor
works well in most applications.
PGOOD is independent of the fault protection states
OVP and UVP.
Fault Protection
Output Overvoltage Protection (OVP)
If the output voltage of either SMPS rises above 111%
of its nominal regulation voltage and the OVP protection
is enabled (OVP = GND), the controller sets the fault
latch, pulls PGOOD low, shuts down both SMPS con-
trollers, and immediately pulls DH_ low and forces DL_
MAX1533
MAX1537
LDO5
BST
DH
LX
(RBST)*
(CNL)*
DBST
CBST
CBYP
INPUT (VIN)
NH
L
LDO5
DL
GND
NL
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
THE SWITCHING-NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 6. Optional Gate-Driver Circuitry
POR
ENABLE OVP
ENABLE UVP
BLANK
(POWER-UP)
POWER-
GOOD
FAULT
0.9 x
INT REF_
0.7 x
INT REF_
1.11 x
INT REF_
FAULT
LATCH
TIMER
POWER-GOOD
FAULT
PROTECTION
INTERNAL FB
Figure 7. Power-Good and Fault Protection
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
26 ______________________________________________________________________________________
high. This turns on the synchronous-rectifier MOSFETs
with 100% duty, rapidly discharging the output capaci-
tors and clamping both outputs to ground. However,
immediately latching DL_ high typically causes slightly
negative output voltages due to the energy stored in
the output LC at the instant the OVP occurs. If the load
cannot tolerate a negative voltage, place a power
Schottky diode across the output to act as a reverse-
polarity clamp. If the condition that caused the overvolt-
age persists (such as a shorted high-side MOSFET),
the battery fuse blows. Cycle VCC below 1V or toggle
either ON3, ON5, or SHDN to clear the fault latch and
restart the SMPS controllers.
Connect OVP to VCC to disable the output overvoltage
protection.
Output Undervoltage Protection (UVP)
Each SMPS controller includes an output UVP protec-
tion circuit that begins to monitor the output 6144 clock
cycles (1 / fOSC) after that output is enabled (ON_
pulled high). If either SMPS output voltage drops below
70% of its nominal regulation voltage and the UVP pro-
tection is enabled (UVP = GND), the UVP circuit sets
the fault latch, pulls PGOOD low, and shuts down both
controllers using discharge mode (see the Output
Discharge (Soft-Shutdown) section). When an SMPS
output voltage drops to 0.3V, its synchronous rectifier
turns on, clamping the discharged output to GND.
Cycle VCC below 1V or toggle either ON3, ON5, or
SHDN to clear the fault latch and restart the SMPS
controllers.
Connect UVP to VCC to disable the output undervoltage
protection.
Table 5. Operating Modes Truth Table
MODE CONDITION COMMENT
Power-Up LDO5 < UVLO threshold.
Transitions to discharge mode after VIN POR and after REF
becomes valid. LDO5, LDO3, REF remain active. DL_ is active
if OVP is low.
Run SHDN = high, ON3 or ON5 enabled. Normal operation.
Output Overvoltage
Protection (OVP)
Either output > 111% of nominal level,
OVP = low. Exited by POR or cycling SHDN, ON3, or ON5.
Output Undervoltage
Protection (UVP)
Either output < 70% of nominal level, UVP
is enabled 6144 clock cycles (1 / fOSC)
after the output is enabled and UVP = low.
Exited by POR or cycling SHDN, ON3, or ON5. If OVP is not
high, DL3 and DL5 go high after discharge.
Discharge
OVP is low and either SMPS output is still
high in either standby mode or shutdown
mode.
Discharge switch (10Ω) connects CSL_ to PGND. This is a
temporary state entered when LDO5 is undervoltage or on the
way to output UVLO, standby, shutdown, or thermal-shutdown
states. One SMPS can be in discharge mode while the other is
in run mode. If both outputs are discharged to 0.3V (on CSL_),
discharge mode transitions to the appropriate state.
Standby ON5 and ON3 < startup threshold,
SHDN = high. DL_ stays high if OVP is low. LDO3, LDO5 active.
Shutdown SHDN = low. All circuitry off.
Thermal Shutdown TJ > +160°C. Exited by POR or cycling SHDN, ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
Switchover Fault Excessive current on LDO3 or LDO5
switchover transistors.
Exited by POR or cycling SHDN, ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 27
Thermal Fault Protection
The MAX1533/MAX1537 feature a thermal fault-protec-
tion circuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch, pulls
PGOOD low, and shuts down both SMPS controllers
using discharge mode (see the Output Discharge (Soft-
Shutdown) section). When an SMPS output voltage
drops to 0.3V, its synchronous rectifier turns on, clamp-
ing the discharged output to GND. Cycle VCC below 1V
or toggle either ON3, ON5, or SHDN to clear the fault
latch and restart the controllers after the junction tem-
perature cools by 15°C.
Auxiliary LDO Detailed
Description (MAX1537 Only)
The MAX1537 includes an auxiliary linear regulator that
delivers up to 150mA of load current. The output
(LDOA) can be preset to 12V, ideal for PCMCIA power
requirements, and for biasing the gates of load switch-
es in a portable device. In adjustable mode, LDOA can
be set to anywhere from 5V to 23V. The auxiliary regu-
lator has an independent ON/OFF control, allowing it to
be shut down when not needed, reducing power con-
sumption when the system is in a low-power state.
A flyback-winding control loop regulates a secondary
winding output, improving cross-regulation when the pri-
mary output is lightly loaded or when there is a low
input-output differential voltage. If VINA - VLDOA falls
below 0.8V, the low-side switch is turned on for a time
equal to 33% of the switching period. This reverses the
inductor (primary) current, pulling current from the out-
put filter capacitor and causing the flyback transformer
to operate in forward mode. The low impedance pre-
sented by the transformer secondary in forward mode
dumps current into the secondary output, charging up
the secondary capacitor and bringing VINA - VLDOA
back into regulation. The secondary feedback loop does
not improve secondary output accuracy in normal fly-
back mode, where the main (primary) output is heavily
loaded. In this condition, secondary output accuracy is
determined by the secondary rectifier drop, transformer
turns ratio, and accuracy of the main output voltage.
Adjustable LDOA Voltage
(Dual-Mode Feedback)
Connect ADJA to GND to enable the fixed, preset 12V
auxiliary output. Connect a resistive voltage-divider at
ADJA between LDOA and GND to adjust the respective
output voltage between 5V and 23V (Figure 8). Choose
R2 (resistance from ADJA to GND) to be approximately
100kΩand solve for R1 (resistance from LDOA to
ADJA) using the following equation:
where VADJA = 2V nominal.
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
•Input Voltage Range. The maximum value
(VIN(MAX)) must accommodate the worst-case, high
AC-adapter voltage. The minimum value (VIN(MIN))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery-selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
RR
V
V
LDOA
ADJA
12 1 =⎛
⎝
⎜⎞
⎠
⎟
-
Figure 8. Linear-Regulator Functional Diagram
FIXED 12V
INA
ADJA
LDOA
ONA
0.15V
SECONDARY
FEEDBACK
REF (2.0V)
5R
R
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
28 ______________________________________________________________________________________
•Maximum Load Current. There are two values to
consider. The peak load current (ILOAD(MAX)) deter-
mines the instantaneous component stresses and fil-
tering requirements and thus drives output-capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (ILOAD) determines the thermal stresses and
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents.
•Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN2. The opti-
mum frequency is also a moving target, due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
•Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output ripple due to increased ripple currents. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 20% and 50% ripple current. When pulse
skipping (SKIP low and light loads), the inductor
value also determines the load-current value at
which PFM/PWM switchover occurs.
Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
For example: ILOAD(MAX) = 5A, VIN = 12V, VOUT = 5V,
fOSC = 300kHz, 30% ripple current or LIR = 0.3.
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Most
inductor manufacturers provide inductors in standard
values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also
look for nonstandard values, which can provide a better
compromise in LIR across the input voltage range. If
using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values. For
the selected inductance value, the actual peak-to-peak
inductor ripple current (∆IINDUCTOR) is defined by:
Ferrite cores are often the best choice, although pow-
dered iron is inexpensive and can work well at 200kHz.
The core must be large enough not to saturate at the
peak inductor current (IPEAK):
Transformer Design (For the MAX1537
Auxiliary Output)
A coupled inductor or transformer can be substituted
for the inductor in the 5V SMPS to create an auxiliary
output (Figure 1). The MAX1537 is particularly well suit-
ed for such applications because the secondary feed-
back threshold automatically triggers DL5 even if the
5V output is lightly loaded.
The power requirements of the auxiliary supply must be
considered in the design of the main output. The trans-
former must be designed to deliver the required current
in both the primary and the secondary outputs with the
proper turns ratio and inductance. The power ratings of
the synchronous-rectifier MOSFETs and the current
limit in the MAX1537 must also be adjusted according-
ly. Extremes of low input-output differentials, widely dif-
ferent output loading levels, and high turns ratios can
further complicate the design due to parasitic trans-
former parameters such as interwinding capacitance,
secondary resistance, and leakage inductance. Power
from the main and secondary outputs is combined to
get an equivalent current referred to the main output.
Use this total current to determine the current limit (see
the Setting the Current Limit section):
ITOTAL = PTOTAL / VOUT5
where ITOTAL is the equivalent output current referred
to the main output, and PTOTAL is the sum of the output
power from both the main output and the secondary
output:
II I
PEAK LOAD MAX INDUCTOR
=+
()
∆
2
∆IVVV
Vf L
INDUCTOR OUT IN OUT
IN OSC
=
()
-
LVV
AH .
.=×
()
×××
=
512
503
650
-5V
12V 300kHz µ
LVV
OUT IN
=
()
- V
V f I LIR
OUT
IN OSC LOAD(MAX)
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 29
where LPRIMARY is the primary inductance, N is the
transformer turns ratio, VSEC is the minimum required
rectified secondary voltage, VFWD is the forward drop
across the secondary rectifier, VOUT5(MIN) is the mini-
mum value of the main output voltage, and VRECT is the
on-state voltage drop across the synchronous-rectifier
MOSFET. The transformer secondary return is often con-
nected to the main output voltage instead of ground to
reduce the necessary turns ratio. In this case, subtract
VOUT5 from the secondary voltage (VSEC - VOUT5) in the
transformer turns-ratio equation above. The secondary
diode in coupled-inductor applications must withstand
flyback voltages greater than 60V. Common silicon recti-
fiers, such as the 1N4001, are also prohibited because
they are too slow. Fast silicon rectifiers such as the
MURS120 are the only choice. The flyback voltage
across the rectifier is related to the VIN - VOUT difference,
according to the transformer turns ratio:
VFLYBACK = VSEC + (VIN - VOUT5) x N
where N is the transformer turns ratio (secondary wind-
ings/primary windings), and VSEC is the maximum sec-
ondary DC output voltage. If the secondary winding is
returned to VOUT5 instead of ground, subtract VOUT5
from VFLYBACK in the equation above. The diode’s
reverse-breakdown voltage rating must also accommo-
date any ringing due to leakage inductance. The
diode’s current rating should be at least twice the DC
load current on the secondary output.
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low VIN - VOUT dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The total output voltage sag is the sum of the voltage
sag while the inductor is ramping up, and the voltage
sag before the next pulse can occur.
where DMAX is the maximum duty factor (see the
Electrical Characteristics table), T is the switching period
(1 / fOSC), and ∆T equals VOUT / VIN x T when in PWM
mode, or L x 0.2 x IMAX / (VIN - VOUT) when in skip
mode. The amount of overshoot during a full-load to no-
load transient due to stored inductor energy can be
calculated as:
Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The
peak inductor current occurs at ILOAD(MAX) plus half
the ripple current; therefore:
where ILIMIT equals the minimum current-limit threshold
voltage divided by the current-sense resistance
(RSENSE). For the default setting, the minimum current-
limit threshold is 70mV.
Connect ILIM_ to VCC for the default current-limit
threshold. In adjustable mode, the current-limit thresh-
old is precisely 1/10th the voltage seen at ILIM_. For an
adjustable threshold, connect a resistive divider from
REF to analog ground (GND) with ILIM_ connected to
the center tap. The external 500mV to 2V adjustment
range corresponds to a 50mV to 200mV current-limit
threshold. When adjusting the current limit, use 1% tol-
erance resistors and a divider current of approximately
10µA to prevent significant inaccuracy in the current-
limit tolerance.
The current-sense method (Figure 9) and magnitude
determine the achievable current-limit accuracy and
power loss. Typically, higher current-sense limits pro-
vide tighter accuracy, but also dissipate more power.
Most applications employ a current-limit threshold
(VLIMIT) of 50mV to 100mV, so the sense resistor can
be determined by:
RSENSE = VLIMIT / ILIM
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure
9a. This configuration constantly monitors the inductor
current, allowing accurate current-limit protection.
II I
LIMIT LOAD MAX INDUCTOR
>+
⎛
⎝
⎜⎞
⎠
⎟
() ∆
2
V
IL
CV
SOAR
LOAD MAX
OUT OUT
=
()
()
∆2
2
V
LI
CVD V
ITT
C
SAG
LOAD MAX
OUT IN MAX OUT
LOAD MAX
OUT
=
()
×
()
+
()
()
()
∆
∆∆
2
2 -
-
NVV
VVV
SEC FWD
OUT RECT SENSE
=+
++
5
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
30 ______________________________________________________________________________________
Alternatively, high-power applications that do not
require highly accurate current-limit protection may
reduce the overall power dissipation by connecting a
series RC circuit across the inductor (Figure 9b) with an
equivalent time constant:
where RLis the inductor’s series DC resistance. In this
configuration, the current-sense resistance equals the
inductor’s DC resistance (RSENSE = RL). Use the worst-
case inductance and RLvalues provided by the induc-
tor manufacturer, adding some margin for the induc-
tance drop over temperature and load.
Output Capacitor Selection
The output filter capacitor must have low enough equiv-
alent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. The output capaci-
tance must be high enough to absorb the inductor
energy while transitioning from full-load to no-load con-
ditions without tripping the overvoltage fault protection.
When using high-capacitance, low-ESR capacitors (see
the Output-Capacitor Stability Considerations section),
L
RCR
LEQ EQ
=×
Figure 9. Current-Sense Configurations
MAX1533
MAX1537
COUT
INPUT (VIN)
INDUCTOR
CIN
b) LOSSLESS INDUCTOR SENSING
CSL_
CSH_
GND
DL_
DH_
LX_
CEQ
REQ
MAX1533
MAX1537
COUT
INPUT (VIN)
NH
NL
NH
NL
L
CIN
DL
DL
a) OUTPUT SERIES RESISTOR SENSING
GND
DL_
DH_
LX_
CSL_
CSH_
RSENSE
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 31
the filter capacitor’s ESR dominates the output voltage
ripple. So the output capacitor’s size depends on the
maximum ESR required to meet the output voltage rip-
ple (VRIPPLE(P-P)) specifications:
In idle mode, the inductor current becomes discontinu-
ous, with peak currents set by the idle-mode current-
sense threshold (VIDLE = 0.2VLIMIT). In idle mode, the
no-load output ripple can be determined as follows:
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent VSAG and VSOAR from
causing problems during load transients. Generally,
once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
is no longer a problem (see the VSAG and VSOAR equa-
tions in the Transient Response section). However, low-
capacity filter capacitors typically have high-ESR zeros
that may affect the overall stability (see the Output-
Capacitor Stability Considerations).
Output-Capacitor Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The boundary of insta-
bility is given by the following equation:
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use at
the time of publication have typical ESR zero frequen-
cies of 25kHz. In the design example used for inductor
selection, the ESR needed to support 25mVP-P ripple is
25mV / 1.5A = 16.7mΩ. One 220µF/4V Sanyo polymer
(TPE) capacitor provides 15mΩ(max) ESR. This results
in a zero at 48kHz, well within the bounds of stability.
For low-input-voltage applications where the duty cycle
exceeds 50% (VOUT / VIN ≥50%), the output ripple volt-
age should not be greater than twice the internal slope-
compensation voltage:
VRIPPLE ≤0.02 x VOUT
where VRIPPLE equals ∆IINDUCTOR x RESR. The worst-
case ESR limit occurs when VIN = 2 x VOUT, so the
above equation can be simplified to provide the follow-
ing boundary condition:
RESR ≤0.04 x L x fOSC
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precau-
tions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: short/long pulses or cycle skip-
ping resulting in a lower switching frequency. Instability
occurs due to noise on the output or because the ESR
is so low that there is not enough voltage ramp in the
output voltage signal. This “fools” the error comparator
into triggering too early or skipping a cycle. Cycle skip-
ping is more annoying than harmful, resulting in nothing
worse than increased output ripple. However, it can
indicate the possible presence of loop instability due to
insufficient ESR. Loop instability can result in oscilla-
tions at the output after line or load steps. Such pertur-
bations are usually damped, but can cause the output
voltage to rise above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC-current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
For an out-of-phase regulator, the total RMS current in
the input capacitor is a function of the load currents, the
input currents, the duty cycles, and the amount of over-
lap as defined in Figure 10.
The 40/60 optimal interleaved architecture of the
MAX1533/MAX1537 allows the input voltage to go as
low as 8.3V before the duty cycles begin to overlap.
ff
where f RC
ESR OSC
ESR ESR OUT
≤
=
π
π
1
2
VVR
R
RIPPLE P P IDLE ESR
SENSE
()
−=
V R I LIR
RIPPLE P P ESR LOAD MAX() ( )
−=
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
32 ______________________________________________________________________________________
This offers improved efficiency over a regular 180°out-
of-phase architecture where the duty cycles begin to
overlap below 10V. Figure 10 shows the input-capacitor
RMS current vs. input voltage for an application that
requires 5V/5A and 3.3V/5A. This shows the improve-
ment of the 40/60 optimal interleaving over 50/50 inter-
leaving and in-phase operation.
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. Choose a capacitor that has less than
10°C temperature rise at the RMS input current for opti-
mal reliability and lifetime.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN)
should be roughly equal to the losses at VIN(MAX), with
lower losses in between. If the losses at VIN(MIN) are
significantly higher, consider increasing the size of NH.
Conversely, if the losses at VIN(MAX) are significantly
higher, consider reducing the size of NH. If VIN does
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (NH) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (NL) that has the lowest
possible on-resistance (RDS(ON)), comes in a moder-
ate-sized package (i.e., SO-8, DPAK, or D2PAK), and is
reasonably priced. Ensure that the MAX1533/MAX1537
DL_ gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic drain-to-gate capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems may occur. Switching losses are not an issue for
the low-side MOSFET since it is a zero-voltage
switched device when used in the step-down topology.
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worst-
case power dissipation due to resistance occurs at
minimum input voltage:
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
RDS(ON) required to stay within package power-dissi-
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (RDS(ON)) losses. High-side switching
losses do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult, since
it must allow for difficult-to-quantify factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board
layout characteristics. The following switching loss cal-
culation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably includ-
ing verification using a thermocouple mounted on NH:
where CRSS is the reverse transfer capacitance of NH,
and IGATE is the peak gate-drive source/sink current
(1A typ).
PD N Switching
VCfI
I
H
IN MAX RSS SW LOAD
GATE
( )
()
=
()
2
PD N sistive V
VIR
HOUT
IN LOAD DS ON
( Re ) ()
=⎛
⎝
⎜⎞
⎠
⎟
()
2
Figure 10. Input RMS Current
INPUT CAPACITOR RMS CURRENT
vs. INPUT VOLTAGE
VIN (V)
IRMS (A)
181612 14108
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
620
IN PHASE
5V/5A AND 3.3V/5A
50/50 INTERLEAVING
40/60 OPTIMAL
INTERLEAVING
INPUT RMS CURRENT FOR INTERLEAVED OPERATION
INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION
(I
OUT5
- I
IN
)
2
(D
LX5
- D
OL
) + (I
OUT3
- I
IN
)
2
(D
LX3
- D
OL
) +
(I
OUT5
+ I
OUT3
- I
IN
)2 D
OL
+ I
IN2
(1 - D
LX5
- D
LX3
+ D
OL
)
D
LX5
=
V
OUT
(V
IN
- V
OUT
)
V
IN
I
RMS
= I
LOAD
D
OL
= DUTY-CYCLE OVERLAP FRACTION
V
OUT5
V
IN
D
LX3
= V
OUT3
V
IN
( )
IRMS =
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 33
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC-adapter voltages
are applied, due to the squared term in the switching-
loss equation (C x VIN2x fSW). If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when subjected to
VIN(MAX), consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy-overload conditions that are
greater than ILOAD(MAX) but are not high enough to
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the cir-
cuit to tolerate:
where ILIMIT is the peak current allowed by the current-
limit circuit, including threshold tolerance and sense-
resistance variation. The MOSFETs must have a
relatively large heatsink to handle the overload power
dissipation.
Choose a Schottky diode (DL) with a forward-voltage
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3rd the load current. This diode is optional
and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
where QGATE is the total gate charge specified in the
high-side MOSFET’s data sheet. For example, assume
the FDS6612A n-channel MOSFET is used on the high
side. According to the manufacturer’s data sheet, a sin-
gle FDS6612A has a maximum gate charge of 13nC
(VGS = 5V). Using the above equation, the required
boost capacitance is:
Selecting the closest standard value. This example
requires a 0.1µF ceramic capacitor.
Applications Information
Duty-Cycle Limits
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). However,
keep in mind that the transient performance gets worse
as the step-down regulators approach the dropout volt-
age, so bulk output capacitance must be added (see
the voltage sag and soar equations in the Design
Procedure section). The absolute point of dropout
occurs when the inductor current ramps down during
the off-time (∆IDOWN) as much as it ramps up during
the on-time (∆IUP). This results in a minimum operating
voltage defined by the following equation:
where VCHG and VDIS are the parasitic voltage drops in
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
Maximum Input Voltage
The MAX1533/MAX1537 controllers include a minimum
on-time specification, which determines the maximum
input operating voltage that maintains the selected
switching frequency (see the Electrical Characteristics
table). Operation above this maximum input voltage
results in pulse-skipping operation, regardless of the
operating mode selected by SKIP. At the beginning of
each cycle, if the output voltage is still above the feed-
VVVh
DVV
IN MIN OUT CHG MAX OUT DIS() =+ +
⎛
⎝
⎜⎞
⎠
⎟+
()
11 -
CnC
mV F
BST == .
13
200 0 065µ
CQ
mV
BST GATE
= 200
II I
LOAD LIMIT INDUCTOR
=⎛
⎝
⎜⎞
⎠
⎟
-
∆
2
PD N sistive V
VIR
LOUT
IN MAX LOAD DS ON
( Re )
() (
)
=⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
()
12
-
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
34 ______________________________________________________________________________________
back-threshold voltage, the controller does not trigger
an on-time pulse, effectively skipping a cycle. This
allows the controller to maintain regulation above the
maximum input voltage, but forces the controller to
effectively operate with a lower switching frequency.
This results in an input threshold voltage at which the
controller begins to skip pulses (VIN(SKIP)):
where fOSC is the switching frequency selected by FSEL.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 11). If possible, mount all of the power compo-
nents on the top side of the board, with their ground
terminals flush against one another. Follow these guide-
lines for good PC board layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩof excess trace resistance caus-
es a measurable efficiency penalty.
• Minimize current-sensing errors by connecting CSH_
and CSL_ directly across the current-sense resistor
(RSENSE_).
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF,
FB_, CSH_, CSL_).
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (NL_ source, CIN, COUT_, and DL_
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite NL_
and NH_ to keep LX_, GND, DH_, and the DL_ gate-
drive lines short and wide. The DL_ and DH_ gate
traces must be short and wide (50 to 100 mils wide if
the MOSFET is 1 inch from the controller IC) to keep
the driver impedance low and for proper adaptive
dead-time sensing.
3) Group the gate-drive components (BST_ diode and
capacitor, LDO5 bypass capacitor) together near
the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 11. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power compo-
nents go; and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single point
directly at the IC.
5) Connect the output power planes directly to the out-
put-filter-capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
VV
ft
IN SKIP OUT OSC ON MIN
() ()
=⎛
⎝
⎜⎞
⎠
⎟
1
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 35
Figure 11. PC Board Layout
VIA TO POWER
GROUND
MAX1533
TOP LAYER
MAX1533
BOTTOM LAYER
VIA TO REF
BYPASS CAPACITOR
CONNECT GND AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
CONNECT THE
EXPOSED PAD TO
ANALOG GND
INDUCTOR
COUT
COUT
C
IN
INPUT
KELVIN-SENSE VIAS
UNDER THE SENSE
RESISTOR
(SEE THE EVALUATION KIT)
GROUND
OUTPUT
INDUCTOR
COUT
C
IN
INPUT
GROUNDOUTPUT
DH
LX
DL
HIGH-POWER LAYOUT LOW-POWER LAYOUT
DUAL
n-CHANNEL
MOSFET
SINGLE
n-CHANNEL
MOSFETS
VIA TO REF PIN
VIA TO VCC
BYPASS CAPACITOR VIA TO VCC PIN
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
36 ______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 6890
PROCESS: BiCMOS
CSL5
FB5
DL5
PGND
FB3
CSL3
DL3
LDO3
LDO5
ON3
ONA
FSEL
ILIM5
REF
GND
ADJA 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
DH3
BST3
LX3
CSH3
UVP
PGOOD
PGDLY
VCC
INA
SHDN
SKIP
DH5
BST5
LX5
IN
CSH5
LDOA
THIN QFN
6mm x 6mm
MAX1537
TOP VIEW
ILIM3
OVP
ON5
Pin Configurations (continued)
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 37
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
0.15 C B
0.15 C A
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45∞
L
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
k
LL
DETAIL B
L
L1
e
XXXXX
MARKING
F
1
2
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
COMMON DIMENSIONS
3.353.15
T2855-1 3.25 3.353.15 3.25
MAX.
3.20
EXPOSED PAD VARIATIONS
3.00T2055-2 3.10
D2
NOM.MIN.
3.203.00 3.10
MIN.
E2
NOM. MAX.
NE
ND
PKG.
CODES
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
NOTES:
SYMBOL
PKG.
N
L1
e
E
D
b
A3
A
A1
k
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
JEDEC
T1655-1 3.203.00 3.10 3.00 3.10 3.20
0.70 0.800.75
4.90
4.90
0.25
0.25
0
--
4
WHHB
4
16
0.350.30
5.10
5.105.00
0.80 BSC.
5.00
0.05
0.20 REF.
0.02
MIN. MAX.NOM.
16L 5x5
3.10
T3255-2 3.00 3.20 3.00 3.10 3.20
2.70
T2855-2 2.60 2.602.80 2.70 2.80
L0.30 0.500.40
------
WHHC
20
5
5
5.00
5.00
0.30
0.55
0.65 BSC.
0.45
0.25
4.90
4.90
0.25
0.65
--
5.10
5.10
0.35
20L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-1
28
7
7
5.00
5.00
0.25
0.55
0.50 BSC.
0.45
0.25
4.90
4.90
0.20
0.65
--
5.10
5.10
0.30
28L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-2
32
8
8
5.00
5.00
0.40
0.50 BSC.
0.30
0.25
4.90
4.90
0.50
--
5.10
5.10
32L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
0.20 0.25 0.30
DOWN
BONDS
ALLOWED
NO
YES3.103.00 3.203.103.00 3.20T2055-3
3.103.00 3.203.103.00 3.20T2055-4
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-7 2.60 2.70 2.80 2.60 2.70 2.80
3.203.00 3.10T3255-3 3.203.00 3.10
3.203.00 3.10T3255-4 3.203.00 3.10
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
3.203.00T1655-2 3.10 3.00 3.10 3.20 YES
NO3.203.103.003.10T1655N-1 3.00 3.20
3.353.15T2055-5 3.25 3.15 3.25 3.35 Y
3.35
3.15T2855N-1 3.25 3.15 3.25 3.35 N
3.35
3.15T2855-8 3.25 3.15 3.25 3.35 Y
3.203.10T3255N-1 3.00 NO
3.203.103.00
L
0.40
0.40
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
SEE COMMON DIMENSIONS TABLE
±0.15
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
F
2
2
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
MAX1533/MAX1537
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
e e
LL
A1 A2 A
E/2
E
D/2
D
E2/2
E2
(NE-1) X e
(ND-1) X e
e
D2/2
D2
b
k
k
L
C
L
C
L
C
L
C
L
E1
2
21-0141
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
L1
L
e
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
3. N IS THE TOTAL NUMBER OF TERMINALS.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
E
2
2
21-0141
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
ENGLISH • ???? • ??? • ???
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Maxim > Products > Power and Battery M anagement
MAX1533, MAX1537
High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers
High-Efficiency, 5x Output, Main-Power-Supply Controllers with Synchronous Rectification,
Intended for Main 5V/3.3V Power Generation in Battery-Powered Systems
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2.
Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt. More: SeeFull Data
Sheet or Part Naming Conventions.
3.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product
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4.
Devices: 1-6 of 6
MAX1533
Free
Sam ple
Buy
Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free?
Materials Analysis
MAX1533ETJ
THIN QFN;32 pin;26 mm
Dwg: 21-0140L (PDF)
Use pkgcode/variation: T3255-4*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX1533ETJ-T
THIN QFN;32 pin;26 mm
Dwg: 21-0140L (PDF)
Use pkgcode/variation: T3255-4*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX1533ETJ+
THIN QFN;32 pin;26 mm
Dwg: 21-0140L (PDF)
Use pkgcode/variation: T3255+4*
-40C to +85C
RoHS/Lead-Free: Lead Free
Materials Analysis
MAX1533ETJ+T
THIN QFN;32 pin;26 mm
Dwg: 21-0140L (PDF)
Use pkgcode/variation: T3255+4*
-40C to +85C
RoHS/Lead-Free: Lead Free
Materials Analysis
MAX1537
Free
Sam ple
Buy
Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free?
Materials Analysis
MAX1537ETX
THIN QFN;36 pin;37 mm
Dwg: 21-0141H (PDF)
Use pkgcode/variation: T3666-3*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX1537ETX-T
THIN QFN;36 pin;37 mm
Dwg: 21-0141H (PDF)
Use pkgcode/variation: T3666-3*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
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Document Ref.: 1 9 -3501; Rev 0; 2004-11-11
This page last modified: 20 06 -11-10
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