X28HC64 (R) 64k, 8k x 8-Bit Data Sheet August 28, 2009 5 Volt, Byte Alterable EEPROM Features The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil's proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64 is a 5V only device. It features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs. * 70ns access time The X28HC64 supports a 64-byte page write operation, effectively providing a 32s/byte write cycle, and enabling the entire memory to be typically written in 0.25 seconds. The X28HC64 also features DATA Polling and Toggle Bit Polling, two methods providing early end of write detection. In addition, the X28HC64 includes a user-optional software data protection mode that further enhances Intersil's hardware write protect capability. Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. FN8109.2 * Simple byte and page write - Single 5V supply - No external high voltages or VPP control circuits - Self-timed - No erase before write - No complex programming algorithms - No overerase problem * Low power CMOS - 40mA active current max. * 200A standby current max. * Fast write cycle times - 64-byte page write operation - Byte or page write cycle: 2ms typical - Complete memory rewrite: 0.25 sec. typical - Effective byte write cycle time: 32s typical * Software data protection * End of write detection - DATA polling - Toggle bit * High reliability - Endurance: 100000 cycles - Data retention: 100 years * JEDEC approved byte-wide pin out * Pb-free available (RoHS compliant) Pinouts A9 A4 6 23 A11 A3 7 X28HC64 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 VSS 14 15 I/O3 1 NC A8 24 1 32 31 30 A6 5 29 A8 A5 6 28 A9 A4 7 27 A11 A3 8 26 NC A2 9 A1 X28HC64 (Top View) 25 OE 10 24 A10 A0 11 23 CE NC 12 22 I/O7 13 21 14 15 16 17 18 19 20 I/O6 I/O0 I/O5 25 5 2 VCC 4 A5 3 WE A6 4 I/O4 NC NC 26 I/O3 3 A12 A7 NC WE VSS VCC 27 A7 28 2 I/O2 1 I/O1 NC A12 NC X28HC64 (32 LD PLCC) TOP VIEW X28HC64 (28 LD PDIP, SOIC) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X28HC64 Ordering Information PART NUMBER PART MARKING X28HC64J-70* X28HC64J-70 RR X28HC64JIZ-70* (Note 1) X28HC64JI-70 ZRR X28HC64JZ-70* (Note 1) TEMPERATURE RANGE (C) ACCESS TIME (ns) 0 to +70 70 PACKAGE PKG. DWG. # 32 Ld PLCC N32.45x55 -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC64J-70 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC64SIZ-70 X28HC64SI-70 RR -40 to +85 28 Ld SOIC (300 mil) M28.3 X28HC64SZ-70 (Note 1) X28HC64S-70 RRZ 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3 X28HC64J-90* X28HC64J-90 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC64JI-90** X28HC64JI-90 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC64JIZ-90* (Note 1) X28HC64JI-90 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC64P-90 X28HC64P-90 RR 0 to +70 28 Ld PDIP E28.6 X28HC64PI-90 X28HC64PI-90 RR -40 to +85 28 Ld PDIP E28.6 X28HC64PIZ-90 (Notes 1, 2) X28HC64PI-90 RRZ -40 to +85 28 Ld PDIP (Pb-free) E28.6 X28HC64PZ-90 (Notes 1, 2) X28HC64P-90 RRZ 0 to +70 28 Ld PDIP (Pb-free) E28.6 X28HC64J-12* X28HC64J-12 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC64JI-12* X28HC64JI-12 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC64JIZ-12* (Note 1) X28HC64JI-12 Z RR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC64JZ-12* (Note 1) X28HC64J-12 RRZ 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC64P-12 X28HC64P-12 RR 0 to +70 28 Ld PDIP E28.6 X28HC64PI-12 X28HC64PI-12 RR -40 to +85 28 Ld PDIP E28.6 X28HC64PIZ-12 (Notes 1, 2) X28HC64PI-12 RRZ -40 to +85 28 Ld PDIP (Pb-free) E28.6 X28HC64PZ-12 (Notes 1, 2) X28HC64P-12 RRZ 0 to +70 28 Ld PDIP (Pb-free) E28.6 X28HC64S-12*, X28HC64S-12 RR 0 to +70 28 Ld SOIC (300 mil) M28.3 X28HC64SI-12* X28HC64SI-12 RR -40 to +85 28 Ld SOIC (300 mil) M28.3 X28HC64SIZ-12* (Note 1) X28HC64SI-12 RRZ -40 to +85 28 Ld SOIC (300 mil) (Pb-free) M28.3 X28HC64SZ-12 (Note 1) X28HC64S-12 RRZ 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3 ** 90 120 *Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications. ***Add "T2" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 2 FN8109.2 August 28, 2009 X28HC64 Pin Descriptions Device Operation Addresses (A0-A12) Read The Address inputs select an 8-bit memory location during a read or write operation. Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Write Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28HC64 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28HC64. TABLE 1. PIN NAMES SYMBOL DESCRIPTION A0-A12 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect Block Diagram 65,536-BIT X BUFFERS LATCHES AND DECODER EEPROM ARRAY A0-A12 ADDRESS INPUTS CE WE Page Write Operation The page write feature of the X28HC64 allows the entire memory to be written in 0.25 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28HC64 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A12) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. Write Operation Status Bits Y BUFFERS LATCHES AND DECODER OE Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 2ms. CONTROL LOGIC AND TIMING I/O BUFFERS AND LATCHES I/O0-I/O7 DATA INPUTS/OUTPUTS The X28HC64 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. I/O DP TB 5 4 3 2 1 0 RESERVED VCC TOGGLE BIT VSS DATA POLLING FIGURE 1. STATUS BIT ASSIGNMENT 3 FN8109.2 August 28, 2009 X28HC64 DATA Polling (I/O7) Toggle Bit (I/O6) The X28HC64 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC64, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. The X28HC64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. DATA Polling I/O7 WE Last Write CE OE VIH VOH HIGH Z I/O7 VOL A0-A12 An An An X28HC64 Ready An An An An FIGURE 2. DATA POLLING BUS SEQUENCE DATA Polling can effectively reduce the time for writing to the X28HC64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. WRITE DATA NO WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS IO7 COMPARE? NO YES READY FIGURE 3. DATA POLLING SOFTWARE FLOW 4 FN8109.2 August 28, 2009 X28HC64 The Toggle Bit I/O6 WE LAST WRITE CE OE VOH I/O6 HIGH Z * * VOL X28HC64 READY * BEGINNING AND ENDING STATE OF I/O6 WILL VARY. FIGURE 4. TOGGLE BIT BUS SEQUENCE Hardware Data Protection The X28HC64 provides two hardware features that protect nonvolatile data from inadvertent writes. LAST WRITE * Default VCC Sense--All write functions are inhibited when VCC is 3V typically. YES * Write Inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity. LOAD ACCUM FROM ADDR N Software Data Protection COMPARE ACCUM WITH ADDR N NO COMPARE OK? YES READY FIGURE 5. TOGGLE BIT SOFTWARE FLOW The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC64 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. 5 The X28HC64 offers a software controlled data protection feature. The X28HC64 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC64 can be automatically protected during powerup and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device, unless the reset command is issued. Once the software protection is enabled, the X28HC64 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Software Algorithm Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window, enabling the host to write from one to sixty-four bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. FN8109.2 August 28, 2009 X28HC64 Software Data Protection VCC (VCC) 0V DATA ADDR AAA 1555 55 0AAA A0 1555 WRITES OK tWC WRITE PROTECTED CE tBLC MAX WE BYTE OR PAGE FIGURE 6. TIMING SEQUENCE--BYTE OR PAGE WRITE Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used, the X28HC64 will automatically disable further writes unless another command is issued to deactivate it. If no further commands are issued the X28HC64 will be write protected during power-down and after any subsequent power-up. WRITE DATA AA TO ADDRESS 1555 WRITE DATA 55 TO ADDRESS 0AAA Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA A0 TO ADDRESS 1555 BYTE/PAGE LOAD ENABLED WRITE DATA XX TO ANY ADDRESS OPTIONAL BYTE/PAGE LOAD OPERATION WRITE LAST BYTE TO LAST ADDRESS AFTER TWC RE-ENTERS DATA PROTECTED STATE FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION 6 FN8109.2 August 28, 2009 X28HC64 Resetting Software Data Protection VCC DATA ADDR AAA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 tWC STANDARD OPERATING MODE CE WE FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE WRITE DATA AA TO ADDRESS 1555 WRITE DATA 55 TO ADDRESS 0AAA In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC64 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA 80 TO ADDRESS 1555 WRITE DATA AA ADDRESS 1555 WRITE DATA 55 TO ADDRESS 0AAA WRITE DATA 20 TO ADDRESS 1555 FIGURE 9. SOFTWARE SEQUENCE TO DEACTIVATE SOFTWARE 7 FN8109.2 August 28, 2009 X28HC64 System Considerations Because the X28HC64 is frequently used in large memory arrays, it is provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus, and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. 1.4 5.5VCC + 25C 1.0 + 125C 0.8 5.5VCC 1.2 - 55C 0.6 0.4 NORMALIZED (mA) NORMALIZED (mA) ICCRD 1.2 0.2 In addition, it is recommended that a 4.7F electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. ICCRD 1.4 Because the X28HC64 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. 1.0 5.0VCC 0.8 4.5VCC 0.6 0.4 0M 10M FREQUENCY (Hz) FIGURE 10. NORMALIZED ICC(RD) BY TEMPERATURE OVER FREQUENCY DATA PROTECTION 8 20M 0.2 0M 10M 20M FREQUENCY (Hz) FIGURE 11. NORMALIZED ICC(RD) @ 25% OVER THE VCC RANGE AND FREQUENCY FN8109.2 August 28, 2009 X28HC64 Absolute Maximum Ratings Thermal Information Temperature Under Bias X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +85C X28HC64I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on any Pin with Respect to Vss . . . . . . . . . . . . . . -1V to +7V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Recommended Operating Conditions Commercial Temperature Range. . . . . . . . . . . . . . . . . 0C to +70C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage Range X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V 10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. DC Electrical Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS TYP MIN (Note 3) MAX UNIT VCC Current (active) (TTL Inputs) ICC CE = OE = VIL, WE = VIH, All I/O's = open, address inputs = TTL levels @ f = 10 MHz 15 40 mA VCC Current (Standby) (TTL Inputs) ISB1 CE = VIH, OE = VIL All I/O's = open, other inputs = VIH 1 2 mA VCC Current (Standby) (CMOS Inputs) ISB2 CE = VCC - 0.3V, OE = GND, All I/O's = open, other inputs = VCC - 0.3V 100 200 A Input Leakage Current ILI VIN = VSS to VCC 10 A Output Leakage Current ILO VOUT = VSS to VCC, CE = VIH 10 A Input LOW Voltage (Note 4) VlL -1 0.8 V Input HIGH Voltage (Note 4) VIH 2 VCC + 1 V Output LOW Voltage VOL IOL = 5mA 0.4 V Output HIGH Voltage VOH IOH = -5mA 2.4 V NOTES: 3. Typical values are for TA = +25C and nominal supply voltage 4. VIL min. and VIH max. are for reference only and are not tested. Endurance and Data Retention Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER MIN Minimum Endurance Data Retention 9 MAX UNIT 100,000 Cycles 100 Years FN8109.2 August 28, 2009 X28HC64 Power-up Timing Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TYP (Note 3) UNIT Power-up to Read Operation (Note 5) tPUR 100 s Power-up to Write Operation (Note 5) tPUW 5 ms PARAMETER Capacitance TA = +25C, f = 1MHz, VCC = 5V PARAMETER SYMBOL TEST CONDITIONS MAX UNIT Input/output Capacitance (Note 5) CI/O VI/O = 0V 10 pF Input Capacitance (Note 5) CIN VIN = 0V 6 pF NOTE: 5. This parameter is periodically sampled and not 100% tested. Symbol Table TABLE 2. AC CONDITIONS OF TEST Input Pulse Levels 0V to 3V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V WAVEFORM TABLE 3. MODE SELECTION CE OE WE MODE I/O POWER L L H Read DOUT Active L H L Write DIN Active H X X Standby and write inhibit High Z Standby X L X Write inhibit -- -- X X H Write inhibit -- -- INPUTS OUTPUTS Must be steady Will be steady Ma y change from LO W to HIGH Will change from LO W to HIGH Ma y change from HIGH to LO W Will change from HIGH to LO W Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Equivalent AC Load Circuits 5V 1.92k OUTPUT 1.37k 30pF 10 FN8109.2 August 28, 2009 X28HC64 AC Electrical Specifications Read Cycle Limits Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER X28HC64-70 X28HC64-90 X28HC64-12 -55C TO +125C -55C TO +125C -55C TO +125C SYMBOL MIN MAX MIN MAX Read Cycle Time tRC 70 Chip Enable Access Time tCE 70 90 120 ns Address Access Time tAA 70 90 120 ns Output Enable Access Time tOE 35 40 50 ns CE LOW to Active Output (Note 6) tLZ 0 0 0 ns OE LOW to Active Output (Note 6) tOLZ 0 0 0 ns CE HIGH to High Z Output (Note 6) tHZ 30 30 30 ns OE HIGH to High Z Output (Note 6) tOHZ 30 30 30 ns Output Hold from Address Change tOH 90 0 0 MIN MAX UNIT 120 ns 0 ns NOTE: 6. tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tOLZ tOHZ tLZ DATA I/O HIGH Z tOH tHZ DATA VALID DATA VALID tAA 11 FN8109.2 August 28, 2009 X28HC64 Write Cycle Limits Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL MIN TYP (Note 3) MAX UNIT 2 5 ms Write Cycle Time (Note 7) tWC Address Setup Time tAS 0 ns Address Hold Time tAH 50 ns Write Setup Time tCS 0 ns Write Hold Time tCH 0 ns CE Pulse Width tCW 50 ns OE High Setup Time tOES 0 ns OE High Hold Time tOEH 0 ns WE Pulse Width tWP 50 ns WE HIGH Recovery (Note 8) tWPH 50 ns Data Valid (Note 8) tDV Data Setup tDS 50 ns Data Hold tDH 0 ns Delay to Next Write (Note 8) tDW 10 s Byte Load Cycle tBLC 0.15 1 100 s s NOTES: 7. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 8. tWPH and tDW are periodically sampled and not 100% tested. WE Controlled Write Cycle tWC ADDRESS tAS tAH tCS tCH CE OE tOES tOEH tWP WE tDV DATA IN DATA VALID tDS tDH HIGH Z DATA OUT 12 FN8109.2 August 28, 2009 X28HC64 CE Controlled Write Cycle tWC ADDRESS tAS tAH tCW CE tOES OE tOEH tCS tCH WE tDV DATA VALID DATA IN tDS tDH HIGH Z DATA OUT Page Write Cycle OE (NOTE 9) CE tWP tBLC WE tWPH Address (NOTE 10) Last Byte I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1 *For each successive write within the page write operation, A6-A12 should be the same or writes to an unknown address could occur. Byte n+2 tWC NOTES: 9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 13 FN8109.2 August 28, 2009 X28HC64 DATA Polling Timing Diagram (Note 11) ADDRESS An An An CE WE tOEH tOES OE tDW I/O7 DIN = X DOUT = X DOUT = X tWC Toggle Bit Timing Diagram (Note 11) CE WE tOES tOEH OE tDW I/O*6 HIGH Z * * tWC * I/O6 beginning and ending state will vary, depending upon actual tWC. NOTE: 11. Polling operations are by definition read cycles and are therefore subject to read cycle timings. 14 FN8109.2 August 28, 2009 X28HC64 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N32.45x55 (JEDEC MS-016AE ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) 0.050 (1.27) TP 0.025 (0.64) R 0.045 (1.14) ND CL C D2/E2 C L E1 E D2/E2 NE VIEW "A" A1 A D1 D 0.015 (0.38) MIN SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.050 (1.27) MIN 32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.125 0.140 3.18 3.55 - A1 0.060 0.095 1.53 2.41 - D 0.485 0.495 12.32 12.57 - D1 0.447 0.453 11.36 11.50 3 D2 0.188 0.223 4.78 5.66 4, 5 E 0.585 0.595 14.86 15.11 - E1 0.547 0.553 13.90 14.04 3 E2 0.238 0.273 6.05 6.93 4, 5 N 28 28 6 ND 7 7 7 NE 9 9 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN (0.12) M A S -B S D S 0.005 VIEW "A" TYP. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions. 7. ND denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. NE denotes the number of leads on the two long sides of the package. 15 FN8109.2 August 28, 2009 X28HC64 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N INDEX AREA 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 0.05 BSC 10.00 h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o 28 0o 10.65 - 0.394 N 0.419 1.27 BSC H NOTES: MAX A1 e MIN 28 - 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 16 FN8109.2 August 28, 2009 X28HC64 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-011-AB ISSUE B) N 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.380 1.565 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 35.1 39.7 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 28 28 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 9 Rev. 1 12/00 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN8109.2 August 28, 2009