© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 7
1Publication Order Number:
MC74HC4040A/D
MC74HC4040A
12-Stage Binary Ripple
Counter
High−Performance Silicon−Gate CMOS
The MC74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 12 master−slave flip−flops. The output of
each flip−flop feeds the next and the frequency at each output is half of
that of the preceding one. The state counter advances on the
negative−going edge of the Clock input. Reset is asynchronous and
active−high.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4040A for some designs.
Features
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance With JEDEC Standard No. 7A Requirements
•Chip Complexity: 398 FETs or 99.5 Equivalent Gates
•These Devices are Pb−Free, Halogen Free and are RoHS Compliant
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See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16 PDIP−16
N SUFFIX
CASE 648
1
16
1
16
1
16
MC74HC4040AN
AWLYYWWG
1
16
HC4040AG
AWLYWW
HC40
40A
ALYWG
G
1
16
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G= Pb−Free Package
1
16
74HC4040A
ALYWG
SOEIAJ−16
F SUFFIX
CASE 966
1
16
(Note: Microdot may be in either location)
MC74HC4040A
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2
Figure 1. Logic Diagram
Q1
9
Q2
7
Q3
6
Q4
5
Q5
3
Q6
2
Q7
4
Q8
13
Q9
12
Q10
14
Clock 10
Reset 11 Pin 16 = VCC
Pin 8 = GND
1516 14 13 12 11 10
21 34567
VCC
9
8
Q11 Q10 Q8 Q9 Reset Clock Q1
Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND
Figure 2. Pinout: 16−Lead Plastic Package
(Top View)
Q11
15
Q12
1
FUNCTION TABLE
Clock Reset Output State
X
L
L
H
No Charge
Advance to Next State
All Outputs Are Low
ORDERING INFORMATION
Device Package Shipping†
MC74HC4040ANG PDIP−16
(Pb−Free)
2000 Units / Box
MC74HC4040ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC4040ADR2G SOIC−16
(Pb−Free)
2500 Units / Reel
MC74HC4040ADTR2G TSSOP−16* 2500 Units / Reel
MC74HC4040AFG SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74HC4040AFELG SOEIAJ−16
(Pb−Free)
2000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74HC4040A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
Tstg Storage Temperature Range – 65 to + 150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package 260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature Range, All Package Types – 55 + 125 _C
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
600
500
400
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Condition
VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH Minimum High−Level Output Voltage Vin = VIH or VIL
|Iout| ≤ 20mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL |Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low−Level Output Voltage Vin = VIH or VIL
|Iout| ≤ 20mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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4
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol Unit
Guaranteed Limit
VCC
V
ConditionParameter
Symbol Unit
≤125°C≤85°C−55 to 25°C
VCC
V
ConditionParameter
Vin = VIH or VIL |Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0mA
6.0 4 40 160 mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
10
15
30
50
9.0
14
28
45
8.0
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q1*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
96
63
31
25
106
71
36
30
115
88
40
35
ns
tPHL Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
65
30
30
26
72
36
35
32
90
40
40
35
ns
tPLH,
tPHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
2.0
3.0
4.5
6.0
69
40
17
14
80
45
21
15
90
50
28
22
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
Cin Maximum Input Capacitance 10 10 10 pF
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n−1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n−1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n−1)] ns VCC = 6.0V: tP = [24.4 + 12 (n−1)] ns
CPD Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, VCC = 5.0 V
pF
31
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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5
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
−55 to 25°C≤85°C≤125°C
trec Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
30
20
5
4
40
25
8
6
50
30
12
9
ns
twMinimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
twMinimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tr, tfMaximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negative−edge triggering clock input. A high−to−low
transition on this input advances the state of the counter.
Reset (Pin 11)
Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.
OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Active−high outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING WAVEFORMS
tf
Clock
Q1
VCC
GND
90%
50%
10%
tr
tw
90%
50%
10%
tPHL
1/fMAX
tPLH
tTLH tTHL
Clock
VCC
GND
tw
trec
50%
Figure 3.
Reset
VCC
GND
50%
Any Q 50%
tPHL
Figure 4.
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6
SWITCHING WAVEFORMS (continued)
50%
Qn
VCC
GND
50%
Qn+1
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5. Figure 6. Test Circuit
tPLH tPHL
Figure 7. Expanded Logic Diagram
Clock 10 C
C
R
Reset 11
Q
Q
C
C
R
Q
Q
Q1
9
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q2
7
Q3
6
Q10
14
Q11
15
Q12
1
Q4 = Pin 5
Q5 = Pin 3
Q6 = Pin 2
Q7 = Pin 4
Q8 = Pin 13
Q9 = Pin 12
VCC = Pin 16
GND = Pin 8
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7
Clock
Reset
Q1
1 2 4 8 16 32 64 128 256 512 1024 2048 4096
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q10
Q11
Figure 8. Timing Diagram
Q9
Q12
APPLICATIONS INFORMATION
Time−Base Generator
A 60Hz sinewave obtained through a 100 K resistor
connected to a 120 Vac power line through a step down
transformer is applied to the input of the MC54/74HC14A,
Schmitt-trigger inverter. The HC14A squares−up the input
waveform and feeds the HC4040A. Selecting outputs Q5,
Q10, Q11, and Q12 causes a reset every 3600 clocks. The
HC20 decodes the counter outputs, produces a single
(narrow) output pulse, and resets the binary counter. The
resulting output frequency is 1.0 pulse/minute.
HC4040A
Figure 9. Time−Base Generator
Clock Q5
Q10
Q11
Q12
VCC
13
12
10
9
1
2
4
5
8
1/2
HC20
1/2
HC20
6
1.0 Pulse/Minute
Output
≥20pF
1.0M
120Vac
60Hz
NOTE: Ground MUST be isolated
by a transformer or
opto−isolator for safety
reasons.
MC74HC4040A
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8
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
MC74HC4040A
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9
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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10
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
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11
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74HC4040A/D
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