MC74HC4040A 12-Stage Binary Ripple Counter High-Performance Silicon-Gate CMOS The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative-going edge of the Clock input. Reset is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs. http://onsemi.com MARKING DIAGRAMS 16 1 16 SOIC-16 D SUFFIX CASE 751B 16 1 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates These Devices are Pb-Free, Halogen Free and are RoHS Compliant MC74HC4040AN AWLYYWWG 1 Features * * * * * * * * PDIP-16 N SUFFIX CASE 648 16 HC4040AG AWLYWW 1 16 HC40 40A ALYWG G TSSOP-16 DT SUFFIX CASE 948F 16 1 1 16 SOEIAJ-16 F SUFFIX CASE 966 16 1 74HC4040A ALYWG 1 A L, WL Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. (c) Semiconductor Components Industries, LLC, 2011 May, 2011 - Rev. 7 1 Publication Order Number: MC74HC4040A/D MC74HC4040A FUNCTION TABLE 9 7 6 5 Clock 3 2 10 4 13 12 14 15 1 Reset 11 Clock Reset Output State X L L H No Charge Advance to Next State All Outputs Are Low Q1 Q2 Q3 Q4 Q5 Q6 VCC Q11 Q10 Q8 Q9 Q7 16 15 14 13 12 Reset Clock 11 Q1 10 9 8 GND Q8 Q9 Q10 Q11 Q12 Pin 16 = VCC Pin 8 = GND Figure 1. Logic Diagram 1 2 3 4 5 6 7 Q12 Q6 Q5 Q7 Q4 Q3 Q2 Figure 2. Pinout: 16-Lead Plastic Package (Top View) ORDERING INFORMATION Package Shipping MC74HC4040ANG PDIP-16 (Pb-Free) 2000 Units / Box MC74HC4040ADG SOIC-16 (Pb-Free) 48 Units / Rail MC74HC4040ADR2G SOIC-16 (Pb-Free) 2500 Units / Reel MC74HC4040ADTR2G TSSOP-16* 2500 Units / Reel MC74HC4040AFG SOEIAJ-16 (Pb-Free) 50 Units / Rail MC74HC4040AFELG SOEIAJ-16 (Pb-Free) 2000 Units / Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 MC74HC4040A MAXIMUM RATINGS Symbol Parameter Value Unit - 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature Range - 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package Plastic DIP SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Supply Voltage (Referenced to GND) Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 0 1000 600 500 400 ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V -55 to 25C 85C 125C Unit VIH Minimum High-Level Input Voltage Vout = 0.1V or VCC -0.1V |Iout| 20mA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low-Level Input Voltage Vout = 0.1V or VCC - 0.1V |Iout| 20mA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Vin =VIH or VIL VOL Maximum Low-Level Output Voltage |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA Vin = VIH or VIL |Iout| 20mA http://onsemi.com 3 V MC74HC4040A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Vin = VIH or VIL |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA Guaranteed Limit VCC V -55 to 25C 85C 125C 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Unit Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0mA 6.0 4 40 160 mA AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) VCC V Guaranteed Limit -55 to 25C 85C 125C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 3.0 4.5 6.0 10 15 30 50 9.0 14 28 45 8.0 12 25 40 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q1* (Figures 1 and 4) 2.0 3.0 4.5 6.0 96 63 31 25 106 71 36 30 115 88 40 35 ns tPHL Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4) 2.0 3.0 4.5 6.0 65 30 30 26 72 36 35 32 90 40 40 35 ns tPLH, tPHL Maximum Propagation Delay, Qn to Qn+1 (Figures 3 and 4) 2.0 3.0 4.5 6.0 69 40 17 14 80 45 21 15 90 50 28 22 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns 10 10 10 pF Symbol Cin Parameter Maximum Input Capacitance * For TA = 25C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: VCC = 2.0 V: tP = [93.7 + 59.3 (n-1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n-1)] ns VCC = 6.0V: tP = [24.4 + 12 (n-1)] ns VCC = 3.0 V: tP = [61.5 + 34.4 (n-1)] ns Typical @ 25C, VCC = 5.0 V CPD 31 Power Dissipation Capacitance (Per Package)* * Used to determine the no-load dynamic power consumption: P D = CPD VCC http://onsemi.com 4 2f + ICC VCC . pF MC74HC4040A TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V -55 to 25C 85C 125C Unit trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 30 20 5 4 40 25 8 6 50 30 12 9 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 PIN DESCRIPTIONS INPUTS OUTPUTS Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1) Clock (Pin 10) Active-high outputs. Each Qn output divides the Clock input frequency by 2N. Negative-edge triggering clock input. A high-to-low transition on this input advances the state of the counter. Reset (Pin 11) Active-high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all Q outputs low. SWITCHING WAVEFORMS tf tr VCC 90% 50% 10% Clock Clock VCC trec GND tw tw 1/fMAX Reset tPHL tPLH Q1 50% 90% 50% 10% Any Q tTHL Figure 3. 50% Figure 4. http://onsemi.com 5 VCC 50% tPHL tTLH GND GND MC74HC4040A SWITCHING WAVEFORMS (continued) TEST POINT VCC Qn OUTPUT 50% DEVICE UNDER TEST GND tPLH Qn+1 tPHL CL* 50% *Includes all probe and jig capacitance Figure 5. Figure 6. Test Circuit Q1 Q2 9 Clock 10 Q10 6 Q11 14 Q12 15 1 C Q C Q C Q C Q C Q C C Q C Q C Q C Q C Q C R Reset Q3 7 R 11 Q4 = Pin 5 Q5 = Pin 3 Q6 = Pin 2 Q7 = Pin 4 Q8 = Pin 13 Q9 = Pin 12 Figure 7. Expanded Logic Diagram http://onsemi.com 6 VCC = Pin 16 GND = Pin 8 Q MC74HC4040A 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 Clock Reset Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Figure 8. Timing Diagram APPLICATIONS INFORMATION Time-Base Generator waveform and feeds the HC4040A. Selecting outputs Q5, Q10, Q11, and Q12 causes a reset every 3600 clocks. The HC20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute. A 60Hz sinewave obtained through a 100 K resistor connected to a 120 Vac power line through a step down transformer is applied to the input of the MC54/74HC14A, Schmitt-trigger inverter. The HC14A squares-up the input VCC 1.0M HC4040A Clock 120Vac 60Hz 13 Q5 12 20pF Q10 10 Q11 9 NOTE: Q12 Ground MUST be isolated by a transformer or opto-isolator for safety reasons. Figure 9. Time-Base Generator http://onsemi.com 7 1/2 HC20 8 1 2 4 5 1/2 HC20 6 1.0 Pulse/Minute Output MC74HC4040A PACKAGE DIMENSIONS PDIP-16 CASE 648-08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 8 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC74HC4040A PACKAGE DIMENSIONS SOIC-16 CASE 751B-05 ISSUE K -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 9 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74HC4040A PACKAGE DIMENSIONS TSSOP-16 CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 10 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC4040A PACKAGE DIMENSIONS SOEIAJ-16 CASE 966-01 ISSUE A 16 LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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