September 1993 2
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT652
FEATURES
•Multiplexed real-time and stored
data
•Independent register for A and B
buses
•Independent enables for A and B
buses
•3-state
•Output capability: Bus driver
•Low power consumption by CMOS
technology
•ICC category: MSI.
APPLICATIONS
•Bus interfaces.
DESCRIPTION
The 74HC/HCT652 are high-speed
SI-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with Jedec standard
no. 7A.
The 74HC/HCT652 consist of 8
non-inverting bus transceiver circuits
with 3-state outputs, D-type flip-flops
and central circuitry arranged for
multiplexed transmission of data
directly from the data bus or from the
internal storage registers. Data on the
“A” or “B” or both buses, will be stored
in the internal registers, at the
appropriate clock pins (CPAB or
CPBA) regardless of the select pins
(SAB and SBA) or output enable (OEAB
and OEBA) control pins. Depending
on the select inputs SAB and SBA data
can directly go from input to output
(real time mode) or data can be
controlled by the clock (storage
mode), this is when the output enable
pins this operating mode permits. The
output enable pins OEAB and OEBA
determine the operation mode of the
transceiver. When OEAB is LOW, no
data transmission from Anto Bnis
possible and when OEBA is HIGH,
there is no data transmission from Bn
to Anpossible. When SAB and SBA are
in the real time transfer mode, it is
also possible to store data without
using the internal D-type flip-flops by
simultaneously enabling OEAB and
OEBA. In this configuration each
output reinforces its input. Thus when
all other data sources to the two sets
of bus lines are at high-impedance,
each set of the bus lines will remain at
its last state. This type differs from the
HC/HCT646 in one extra
bus-management function. This is the
possibility to transfer stored “A data to
the “B” bus and transfer stored ”B”
data to the ”A” bus at the same time.
The examples at the application
information demonstrate all bus
management functions.
Schmitt-trigger action in the clock
inputs makes the circuit highly
tolerant to slower clock rise and fall
times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns; VCC = 4.5 V; CL= 50 pF.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz; CL= output load capacitance in pF;
fo= output frequency in MHz; VCC = supply voltage in V;
∑ (CL× VCC2× fo) = sum of the outputs
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPLH/tPZL propagation delay An/Bnto Bn/AnCL= 15 pF;
VCC =5 V 13 13 ns
propagation delay CPAB/CPBA to Bn/An18 20 ns
propagation delay SAB/SBA to Bn/An20 23 ns
tPHZ/tPZL 3-state output enable time OEAB/OEBA to Bn/An14 15 ns
tPHZ/tPLZ 3-state output disable time OEAB/OEBA to Bn/An12 13 ns
fmax maximum clock frequency 92 92 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per channel notes 1 and 2 26 28 pF