256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
1
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specifications without notices. 2009 NTC. All rights reserved.
Feature
z Fully synchronous; all signals registered on positive edge of
system clock
z Internal, pipelined operation; column address can be changed
every clock cycle
z Four internal banks for concurrent operation
z Programmable Burst Lengths: 1, 2, 4 ,8 or continuous
z Auto precharge, includes concurrent auto precharge
z Auto Refresh and Self Refresh Modes
z Optional Partial Array Self Refresh (PASR) and Temperature
Compensated Self Refresh (TCSR)
z Deep Power Down Mode (DPD)
z Selectable output drive strength (DS)
z LVTTL-compatible inputs and outputs
z V
DD/VDDQ= 1.70~1.95V
Table 1: Key Timing Parameters (CL=3)
Clock Rate (MHz) Access Time(ns) Speed
Grade CL=2 CL=3 CL=2 CL=3
-6 111 166 8 5
-75 111 133 8 5.4
Table 2: Configuration Addressing
Architecture 16M x 16 8M x 32
8M x 32
Reduced
page –size
option1
Number of banks 4 4 4
Bank address balls BA0, BA1 BA0, BA1 BA0, BA1
Row address balls A[12:0] A[11:0] A[12:0]
Column address balls A[8:0] A[8:0] A[7:0]
Refresh count 8k 4k 4k
Note: 1. For reduced page-size option, contact factory for availability.
Options Marking
z V
DD /VDDQ
-1.8V/1.8V M
z Configuration
-16Meg x 16 (4 Meg x 16 x 4 banks) 16M16
-8Meg x 32 (2 Meg x 32 x 4 banks) 8M32
z Row-size option
-JEDEC-standard addressing
-JEDEC reduced page-size addressing
z RoHS compliance and Halogen free
z Package
-54-ball VFBGA (x16: 8 x 9mm) G
-90-ball VFBGA (x32: 8 x13mm) K
z Timing – cycle time
-6.0ns @ CL=3 S1
-7.5ns @ CL=3 S2
z Operating temperature range
-Commercial (-25℃ to +85℃)
-Industrial (-40℃ to +85℃)
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
2
R1.3 Nanya Technology, Inc., reserves the right to change products or
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Description
The 256Mb Mobile SDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is
internally configured as a qual-bank DRAM.
The 256Mb chip is organized as 4Mbit x 4 banks x 16 I/O or 2Mbit x 4 banks x 32 I/O device. Each of the x16’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as4,096 rows by 512
columns by 32 bits. In the reduced page-size option, each of the x32’s 67,108,864-bit banks are organized as 8,192 rows by 256
columns by 32 bits. To achieve high-speed operation, our LPSDR SDRAM are quad-bank DRAM that operate at 1.8V, pipelined
architecture and include a synchronous interface. The pipelined architecture enables changing the column address on every clock
cycle to achieve a high-speed, fully random access. All signals are registered on the positive edge of the clock signal, CLK.
Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provides seamless
high-speed, random access operation.
LPSDR SDRAM, Read and Write access are burst oriented. The address bits registered coincident with the ACTIVE command to
select the row in the specific bank. And then the address bits registered with the READ or WRITE command to select the starting
column location in the bank for the burst access. The burst length can be programmed as 1, 2, 4, 8 or continuous. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of burst access.
LPSDR SDRAM with Auto Refresh mode, and the Power-down mode for power saving. And the Deep Power Down Mode can
achieve the maximum power reduction by removing the memory array power within Low Power DDR SDRAM. With this feature, the
system can cut off almost all DRAM power without adding the cost of a power switch and giving up month-board power-line layout
flexibility. Self Refresh mode with Temperature Compensated Self Refresh (TCSR) and Partial Array Self Refresh (PASR) options,
which allow users to achieve additional power saving. The TCSR and PASR options can be programmed via the extended mode
register. The two features may be combined to achieve even greater power saving.
All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
3
R1.3 Nanya Technology, Inc., reserves the right to change products or
specifications without notices. 2009 NTC. All rights reserved.
Ordering Information
Speed
Organization Part Number Package
tCK
(ns) Clock (MHz) Data Rate
(Mb/s/pin) CL
NT6SM16M16AG-S1 6.0 166 166 3
NT6SM16M16AG-S1I 6.0 166 166 3
NT6SM16M16AG-S2 7.5 133 133 3
16M x16
NT6SM16M16AG-S2I
54-Ball FBGA
7.5 133 133 3
NT6SM8M32AK-S1 6.0 166 166 3
NT6SM8M32AK-S1I 6.0 166 166 3
NT6SM8M32AK-S2 7.5 133 133 3
8M x32
NT6SM8M32AK-S2I
90-Ball FBGA
7.5 133 133 3
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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R1.3 Nanya Technology, Inc., reserves the right to change products or
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NANYA
Technology
ProductFamily
6S=LPSDRSDRAM
6D=LPDDRSDRAM
6V=LPDDR2‐S2SDRAM
6T=LPDDR2‐S4SDRAM
6X=LPSDR/DDRcomb
6Y=LPDDR2‐S2/S4comb
I
NANYA Mobile Component/Wafer Part Numbering Guide:
NT 6S M16M16
A
KS1
PackageCode()
G=54‐BallBGA(LPSDR,x16)
D=60‐BallBGA(LPDDR,x16)
K=90‐BallBGA(LPSDR,x32)
C=90‐BallBGA(LPDDR,x32)
A=79‐BallBGA(LPDDR2,x16)
I=134‐BallBGA(LPDDR2,x32)
Q=168‐BallPoP‐VFBGA(LPDDR2)
R=216‐BallPoP‐VFBGA(LPDDR2)
3=240‐BallPoP‐VFBGA(LPDDR2)
0=Wafer(KGD)
Speed
LPSDR
S1=166MHz@CL=3
S2=133MHz@CL=3
LPDDR
T1=5.0ns@CL=3
T2=5.4ns@CL=3
T3=6.0ns@CL=3
T4=7.5ns@CL=3
LPDDR2‐S2
T1=5.0ns@RL=3
T3=6.0ns@RL=3
LPDDR2‐S4
G0=1.8ns@RL=8
G1=2.5ns@RL=6
G2=3.0ns@RL=5
G3=3.7ns@RL=4
G4=5.0ns@RL=3
Note1:DDP–DualDiePackage
Note2:F=QuarticDiePackage
Note3:R=Reducedpagesize
DeviceVersion
A=1stversion
B=2ndversion
C=3rdversion
Organization(Depth,Width):M=Mono;T=DDP1;F=QDP2
256Mb=16M16=8M32=8M32R3
512Mb=32M16=16M32=16M32R
1Gb=64M16=32M32=32M32R
2Gb=256M8=128M16=64M32=64M32R
4Gb=256M16=128M32=64T64
8Gb=128T64=128F64
Grade
I=IndustrialGrade
N/A=CommercialGrade
Interface&Power(VDD&VDDQ)
M=LVCMOS(1.8V,1.8V)
Interface&Power(VDD1,VDD2,VDDQ)
H=HSUL_12(1.8V,1.35V,1.35V)
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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R1.3 Nanya Technology, Inc., reserves the right to change products or
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Pin Configuration – 54 balls BGA Package (x16)
< TOP View>
See the balls through the package
Package Dimensions (x16; 54 balls; 0.8mmx0.8mm Pitch; 8 x 9mm BGA Package)
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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R1.3 Nanya Technology, Inc., reserves the right to change products or
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Pin Configuration – 90 balls BGA Package (x32)
< TOP View>
See the balls through the package
Notes:
1. TheK2pinmustbeconnectedtoVSS,VSSQ,orleftfloating.
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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R1.3 Nanya Technology, Inc., reserves the right to change products or
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Package Dimensions (x32; 90 balls; 0.8mmx0.8mm Pitch; 8 x 13mm BGA Package)
Input / Output Functional Description
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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Symbol Type Function
CLK Input
Clock: Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the output
registers.
CKE Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge powerdown and SELF REFRESH operation (all banks idle), active
powerdown (row active in any bank), deep power-down (all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the device enters
power-down and self refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power.
/CS Input
Chip Select:/CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank
selection on systems with multiple banks. /CS is considered part of the command code.
/RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered.
DM
For x16: LDQM, UDQM
For x32: DQM0-DQM3
Input
Input Data Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) during a READ cycle.
For x16 devices, LDQM corresponds to the data on DQ0-DQ7, UDQM corresponds to the data on
DQ8-DQ15.
For x32 devices, DQM0 corresponds to the data on DQ0-DQ7, DQM1 corresponds to the data on
DQ8-DQ15, DQM2 corresponds to the data on DQ16-DQ23, and DQM3 corresponds to the data
on DQ24-DQ31.
DQM0-DQM3 (LDQM / UDQM if x16) are considered same state when referenced as DQM.
DQ
For x16: DQ0-DQ15
For x32: DQ0-DQ31
Input/output Data Bus: Bi-directional Input / Output data bus.
BA0, BA1 Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA0 and BA1 become when registering an ALL BANK
PRECHARGE (A10 HIGH).
A [12:0] Input
Address Inputs: A[12:0] are sampled during the ACTIVE command (row-address A[12:0]) and
READ/WRITE command [column-address A[8:0] (x32); column-address A[8:0] (x16); with A10
defining auto precharge] to select one location out of the memory array in the respective bank. A10
is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10
HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
NC Input No Connect: No internal electrical connection is present.
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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VDDQ Supply
DQ Power Supply: Isolated on the die for improved noise immunity.
VSSQ Supply
DQ Ground: Isolated on the die for improved noise immunity.
VDD Supply
Power Supply
VSS Supply
Ground
Functional Block Diagram – LPSDR 16Mx16
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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specifications without notices. 2009 NTC. All rights reserved.
Functional Block Diagram – LPSDR 8Mx32
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
11
R1.3 Nanya Technology, Inc., reserves the right to change products or
specifications without notices. 2009 NTC. All rights reserved.
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
12
R1.3 Nanya Technology, Inc., reserves the right to change products or
specifications without notices. 2009 NTC. All rights reserved.
Simplified State Diagram
Abbreviation Function Abbreviation Function
A
bbreviation Function
ACT Active LMR Load mode register PRE Precharge
READ Read (w/o Autoprecharge) CKEH Exit power-down PREALL Precharge all banks
READ A Read (w/ Autoprecharge) CKEL Enter power-down AREF Auto Refresh
WRITE Write (w/o Autoprecharge) DPD Enter Deep Power Dow
n
SREF Enter self refresh
WRITE A Write (w/ Autoprecharge) DPDX Exit Deep Power Down SREFX Exit self refresh
EMR Load extended mode regist
e
BST Burst Terminate SRR Status Register Read
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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Electrical Specifications
Absolute Maximum DC Ratings
Symbol Parameter Min Max Units
VDD / VDDQ V
DD / VDDQ supply voltage relative to Vss -0.5 +2.4 V
Vin Voltage on any pin relative to Vss -0.5 +2.4 V
Tstg Storage Temperature (plastic) -55 +150 °C
Notes:
1. Stressesgreaterthanthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.This
isastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedin
theoperationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsfor
extendedperiodsmayaffectreliability.
2. StorageTemperatureisthecasesurfacetemperatureonthecenter/topsideoftheDRAM.
3. VDDandVDDQmustbewithin300mVofeachotheratalltimes.VDDQmustnotexceedVDD.
Input / Output Capacitance (x16, x32)
Symbol Parameter Min Max Unit
CI1 Input capacitance: CLK 2.0 2.0 pF
CI2 Input capacitance: All other input-only balls 2.0 5.0 pF
CIO Input/output capacitance: DQs 2.5 6.0 pF
Notes:Thisparameterissampled.VDD/VDDQ=+1.8V,TA=25C;ballundertestbiasedat0.9V,f=1MHz.
DC Electrical Characteristics and Operating Conditions
V
DD / VDDQ = 1.70 ~ 1.95V
Symbol Parameter Min Max Unit Notes
VDD Supply voltage 1.7 1.95 V
VDDQ I/O Supply voltage 1.7 1.95 V
Address and Command inputs
VIH Input voltage high: Logic 1; All inputs 0.8 x VDDQ V
DDQ + 0.3 V 3
VIL Input voltage low : Logic 0 ; All inputs -0.3 +0.3 V 3
Data outputs
VOH Output high voltage 0.9 x VDDQ - V 4
VOL Output low voltage - 0.2 V 4
Leakage current
II
Input leakage current:
Any input 0 ≦ V
IN ≦ V
DD, (All other balls not
under test = 0V)
-1.0 1.0 uA
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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IOZ
Output leakage current:
DQs are disabled; 0 ≦ V
OUT ≦ V
DDQ
-1.5 1.5 uA
Operating temperature
TA Commercial -25 +85 °C
TA Industrial -40 +85 °C
Notes:
1. AllvoltagereferencedtoVss.
2. Afullinitializationsequenceisrequiredbeforeproperdeviceoperationisensured.
3. VIHovershoot:VIH(MAX)=VDDQ+2Vforapulsewidth≤3ns,andthepulsewidthcannotbegreaterthanonethirdofthe
cyclerate.VILundershoot:VIL(MIN)=–2Vforapulsewidth≤3ns.
4. IOUT=4mAforfulldrivestrength.Otherdrivestrengthsrequireappropriatescale..
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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IDD Specifications and Measurement Conditions
16Mx16 IDD Specifications; V DD/VDDQ = 1.70~1.95V
8Mx32 IDD Specifications; VDD/VDDQ = 1.70~1.95V
Speed Grade
Symbol Parameter/Condition S1
(-6) S2
(-75)
Unit Notes
IDD1 Operatin g current:
Active mode; Burst = 1; READ or WRITE; tRC=tRC(min) 45 42 mA 2,3,4
IDD2P Standby current:
Power-down mode; All banks idle; CKE is LOW 250 250 uA 5
IDD2N Standby current:
Non-power-down; All banks idle; CKE is HIGH 8 8 mA
IDD3P
Standby current:
Active mode; CKE is LOW; /CS is HIGH; All banks active; No
accesses in progress.
1.5 1.5 mA 3,4,6
IDD3N
Standby current:
Active mode; CKE is HIGH; /CS is HIGH; All banks active after
tRCD met; No accesses in progress.
12 12 mA 3,4,6
IDD4
Operating current:
Burst mode; READ or WRITE; All banks active, half DQs toggling
every cycle.
40 40 mA 2,3,4
IDD5 tRFC = 80ns 75 75 mA 2,3,4,6
IDD6
Auto Refresh current:
CKE=HIGH; /CS is HIGH. tRFC = 7.8125us 2 2 mA 2,3,4,7
IZZ Deep power-down current: 10 10 uA 5,8
Speed Grade
Symbol Parameter/Condition S1
(-6) S2
(-75)
Unit Notes
IDD1 Operatin g current:
Active mode; Burst = 1; READ or WRITE; tRC=tRC(min) 45 42 mA 2,3,4
IDD2P Standby current:
Power-down mode; All banks idle; CKE is LOW 260 260 uA 5
IDD2N Standby current:
Non-power-down; All banks idle; CKE is HIGH 5 5 mA
IDD3P
Standby current:
Active mode; CKE is LOW; /CS is HIGH; All banks active; No
accesses in progress.
1.5 1.5 mA 3,4,6
IDD3N
Standby current:
Active mode; CKE is HIGH; /CS is HIGH; All banks active after
tRCD met; No accesses in progress.
12 12 mA 3,4,6
IDD4
Operating current:
Burst mode; READ or WRITE; All banks active, half DQs toggling
every cycle.
45 45 mA 2,3,4
IDD5 tRFC = 80ns 75 75 mA 2,3,4,6
IDD6
Auto Refresh current:
CKE=HIGH; /CS is HIGH. tRFC = tREFI 2 2 mA 2,3,4,7
IZZ Deep power-down current: 10 10 uA 5,8
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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IDD7 Self-refresh current; VDD/VDDQ = 1.70~1.95V (x16 and x32)
Symbol Parameter / Condition Max Unit Notes
Full Array 350
1/2 Array 290
1/4 Array 270
85°C
1/8 Array 260
Full Array 220
1/2 Array 175
1/4 Array 150
IDD7
Self refresh current: CKE=LOW;
tCK=tCK(min); Address and control
inputs are stable; Data bus inputs are
stable.
45°C
1/8 Array 150
uA
Notes:
1. Afullinitializationsequenceisrequiredbeforeproperdeviceoperationisensured.
2. IDDisdependentonoutputloadingandcyclerates.Specifiedvaluesareobtainedwithminimumcycletimeandtheoutputs
open.
3. TheIDDcurrentwillincreaseordecreaseproportionallyaccordingtotheamountoffrequencyalterationforthetest
condition.
4. Addresstransitionsaverageonetransitioneverytwoclocks.
5. Measurementistaken500msafterenteringintothisoperatingmodetoallowtestermeasuringunitsettlingtime.
6. OtherinputsignalsareallowedtotransitionnomorethanonceeverytwoclocksandareotherwiseatvalidVIHorVILlevels.
7. CKEisHIGHduringREFRESHcommandperiodtRFCelseCKEisLOW.
8. Typicalvaluesat25°C(notamaximumvalue).
9. Enableson‐dierefreshandaddresscounters.
10. ValuesforIDD785°Cfullarrayandpartialarrayareguaranteedfortheentiretemperaturerange.IDD745°Cvaluesare
typicalvalues.
256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
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Electrical Characteristics and Recommended AC Operating Conditions
VDD/VDDQ = 1.70~1.95V
S1(-6) S2(-75)
Symbol Parameter Min Max Min Max
Unit Notes
Clock parameters
CL=3 - 5 - 5.4
tAC
Access time from CLK
(positive edge) CL=2 - 8 - 8
ns
CL=3 6 - 7.5 -
tCK Clock cycle time CL=2 9 - 9 -
ns 6
tCH CK high-level width 2.5 - 2.5 -
ns
tCL CK low-level width 2.5 - 2.5 -
ns
CKE input parameters
tCKH CKE hold time 1 - 1 - ns
tCKS CKE setup time 1.5 - 1.5 - ns
Data parameters
tDH Data-in hold time 1 - 1 - ns
tDS Data –in setup time 1.5 - 1.5 - ns
CL=3 - 5 - 5.4 ns
tHZ Data-out high-z time
CL=2 - 8 - 8 ns
7
tLZ Data-out Low-z time 1.0 - 1.0 - ns
tOH Data-out hold time (load) 2.5 - 2.5 - ns
tOHN Data-out hold time (no load) 1.8 - 1.8 - ns
Command / Address Input parameters
tAH Address hold time 1 - 1 - ns
tAS Address setup time 1.5 - 1.5 - ns
tCMH /CS, /RAS, /CAS, /WE, DQM hold time 0.5 - 0.5 - ns
tCMS /CS, /RAS, /CAS, /WE, DQM setup time 1.5 - 1.5 - ns
SDRAM core parameters
tRAS
ACTIVE to PRECHARGE command
42 120,000 45 120,000 ns
256Mb LPSDR SDRAM
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S1(-6) S2(-75)
Symbol Parameter Min Max Min Max
Unit Notes
tRC ACTIVE to ACTIVE command period 60 - 67.5 - ns
tRCD ACTIVE to READ or WRITE delay 18 - 19.2 - ns
tRP PRECHARGE command period 18 - 19.2 - ns
tRRD ACTIVE bank-a to ACTIVE bank-b
command 2 - 2 -
tCK
tWR Write recovery time 15 - 15 - ns 10
tT Transition time 0.3 1.2 0.3 1.2 ns 9
tXSR Exit SELF REFRESH to first valid
command 112.5 - 112.5 - ns 11
tREF Refresh period - 64 - 64 ms
tREFI Average periodic refresh interval (8,192
rows) - 7.8125 - 7.8125 us 8
tRFC Auto Refresh command period 97.5 - 97.5 - ns
Other parameters
tBDL Last data-in to burst STOP command 1 1
tCK 12
tCCD READ/WRITE command to
READ/WRITE command 1 1
tCK 12
tCDL Last data-in to new READ/WRITE
command 1 1
tCK 13
tCKED CKE to clock disable or power-down
entry mode 1 1
tCK 13
tDAL Data-in to ACTIVE command 5 5
tCK 14,16
tDPL Data-in to PRECHARGE command 2 2
tCK 15,16
tDQD DQM to input data delay 0 0
tCK 12
tDQM DQM to data mask during WRITEs 0 0
tCK 12
tDQZ DQM to data High-Z during READs 2 2
tCK 12
tDWD WRITE command to input data delay 0 0
tCK 12
tMRD LOAD MODE REGISTER command to
ACTIVE or REFRESH command 2 2
tCK
tPED CKE to clock enable or power-down exit
mode 1 1
tCK 13
tRDL Last data-in to PRECHARGE command 2 2
tCK 15,16
CL=3 3 3
tROH Data-out High-Z from
PRECHARGE command CL=2 2 2
tCK 12
256Mb LPSDR SDRAM
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Notes:
1. Afullinitializationsequenceisrequiredbeforeproperdeviceoperationisensured.
2. Theminimumspecificationsareusedonlytoindicatecycletimeatwhichproperoperationoverthefulltemperaturerange
(0°C≤TA≤+70°Cstandardtemperatureand–40°C≤TA≤+85°Cindustrialtemperature)isensured.
3. Inadditiontomeetingthetransitionratespecification,theclockandCKEmusttransitbetweenVIHandVIL(orbetween
VILandVIH)inamonotonicmanner.
4. Outputsmeasuredfor1.8Vat0.9Vwithequivalentload:
TestloadswithfullDQdriverstrength.PerformancewillvarywithactualsystemDQbuscapacitiveloading,termination,
andprogrammeddrivestrength.
5. ACtimingtestshaveVILandVihwithtimingreferencedtoVIH/2=crossoverpoint.Iftheinputtransitiontimeislonger
thantT(MAX),thenthetimingisreferencedatVIL(MAX)andVIH(MIN)andnolongerattheVIH/2crossoverpoint.
6. Theclockfrequencymustremainconstant(stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfor
theclockball)duringaccessorprechargestates(READ,WRITE,includingtWR,andPRECHARGEcommands).CKEmaybe
usedtoreducethedatarate.
7. tHZdefinesthetimeatwhichtheoutputachievestheopencircuitcondition,itisnotareferencetoVOHorVOL.Thelast
validdataelementwillmeettOHbeforegoingHigh‐Z.
8. The1GbMobileSDRAMrequires8,192AUTOREFRESHcyclesevery64ms(tREF).ProvidingadistributedAUTOREFRESH
commandevery7.8125μsmeetstherefreshrequirementandensuresthateachrowisrefreshed.Alternatively,8,192
AUTOREFRESHcommandscanbeissuedinaburstattheminimumcyclerate(tRFC),onceevery64ms.
9. ACcharacteristicsassumetT=1ns.
10. Autoprechargemodeonly.Theprechargetimingbudget(tRP)beginsatxnsfor‐75afterthefirstclockdelayandafterthe
lastWRITEisexecuted.Maynotexceedthelimitsetforprechargemode.
11. CLKmustbetoggledaminimumoftwotimesduringthisperiod.
12. RequiredclocksarespecifiedbyJEDECfunctionalityandarenotdependentonanytimingparameter.
13. TimingisspecifiedbytCKS.Clock(s)specifiedasareferenceonlyatminimumcyclerate.
14. TimingisspecifiedbytWRplustRP.Clock(s)specifiedasareferenceonlyatminimumcyclerate.
15. TimingisspecifiedbytWR.
16. BasedontCK(MIN),CL=3.
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Target Output Drive Characteristics (Full Strength)
Characteristics are specified under best and worst process variation/conditions
Min Max Min Max
0.00 0.00 0.00 0.00 0.00
0.10 2.8 18.53 –2.80 –18.53
0.20 5.6 26.8 –5.60 –26.80
0.30 8.4 32.8 –8.40 –32.80
0.40 11.2 37.05 –11.20 –37.05
0.50 14 40 –14.00 –40.00
0.60 16.8 42.5 –16.80 –42.50
0.70 19.6 44.57 –19.60 –44.57
0.80 22.4 46.5 –22.40 –46.50
0.85 23.8 47.48 –23.80 –47.48
0.90 23.8 48.5 –23.80 –48.50
0.95 23.8 49.4 –23.80 –49.40
1.00 23.8 50.05 –23.80 –50.05
1.10 23.8 51.35 –23.80 –51.35
1.20 23.8 52.65 –23.80 –52.65
1.30 23.8 53.95 –23.80 –53.95
1.40 23.8 55.25 –23.80 –55.25
1.50 23.8 56.55 –23.80 –56.55
1.60 23.8 57.85 –23.80 –57.85
1.70 23.8 59.15 –23.80 –59.15
1.80 – 60.45 – –60.45
1.90 – 61.75 – –61.75
Voltage (V) Pull-Down Current (mA) Pull-Up Current (mA)
Notes:
1. Tablevaluesbasedonnominalimpedanceof25Ω(full‐drive)atVDDQ/2.
2. Thefullvariationindrivecurrent,fromminimumtomaximum—duetoprocess,voltage,andtemperature—willliewithin
theouterboundinglinesoftheI‐Vcurves.
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Target Output Drive Characteristics (Three-Quarter Strength)
Characteristics are specified under best and worst process variation/conditions
Min Max Min Max
0.00 0.00 0.00 0.00 0.00
0.10 1.96 12.97 -1.96 -12.97
0.20 3.92 18.76 -3.92 -18.76
0.30 5.88 22.96 -5.88 -22.96
0.40 7.84 25.94 -7.84 -25.94
0.50 9.8 28 -9.8 -28
0.60 11.76 29.75 -11.76 -29.75
0.70 13.72 31.2 -13.72 -31.2
0.80 15.68 32.55 -15.68 -32.55
0.85 16.66 33.24 -16.66 -33.24
0.90 16.66 33.95 -16.66 -33.95
0.95 16.66 34.58 -16.66 -34.58
1.00 16.66 35.04 -16.66 -35.04
1.10 16.66 35.95 -16.66 -35.95
1.20 16.66 36.86 -16.66 -36.86
1.30 16.66 37.77 -16.66 -37.77
1.40 16.66 38.68 -16.66 -38.68
1.50 16.66 39.59 -16.66 -39.59
1.60 16.66 40.5 -16.66 -40.5
1.70 16.66 41.41 -16.66 -41.41
1.80 – 42.32 – -42.32
1.90 – 43.23 – -43.23
Voltage (V) Pull-Down Current (mA) Pull-Up Current (mA)
Notes:
1. Tablevaluesbasedonnominalimpedanceof37Ω(three‐quarterdrivestrength)atVDDQ/2.
2. Thefullvariationindrivecurrent,fromminimumtomaximum—duetoprocess,voltage,andtemperature—willliewithin
theouterboundinglinesoftheI‐Vcurves.
3. Contactfactoryforavailabilityofthree‐quarterdrivestrength.
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Target Output Drive Characteristics (One-half Strength)
Characteristics are specified under best and worst process variation/conditions
Min Max Min Max
0.00 0.00 0.00 0.00 0.00
0.10 1.27 8.42 –1.27 –8.42
0.20 2.55 12.3 –2.55 –12.30
0.30 3.82 14.95 –3.82 –14.95
0.40 5.09 16.84 –5.09 –16.84
0.50 6.36 18.2 –6.36 –18.20
0.60 7.64 19.3 –7.64 –19.30
0.70 8.91 20.3 –8.91 –20.30
0.80 10.16 21.2 –10.16 –21.20
0.85 10.8 21.6 –10.80 –21.60
0.90 10.8 22 –10.80 –22.00
0.95 10.8 22.45 –10.80 –22.45
1.00 10.8 22.73 –10.80 –22.73
1.10 10.8 23.21 –10.80 –23.21
1.20 10.8 23.67 –10.80 –23.67
1.30 10.8 24.14 –10.80 –24.14
1.40 10.8 24.61 –10.80 –24.61
1.50 10.8 25.08 –10.80 –25.08
1.60 10.8 25.54 –10.80 –25.54
1.70 10.8 26.01 –10.80 –26.01
1.80 – 26.48 – –26.48
1.90 – 26.95 – –26.95
Voltage (V) Pull-Down Current (mA) Pull-Up Current (mA)
Notes:
1. Tablevaluesbasedonnominalimpedanceof55Ω(half‐drivestrength)atVDDQ/2.
2. Thefullvariationindrivecurrent,fromminimumtomaximum—duetoprocess,voltage,andtemperature—willliewithin
theouterboundinglinesoftheI‐Vcurves.
3. TheI‐Vcurveforone‐quarterdrivestrengthisapproximately50percentofone‐halfdrivestrength.
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Basic Functionality
The 256Mb Mobile LPSDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 218,435,456 bits. It is
internally configured as a quad-bank DRAM.
The 256Mb chip is organized as 4Mbit x 4 banks x 16 I/O or 2Mbit x 4 banks x 32 I/O device. Each of the x16’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as 4,096 rows by 512
columns by 32 bits. In the reduced page-size option, each of the x32’s 67,108,864-bit banks are organized as 8,192 rows by 256
columns by 32 bits. To achieve high-speed operation, our LPSDR SDRAM are quad-bank DRAM that operate at 1.8V, pipelined
architecture and include a synchronous interface. The pipelined architecture enables changing the column address on every clock
cycle to achieve a high-speed, fully random access. All signals are registered on the positive edge of the clock signal, CLK.
Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provides seamless high-speed,
random access operation.
LPSDR SDRAM, Read and Write access are burst oriented. The address bits registered coincident with the ACTIVE command to
select the row in the specific bank. And then the address bits registered with the READ or WRITE command to select the starting
column location in the bank for the burst access. The burst length can be programmed as 1, 2, 4, 8 or continuous. An Auto Precharge
function may be enabled to provide a self-timed row precharge that is initiated at the end of burst access.
LPSDR SDRAM with Auto Refresh mode, and the Power-down mode for power saving. And the Deep Power Down Mode can
achieve the maximum power reduction by removing the memory array power within Low Power SDR SDRAM. With this feature, the
system can cut off almost all DRAM power without adding the cost of a power switch and giving up month-board power-line layout
flexibility. Self Refresh mode with Temperature Compensated Self Refresh (TCSR) and Partial Array Self Refresh (PASR) options,
which allow users to achieve additional power saving. The TCSR and PASR options can be programmed via the extended mode
register. The two features may be combined to achieve even greater power saving.
All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
Prior to normal operation, the LPSDR SDRAM must be initialized. The following sections provide detailed information covering
device initialization, register definition, command descriptions and device operation.
Initialization
LPSDR SDRAMs must be powered up and initialized in a predefined manner. Operations procedures other than those
specified may result in undefined operation. And any interruption to the device power, the initialization routine should be
followed to ensure proper functionality of the Mobile SDR SDRAM. After power is simultaneously applied to VDD and
VDDQ and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock
ball), the SDRAM requires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or NOP.
Starting at some point during this 100μs period and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
After the 100μs delay is satisfied by issuing at least one COMMAND INHIBIT or NOP command, a PRECHARGE
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command must be issued. All banks must then be precharged, which places the device in the all-banks-idle state. When
in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for mode register programming. Because the Mode registers powers up in an unknown state, it should
be loaded prior to issuing any operational command.
Initialization and Load Mode Register Sequence
Notes:
1.PRE=PRECHARGEcommand;LMR=LOADMODEREGISTERcommand;AR=AUTOREFRESHcommand.
2.NOPsorDESELECTsmustonlybeprovidedduringtRFCtime.
3.NOPsorDESELECTsmustonlybeprovidedduringtMRDtime.
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Register Definition
Mode Registers and Extended Mode Registers
The Mode Registers are used to define the specific mode of operation of the LPSDR SDRAM. This define includes the definition of a
burst length, a burst type, a CAS latency, operating mode, and write burst mode. The default value of the mode register is not defined,
therefore the mode register must be written after power up for proper operation. The Mode Register must be loaded when all banks
are idle and no bursts are progress, and the controller must wait the specific time tMRD before initiating any subsequent operation.
Violating either of these requirements will result in unspecified operation. The MRS contents won’t be changed until it is
reprogrammed, the device goes into Deep Power-Down, or the device loses power.
The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the state of address pins
A0~A12. The mode register contents can be changed using the same command and clock cycle requirements during normal
operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on the
functionality. Burst length is defined by M0~M2 with options of 1, 2, 4, 8 and continuous bit burst length. Burst address sequence type
is defined by M3 and CAS latency is defined by M4~M6. M7~M8 specify the operating mode. M9 specifies the write burst mode, and
M10~Mn must be set to low to ensure future compatibility. Mn+1~Mn+2 should be set to zero to prevent the extended mode register
from being programmed.
Standard Mode Register definition
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Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit M3 as above
figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. The burst
length is defined by bits M0-M2. Burst length options include 1, 2, 4, 8 or continuous locations are available for both the sequential
and the interleaved burst types. The continuous page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary BLs. Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that burst
take place within this block, meaning that the burst will wrap when a boundary is reached. The block is uniquely selected by A1–Ai
when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when BL = 8, where Ai is the most significant column address bit for a given
configuration. The remaining (least significant) address bits are used to specify the starting location within the block. The
programmed BL applies to both READ and WRITE bursts. Accesses within a given burst may be programmed to be either sequential
or interleaved via the standard mode register, and the burst type is selected via bit M3.
Burst Type and Burst Order
Burst Length Starting Column Address
(
A3, A2,A1,A0
)
Burst type = Sequential
A
3 = 0 Burst type = Interleaved
A3 = 1
0000 0,1 0,1
0001 1,0 1,0
0000 0,1,2,3 0,1,2,3
0001 1,2,3,0 1,0,3,2
0010 2,3,0,1 2,3,0,1
0011 3,0,1,2 3,2,1,0
0000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
0001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6
0010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5
0011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4
0100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
0101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2
0110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1
0111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
Continuous n = A0~An/9/8 (location 0-y) Cn, Cn+1, Cn+2, …, Cn-1, Cn… Not supported
2
4
8
CAS Latency (CL)
The CAS Latency, or READ latency is the delay, in clock cycles, between the registration of a Read command and the availability of
the first bit of output data. The latency can be set to two or three clocks. CAS Latency is defined by bit A6~A4 in the standard mode
register. If a READ command is registered at a clock edge n, and the CAS latency is m clocks, the first data element will be valid by
clock edge n+m. The DQ start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access
times are met, the data is valid by clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with
future versions may result.
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Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the BL programmed via M[2:0] applies to both READ and WRITE bursts; when M9 = 1, the programmed BL applies to
READ bursts, but write accesses are single location (nonburst) accesses.
Extended Mode Register definition
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include
output drive strength selection, Temperature Compensated Self Refresh (TCSR) and Partial Array Self Refresh (PASR). TCSR and
PASR are effective in Self Refresh mode only. The extended mode register is programmed via the LMR (LOAD MODE REGISTER)
command with BA0=0 and BA1=1, and the information won’t be changed until it is reprogrammed, the device goes into deep
power-down mode, or the device loses power. The EMRS must be loaded when all banks are idle and no bursts are in progress, and
the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation. Address bits A0-A2 specify PASR, A3-A4 the TCSR, A5-A6 the Drive Strength. A logic 0 should be
programmed to all the undefined addresses bits to ensure future compatibility.
Temperature Compensated Self Refresh (TCSR)
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On this version of the LPSDR SDRAM, the internal temperature sensor is implemented to adjust the self refresh oscillator
automatically base on the case temperature. To maintain backward compatibility, the programming of TCSR bits no effect on the
device. The self refresh oscillator will continue refresh at the optimal factory-programmed rate for the device temperature. The
address bits, A3 and A4 are ignore (don’t care) during EMRS programming.
Partial-Array Self Refresh (PASR)
For further power savings during self refresh, the PASR feature may allow the self refresh to be restricted to a variable portion of the
total array. They are full array (default: banks 0, 1, 2, and 3), 1/2 array (banks 0 and 1), 1/4 array (bank 0), and 1/8 array (bank 0 with
row address MSB=0). Data outside the defined area will be lost. Address bits A0 to A2 are used to set PASR. WRITE and READ
commands can still be issued to any bank selected during standard operation, but only the selected banks or segments of a bank in
PASR are refreshed during self refresh. It is important to note that data in unused banks or portions of banks is lost when PASR is
used.
Output Drive Strength
LPSDR SDRAM provides the option to control the drive strength of the output buffers for the smaller systems or point-to-point
environments. The value was selected based on the expected loading of the memory bus. Total four values provided, and they are 25
ohm, 37ohm, 55ohm, and 80ohm internal impedance. They are full, three-quarter, one-half, and one-quarter drive strengths,
respectively.
Extended Mode Register
Notes:1.On‐dietemperaturesensorisusedinplaceofTCSR.Settingthesebitswillhavenoeffect.
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LPSDR SDRAM Command Description and Operation
Command Truth Table
NANE (Function) Abbreviation /CS /RAS /CAS /WE DQM ADDR DQ NOTES
DESELECT DESELECT H X X X X X X
NO OPERATION NOP L H H H X X X
ACTIVE (select bank and active row) ACT L L H H X Bank/Row X 2
READ (select bank, column, and start read burst) READ L H L H L/H Bank/Col X 3
WRITE (select bank, column, and start write burst) WRITE L H L L L/H Bank/Col Valid 3
WRITE with AP (write burst with Auto Precharge) WRITEA L H L L Valid H Col 3
BURST TERMINATE or enter Deep Power-Down BST L H H L X X X 4,5
PRECHARGE (deactive row in selected bank) PRE L L H L X Code X 6
AUTO REFRESH or enter SELF REFRESH
REFA
/
REFS
LLLH X X X 7,8
LOAD MODE REGISTER LMR L L L L X Op-code X 9
Write enable/output enable X X X X L X Active 10
Write inhibit/output High-Z X X X X H X High-Z 10
Notes:
1. CKEisHIGHforallcommandsshownexceptSELFREFRESHandDEEPPOWER‐DOWN.
2. A[0:n]providerowaddress(whereAnisthemostsignificantaddressbit),BA0andBA1determinewhichbankismadeactive.
3. A[0:i]providecolumnaddress(wherei=themostsignificantcolumnaddressforagivendeviceconfiguration).A10HIGHenables
theautoprechargefeature(non‐persistent),whileA10LOWdisablestheautoprechargefeature.BA0andBA1determinewhichbank
isbeingreadfromorwrittento.
4. ThiscommandisBURSTTERMINATEwhenCKEisHIGHandDEEPPOWER‐DOWNwhenCKEisLOW.
5. ThepurposeoftheBURSTTERMINATEcommandistostopadataburst,thusthecommandcouldcoincidewithdataonthebus.
However,theDQcolumnreadsa“Don’tCare”statetoillustratethattheBURSTTERMINATEcommandcanoccurwhenthereisno
datapresent.
6. A10LOW:BA0,BA1determinethebankbeingprecharged.A10HIGH:allbanksprechargedandBA0,BA1are“Don’tCare.”.
7. ThiscommandisAUTOREFRESHisCKEisHigh,andSELFREFRESHifCKEisLow.
8. Internalrefreshcountercontrolsrowaddressing;allinputsandI/Osare“Don’tCare”exceptforCKE.
9. A[11:0]definetheop‐codewrittentothemoderegister.
10. ActivatesordeactivatestheDQduringWRITEs(zero‐clockdelay)andREADs(two‐clockdelay).
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CKE Truth Table
Previous
Cycle (n-1) Current
Cycle (n)
Power Down L L X Maintain Power Down
Self Refresh L L X Maintain Self Refresh
Clock suspend L L X Maintain clock suspend
Deep Power Down L L X Maintain Deep Power Down
Power Down L H NOP or DESELECT Exit Power Down 5
Self Refresh L H NOP or DESELECT Exit Self Refresh 6
Deep Power Down L H X Exit Deep Power Down 7
Clock suspend L H X Exit clock suspend
All Banks Idle H L NOP or DESELECT Precharge Power Down Entry
All Banks Idle H L BURST TERMINATE Deep Power Down Entry 8
All Banks Idle H L AUTO REFRESH Self Refresh Entry
Reading or Writing H L VALID Clock suspend entry
See the other Truth Tables H H
Notes
See the other Truth Tables
CKE
Current State Command (n)
/RAS, /CAS, /WE, /CS Ac tio n (n)
-Result
Notes:
1. CKEnisthelogicstateofCKEatclockedgen;CKEn‐1wasthestateofCKEatthepreviousclockedge.
2. CurrentstateisthestateoftheSDRAMimmediatelypriortoclockedgen.
3. COMMANDnisthecommandregisteredatclockedgen,andACTIONnisaresultofCOMMANDn.
4. Allstatesandsequencesnotshownareillegalorreserved.
5. Exitingpower‐downatclockedgenwillputthedeviceintheall‐banks‐idlestateintimeforclockedgen+1(providedthattCKSis
met).
6. Exitingselfrefreshatclockedgenwillputthedeviceintheall‐banks‐idlestateaftertXSRismet.COMMANDINHIBITorNOP
commandsshouldbeissuedonanyclockedgesoccurringduringthetXSRperiod.AminimumoftwoNOPcommandsmustbe
providedduringthetXSRperiod.
7. Afterexitingclocksuspendatclockedgen,thedevicewillresumeoperationandrecognizethenextcommandatclockedgen+1.
8. Deeppower‐downisapower‐savingfeatureofthisMobileSDRAMdevice.ThiscommandisBURSTTERMINATEwhenCKEisHIGH
andDEEPPOWER‐DOWNwhenCKEisLOW..
Current State Bank n Truth Table (command to Bank n)
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/CS /RAS /CAS /WE Description
H X X X DESELECT (NOP) Continue previous operation
L H H H NOP Continue previous operation
L L H H ACTIVE Select and Active row
L L L H AUTO REFRESH Auto refresh 7
L L L L LMR Load Mode register set 7
L L H L PRE Precharge 11
L H L H READ Select column & start read burst 10
L H L L WRITE Select column & start write burst 10
L L H L PRECHARGE Deactive row in bank or banks 8
L H L H READ Select column & start new read burst 10
L H L L WRITE Select column & start write burst 10
L L H L PRECHARGE Truncate read burst, start precharge 8
L H H L BURST TERMINTE Burst terminate 9,10
L H L H READ Select column & start read burst 10
L H L L WRITE Select column & start new write burst 10
L L H L PRECHARGE Truncate write burst, start precharge 8
L H H L BURST TERMINTE Truncate write burst, start precharge 9,10
Notes
Current
State Action (n)
-Result
Command
Any
Idle
Row Active
READ
(AP disable)
WRITE
(AP disable)
Notes:
1. TheTableapplieswhenbothCKEn‐1andCKEareHIGH,andaftertXSRortXPhasbeenmetifthepreviousstatewasselfrefreshor
PowerDown.
2. Thistableisbank‐specific,exceptwherenoted;i.e.,thecurrentstateisforaspecificbankandthecommandsshowncanbeissued
tothatbankwheninthatstate.Exceptionsarecoveredinthenotesbelow..
3. CurrentStateDefinitions:
Idle: Thebankhasbeenprecharged,andthetRPhasbeenmet.
RowActive: Arowinthebankhasbeenactivated,andtRCDhadbeenmet.Nodatabursts/accesses,registeraccessesin
progress
Read: AREADbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeen
terminated.
Write: AWRITEbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeen
terminated.
4. Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.COMMANDINHIBITorNOPcommands,or
supportedcommandstotheotherbank,shouldbeissuedonanyclockedgeoccurringduringthesestates.Supportedcommands
toanyotherbankaredeterminedbythatbank’scurrentstate.
Precharging: StartswithregistrationofaPRECHARGEcommand,endswhentRPismet.Thenthebankwillbeinidlestate.
RowActivating:StartswithregistrationofanAVTIVEcommand,endswhentRCDismetThenthebankwillbeinrowactive
state
Readw/APenabled:StartwithregistrationofaREADcommandwithautoprechargeenabled,endswhentRPhasbeenmet.
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Thenthebankwillbeintheidlestate.
Writew/APenabled:StartwithregistrationofaWRITEcommandwithautoprechargeenabled,endswhentRPhasbeenmet.
Thenthebankwillbeintheidlestate.
5. Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;DESELECTorNOPcommandsmustbeappliedoneach
positiveclockedgeduringthesestates.
Refreshing: StartswithregistrationofanAUTOREFRESHcommand,endswhentRFCismet.Thenallbankswillbeinidle
state.
AccessingModeRegister:StartswithregistrationofaLOADMODEREGISTERcommand,endswhentMRDismet.Thenallbanks
willbeinidlestate.
PrechargingAll:StartswithregistrationofaPRECHARGEALLcommand,endswhentRPismet.Thenallbankswillbeinidle
state
6. Allstatesandsequencesnotshownareillegalorreserved.
7. Notbank‐specific;requiresthatallbanksareidleandnoburstsareinprogress.
8. Mayormaynotbebankspecific;ifallbanksaretobeprecharged,eachmustbeinavalidstateforprecharging.
9. ThiscommandisBURSTTERMINATEwhenCKEisHIGHandDEEPPOWER‐DOWNwhenCKEisLOW.
10. READsorWRITEslistedintheCommand/ActioncolumnincludeREADsorWRITEswithautoprechargeenabledandREADsor
WRITEswithautoprechargedisabled.
11. DoesnotaffectthestateofthebankandactsasaNOPtothatbank.
Current State Bank n Truth Table (command to Bank m)
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/CS /RAS /CAS /WE Description
H X X X DESELECT (NOP) Continue previous operation
L H H H NOP Continue previous operation
Idle X X X X ANY Any command allowed to bank m
L L H H ACTIVE Select and activate row
L H L H READ Select column & start read burst 7
L H L L WRITE Select column & start write burst 7
L L H L PRECHARGE Precharge
L L H H ACTIVE Select and activate row
L H L H READ Select column & start read burst 7,10
L H L L WRITE Select column & start write burst 7,11
L L H L PRECHARGE Precharge 9
L L H H ACTIVE Select and activate row
L H L H READ Select column & start read burst 7,12
L H L L WRITE Select column & start write burst 7,13
L L H L PRECHARGE Precharge 9
L L H H ACTIVE Select and activate row
L H L H READ Select column & start read burst 7,8,14
L H L L WRITE Select column & start write burst 7,8,15
L L H L PRECHARGE Precharge 9
L L H H ACTIVE Select and activate row
L H L H READ Select column & start read burst 7,8,16
L H L L WRITE Select column & start write burst 7,8,17
L L H L PRECHARGE Precharge 9
Notes
Row Activating,
Active, or
Precharging
WRITE
(AP disable)
Current State Act io n (n)
-Result
Command
Any
READ
(AP disable)
Read
(AP enabled)
Write
(AP enabled)
Notes:
1. TheTableapplieswhenbothCKEn‐1andCKEareHIGH,andaftertXSRortXPhasbeenmetifthepreviousstatewasselfrefreshor
PowerDown.
2. Thistabledescribesalternatebankoperation,exceptwherenoted;i.e.,thecurrentstateisforbanknandthecommandsshown
canbeissuedtobankm(assumingthatbankmisinsuchastatethatthegivencommandissupported).Exceptionsarecoveredin
thenotesbelow.
3. CurrentStateDefinitions:
Idle: Thebankhasbeenprecharged,andthetRPhasbeenmet.
RowActive: Arowinthebankhasbeenactivated,andtRCDhadbeenmet.Nodatabursts/accesses,registeraccessesin
progress
Read: AREADbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeen
terminated.
Write: AWRITEbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeen
terminated.
Readw/AP:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentRPhasbeenmet.
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AftertRPismet,thebankwillbeintheidlestate.
Writew/AP:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentRPhasbeenmet.
AftertRPismet,thebankwillbeintheidlestate.
4. AUTOREFRESH,SELFREFRESH,andLOADMODEREGISTERcommandsmayonlybeissuedwhenallbanksareidle.
5. ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;itappliestothebankrepresentedbythecurrentstateonly.
6. Allstatesandsequencesnotshownareillegalorreserved.
7. READsorWRITEslistedintheCommandcolumnincludeREADsandWRITEswithAutoPrechargeenabledandREADsandWRITEs
withAutoPrechargedisabled.
8. Concurrentautoprecharge:Banknwillinitiatetheautoprechargecommandwhenitsbursthasbeeninterruptedbybankmburst.
9. Theburstinbankncontinuesasinitiated.
10. ForaREADwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterruptthe
READonbankn,CASlatency(CL)later.
11. ForaREADwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt
theREADonbanknwhenregistered.DQMshouldbeusedoneclockpriortotheWRITEcommandtopreventbuscontention.
12. ForaWRITEwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt
theWRITEonbanknwhenregistered,withthedata‐outappearingCLlater.ThelastvalidWRITEtobanknwillbedata‐in
registeredoneclockpriortotheREADtobankm.
13. ForaWRITEwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt
theWRITEonbanknwhenregistered.ThelastvalidWRITEtobanknwillbedata‐inregisteredoneclockpriortoREADtobankm.
14. ForaREADwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterruptthe
READonbankn,CLlater.ThePRECHARGEtobanknwillbeginwhentheREADtobankmisregistered.
15. ForaREADwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterruptthe
READonbanknwhenregistered.DQMshouldbeusedtwoclockspriortotheWRITEcommandtopreventbuscontention.The
PRECHARGEtobanknwillbeginwhentheWRITEtobankmisregistered.
16. ForaWRITEwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterruptthe
WRITEonbanknwhenregistered,withthedata‐outappearingCLlater.ThePRECHARGEtobanknwillbeginaftertWRismet,
wheretWRbeginswhentheREADtobankmisregistered.ThelastvalidWRITEbanknwillbedata‐inregisteredoneclockpriorto
theREADtobankm.
17. ForaWRITEwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterruptthe
WRITEonbanknwhenregistered.ThePRECHARGEtobanknwillbeginaftertWRismet,wheretWRbeginswhentheWRITEto
bankmisregistered.ThelastvalidWRITEtobanknwillbedataregisteredoneclocktotheWRITEtobankm.
COMMAND
NO OPERATION (NOP)
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The No operation (NOP) command is used to instruct the selected LPSDR SDRAM to perform a NOP. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
DESELECT
The Deselect function (/CS=HIGH) prevents new commands from being executed by the LPSDR SDRAM. Operations already in
progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via the address inputs and can only be issued when all banks are idle, no bursts are in progress. The
subsequent executable command can not be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1
inputs selects the bank, and the address provided selects the row. This row remains activate (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the
same bank.
READ
The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank;
the address provided selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto
precharge is selected, the row being accessed is precharged at the end of the READ burst; if auto precharge is not selected, the row
remains open for subsequent accesses. Read data appears on the DQ subject to the logic level on the DQM inputs two clocks earlier.
If a given DQM signal was registered HIGH, the corresponding DQ will be High-Z two clocks later; if the DQM signal was registered
LOW, the DQ will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The values on the BA0 and BA1 inputs select the bank;
the address provided selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto
precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row
remains open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data is written to memory; if the
DQM signal is registered HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank.
Otherwise BA0 and BA1 are treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank.
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AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function, but without requiring an explicit command.
This is accomplished by using A10 (A10=High), to enable Auto Precharge in conjunction with a specific READ or WRITE command.
A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of
the read or write burst. Auto precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE
command. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or continuous page bursts. The most recently registered
READ or WRITE command prior to the BURST TERMINATE command will be truncated.
REFRESH
LPSDR SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an
explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:
- AUTO REFRESH
AUTO REFRESH command is used during normal operation of the LPSDR SDRAM, and it’s non-persistent, so it must be issued
each time a refresh is required. The refresh addressing is generated by the internal refresh controller. The address bits become
“Don’t Care” during AUTO REFRESH. The LPSDR SDRAM requires AUTO REFRESH commands at an average periodic interval
of tREFI. To provide improved efficiency in scheduling and switching between tasks, some flexibility in the absolute interval is
provided. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later.
SELF REFRESH
SELF REFRESH command can be used to retain data in the LPSDR SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the LPSDR SDRAM retains data without external clocking. The LPSDR SDRAM device has a
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built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. Once the SELF REFRESH
command is registered, the external clock can be halted after one clock later. CKE must be held low to keep the device in Self
Refresh mode, and internal clock also disabled to save power. The minimum time that the device must remain in Self Refresh mode
is tRFC.
In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self Refresh and Partial Array Self
Refresh. During this mode, the device is refreshed as identified in the extended mode register. An internal temperature sensor will
adjust the refresh rate to optimize device power consumption while ensuring data integrity. During SELF REFRESH operation,
refresh intervals are scheduled internally and may vary. These refresh intervals may be different then the specified tREFI time. For
this reason, the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK must be stable prior to CKE going back
HIGH. When CKE is HIGH, the LPDDR SDRAM must have NOP commands issued for tXSR time.
Power-Down
Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred
to as active power-down. Power-down mode deactivates the input and output buffers, excluding CK, /CK and CKE. CKE keep Low to
maintain device in the power-down mode, and all other inputs signals are “Don’t Care”. The minimum power-down duration is
specified by tCKE. The device can not stay in this mode for longer than the refresh requirements of the device, without losing data.
The power-down state is synchronously existed when CKE is registered High (along with a NOP or DESELECT command). A valid
command can be issued after tXP after exist from power-down.
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Deep-Power-Down
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the LPSDR SDRAM
are stopped and all memory data, MRS and EMRS information is lost in this mode. The DPD command is the same as a BURST
TERMINATE command with CKE LOW. All banks must be in idle state with no activity on the data bus prior to entering the DPD
mode. While in this mode, CKE must be held in a constant Low state. To exit the DPD mode, CKE is taken high after the clock is
stable and NOP commands must be maintained for at least 200us. After 200us a complete re-initialization is required.
READs
READ burst operations are initiated with a READ command. The starting column and bank addresses are provided with the READ
command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being
accessed is precharged at the completion of the burst. During READ bursts, the valid data-out element from the starting column
address will be available following the CAS latency after the READ command. The first data-out element is edge aligned with the first
rising edge of DQS and the successive data-out elements are edge aligned to successive edges of DQS. DQS is driven by LPSDR
SDRAM along with output data. Upon completion of a read burst, assuming no other READ command has been initiated, the DQ will
go to High-Z.
READ to READ
Data from any READ burst can be truncated with a subsequent READ command, and data from a fixed-length READ burst can be
followed immediately by data from a READ command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that
is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element
is valid, where x = CL - 1. LPSDR SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated
with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed
random read accesses can be performed to the same bank, or each subsequent READ can be performed to a different bank.
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Consecutive Read Bu rsts (CL=2 and CL=3)
Notes:
1. EachREADcommandcanbetoanybank.DQMisLOW.
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Random Read Access (CL=2 and CL=3)
Notes:
1. EachREADcommandcanbetoanybank.DQMisLOW.
READ to WRITE
Data from any READ burst can be truncated with a subsequent WRITE command, and data from a fixed-length READ burst can be
followed immediately by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst can be initiated on
the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be
avoided. In a given system design, there is a possibility that the device driving the input data will go Low-Z before the SDRAM DQ go
to High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers) to suppress data out from the READ. After the WRITE command is
registered, the DQ will go to High-Z (or remain at High-Z), regardless of the state of the DQM signal, provided the DQM was active on
the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE.
For example, if DQM was LOW during T4 then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
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Read to Write (CL=3)
Notes:
1. CL=3.TheREADcommandcanbetoanybank,andtheWRITEcommandcanbetoanybank.Ifaburstofoneisused,DQMis
notrequired.
Read to Write with Extra Clock C ycle (CL=3)
Notes:
1. CL=3.TheREADcommandcanbetoanybank,andtheWRITEcommandcanbetoanybank.
READ to Precharge
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto
precharge was not activated). The PRECHARGE command should be issued x cycles before the clock edge at which the last desired
data element is valid, where x = CL - 1. The data element n + 3 is either the last of a burst of four or the last desired data element of a
longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Note that part of the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described
above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the
command. However, the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or continuous page
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bursts.
Read to Precharge (CL= 2 and CL=3)
Notes:
1. DQMisLOW.
READ BURST TERMINATE
Continuous-page READ bursts can be truncated with a BURST TERMINATE command and fixed-length READ bursts can be
truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE
command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. The data
element n + 3 is the last desired data element of a longer burst.
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Terminating a Read Bursts (CL=2 and CL=3)
Notes:1.DQMisLOW.
A
lternating Bank Read Accesses (CL=2, and BL=4)
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Read Continuous Page Burst (CL=2)
Read – DQM Operation (CL=2, and BL= 4)
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WRITEs
WRITE bursts are initiated with a WRITE command, the starting column and bank addresses are provided with the WRITE command
and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged
at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled.
WRITE Burst
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command. Subsequent data elements
are registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have
been initiated, the DQ will remain at High-Z and any additional input data will be ignored. A continuous page burst continues until
terminated; at the end of the page, it wraps to column 0 and continues.
Write Burst (BL=2)
Notes:
1. DQMisLOW.
WRITE to WRITE
Data for any WRITE burst can be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst can be
followed immediately by data for a WRITE command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to the new command. Data n + 1 is either the last
of a burst of two or the last desired data element of a longer burst. LPSDR SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, or each
subsequent WRITE can be performed to a different bank.
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WRITE-to-WRITE
Notes:
1. DQMisLOW.EachWRITEcommandmaybetoanybank.
Random WRITE Cycles
Notes:
1. DQMisLOW.EachWRITEcommandmaybetoanybank.
WRITE to READ
Data for any WRITE burst can be truncated with a subsequent READ command, and data for a fixed-length WRITE burst can be
followed immediately by a READ command. After the READ command is registered, data input is ignored and WRITEs will not be
executed. Data n + 1 is either the last of a burst of two or the last desired data element of a longer burst.
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Write-to-Read (CL=2)
Notes:
1. TheWritecommandcanbetoantbank,andtheREADcommandcanbetoanybank.DQMisLOW.
WRITE to PRECHARGE
Data for a fixed-length WRITE burst can be followed by or truncated with a PRECHARGE command to the same bank (provided that
auto precharge was not activated), and a continuous-page WRITE burst can be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is
registered. The auto precharge mode requires a tWR of at least one clock with time to complete, regardless of frequency.
In addition, when truncating a WRITE burst at high clock frequencies (tCK < 15ns), the DQM signal must be used to mask input data
for the clock edge prior to and the clock edge coincident with the PRECHARGE command. Data n + 1 is either the last of a burst of
two or the last desired data element of a longer burst. Following the PRECHARGE command, a subsequent command to the same
bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described
above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the
command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length bursts or continuous page
bursts.
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Write-to-Precharge
Notes:
1. Inthisexample,DQMcouldremainLOWiftheWRITEburstisafixedlengthoftwo.
Terminating a WRITE Burst
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input
data applied coincident with the BURST TERMINATE command is ignored. The last data written (provided that DQM is LOW at that
time) will be the input data applied one clock previous to the BURST TERMINATE command.
Terminating a WRITE Burst Notes:1.DQMisLOW.
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Alternating Bank Write Accesses (BL=4)
WRITE – Continuous Page Burst
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Notes:
1. tWRmustbesatisfiedpriortoissuingaPRECHARGEcommand.
2. Pageleftopen;notRP.
WRITE – DQM Operation (BL=4)
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a “1.” In this mode,
all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed BL. READ
commands access columns according to the programmed BL and sequence, just as in the normal mode of operation (M9 = 0).
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PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged. In case where only one bank is to be precharged (A10=LOW), inputs BA0, BA1 select
the bank. Otherwise BA0, BA1 are treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if
there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging.
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function described previously, but without requiring
an explicit command. This is accomplished by using A10 (A10=High), to enable Auto Precharge in conjunction with a specific READ
or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed
upon completion of the read or write burst. Auto precharge is non-persistent in that it is either enabled or disabled for each individual
READ or WRITE command. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The
“earliest valid stage” is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating
tRAS(min). The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts:
the access period and the precharge period. The access period starts with registration of the command and ends where the
precharge period (or tRP) begins. For READ with auto precharge, the precharge period is defined as if the same burst was executed
with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all the data in
the burst. For WRITE with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge
was disabled. In addition, during a WRITE with auto precharge, at least one clockis required during tWR time. During the prechare
period, the user must not issue another command to the same bank until tRP is satisfied. This device supports tRAS lock-out. In the
case of a single READ with auto-precharge or a single WRITE with auto-precharge issued at tRCD(min), the internal precharge will
be delayed until tRAS(min) has been satisfied.
Concurrent AUTO PRECHARGE
This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto
precharge is enabled, any command to another bank is supported, as long as that command does not interrupt the read or write data
transfer already in process. This feature enables the precharge to complete in the bank in which the READ or WRITE with auto
precharge was executed, without requiring an explicit PREACHRGE command, thus freeing the command bus for operations in other
banks. During the access period of a READ or a WRITE with auto precharge, only ACTIVE and PRECHARGE commands may be
applied to other banks. During the precharge period, ACTIVE, PRECHARGE, READ, and WRITE commands may be applied to other
banks. In either situation, all other related limitations apply.
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n following the
programmed CL. The precharge to bank n begins when the READ to bank m is registered.
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered.
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DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n begins when the
WRITE to bank m is registered.
READ with Auto Precharge Interrup t ed by a READ
Notes:
1. DQMisLOW.
READ with Auto Precharge Interrupted b y a WRITE
Notes:
1. DQMisHIGHatT2topreventDouta+1fromcontendingwithDindatT4.
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READ with Auto Precharge (BL=4 and CL=2)
READ without Auto Prech arge (BL=4 and CL=2)
Notes:1.TheREADburstisfollowedbyamanualPRECHARGE.
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.
Single READ with Auto Precharge (BL=1 and CL=2)
Single READ without Auto Precharge (BL=1 and CL=2)
Notes:1.TheREADburstisfollowedbyamanualPRECHARGE.
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WRITE with AUTO PRECHARGE
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with
the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is
registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered.
The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior to a WRITE to bank m.
WRITE with Auto Precharge In terru pted by a READ
Notes:1.DQMisLOW.
WRITE with Auto Precharge Interrupted by a WRITE
Notes:1.DQMisLOW.
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WRITE with Auto Precharge (BL= 4)
WRITE without Auto Precharge (BL=4)
Notes:1.TheWRITEburstisfollowedbyamanualPRECHARGE.
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Single WRITE wit Auto Precharge (BL=1)
Single WRITE without Auto Precharge (BL=1)
Notes:1.TheWRITEburstisfollowedbyamanualPRECHARGE.
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AUTO REFRESH
The AUTO REFRESH command is used during normal operation of the SDRAM to refresh the contents of the SDRAM array. This
command is non persistent, so it must be issued each time a refresh is required. All active banks must be precharged prior to issuing
an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP is met following the
PRECHARGE command. Addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command.
After the AUTO REFRESH command is initiated, it must not be interrupted by any executable command until tRFC has been met.
During tRFC time, COMMAND INHIBIT or NOP commands must be issued on each positive edge of the clock. The SDRAM requires
that every row be refreshed each tREF period. Providing a distributed AUTO REFRESH command—calculated by dividing the refresh
period (tREF) by the number of rows to be refreshed—meets the timing requirement and ensures that each row is refreshed.
Alternatively, a burst refresh can be employed after every tREF period—by issuing consecutive AUTO REFRESH commands for the
number of rows to be refreshed at the minimum cycle rate (tRFC)—to satisfy the refresh requirement.
Auto Refresh Mode
Notes:1.Back‐to‐BackAUTOREFRESHcommandsarenotrequired.
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SELF REFRESH
The self refresh mode can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in self refresh
mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become
“Don’t Care” with the exception of CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, enabling it to perform its own AUTO REFRESH
cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and remains in self refresh mode for an
indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a
signal cycling within timing constraints specified for the clock ball) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued according to the distributed refresh rate
(tREF/refresh row count) as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.
Self Refresh Mode
Notes:1.EachAUTOREFRESHcommandperformsaREFRESHcycle.Back‐to‐Backcommandsarenotrequired.
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Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If
power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers,
excluding CKE, for maximum power savings while in standby. The device cannot remain in the power-down state longer than the
refresh period (64ms) as no REFRESH operations are performed in this mode. The power-down state is exited by registering a NOP
or COMMAND INHIBIT with CKE HIGH at the desired clock edge (meeting tCKS).
Power-Down Mode
Notes:1.Violatingrefreshrequirementsduringpower‐downmayresultinalossofdata.
Deep-Power-Down
Deep power-down mode is a maximum power-saving feature achieved by shutting off the power to the entire device memory array.
Data on the memory array will not be retained after deep power-down mode is executed. Deep power-down mode is entered by
having all banks idle, with CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW.
CKE must be held LOW during deep power down.
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Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode,
the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the
next internal positive clock edge is suspended. Any command or data present on the input balls when an internal clock edge is
suspended will be ignored; any data present on the DQ balls remains driven; and burst counters are not incremented, as long as the
clock is suspended. Exit clock suspend mode by registering CKE HIGH; the internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend during WRITE Burst (BL=4 or greater)
Notes:1.DQMisLOW.
Clock Suspend during READ Burst (CL=2, BL=4 or greater)
Notes:1.DQMisLOW.
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Clock Suspend Mode (CL=3, and BL=2)
Notes:1.TheAutoPrechargeisdisable..
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Revision Log
Rev Date Modification
0.1 11/2010 Preliminary Release
0.2 1/2011 Update Idd values base on the DCTC characterization results
0.9 7/2011
Modify the errors
1.0 8/2011
For Web Release
1.1 10/2011
Errors correction
1.2 12/2011
P/N (x16) added
1.3 6/7/2012
R1.3 Typo
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®
Nanya Technology Corporation.
All rights reserved.
Printed in Taiwan, R.O.C., 2006
The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both.
NANYA and NANYA logo
Other company, product and service names may be trademarks or service marks of others.
NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants
performance of its semiconductor products and related software to the specifications applicable at the time of sale in
accordance with NTC’s standard warranty. Testing and other quality control techniques are utilize to the extent NTC
deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed,
except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe
property or environmental damage (“Critical Applications”).
NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE
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Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products
in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk
applications should be directed to NTC through a local sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should
be provided by customer to minimize the inherent or procedural hazards.NTC assumes no liability of applications
assistance, customer product design, software performance, or infringement of patents or services described herein. Nor
does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright,
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in which such semiconductor products or services might be or are used.
NANYA TECHNOLOGY CORPORATION
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669, FU HSING 3rd Rd., Kueishan,
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