SiI2020A SerDes Data Sheet March 2002 General Description Features Silicon Image's SiI2020A is a serializer/deserializer (SerDes) capable of transmitting and receiving data at 1.0625 and 2.125 gigabits-per-second (Gbps) targeting Fibre Channel applications. Designed for power, performance and price, the SiI 2020A SerDes makes use of a robust, low-power, low-cost, low-jitter, single-PLL CMOS design that comes in compact 64-pin, 14 mm MQFP and 10 mm TQFP packages. The SiI2020A supports selectable transmit and receive data rates for automatic speed negotiation and a narrow 10-bit SSTL_2-compatible interface for parallel data input/output. The innovative digital, fastlocking, single-PLL design enables high data reliability and ease-of-design while eliminating the need for external PLL capacitors and multiple PLLs. General * Fibre Channel-compliant * Multi-rate: 1.0625 Gbps and 2.125 Gbps The SiI2020A leverages much of the circuit innovation at the physical layer of Silicon Image's proprietary reduced overhead Multi-layer Serial Link (MSLTM) architecture, which was pioneered and proven with our market-leading PanelLink products. Silicon Image has shipped over 20 million units of PanelLink products for host systems and displays in the PC and the CE markets, notable for their noisy operating conditions. The MSL technology is a multilayered approach to providing cost-effective, multi-gigabit semiconductor solutions on a single chip for high-bandwidth applications. GND VDD_TX TX+ TX- VDD_TX VDD_TX GND VDD EQ RX_RATE RX+ VDD_RX RX- GND VDD_SSTL PLLBW SiI 2020A Pin Diagram 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 RXZ_CNT TX[0] 2 47 VREFR TX[1] 3 46 GND TX[2] 4 45 RX[0] VREFT 5 44 RX[1] TX[3] 6 43 TX[4] 7 TX[5] 8 TX[6] 9 42 RX[3] RX[4] 39 RX[5] TX[7] 11 TX[8] 12 37 38 27 RX_LOS COM_DET 28 29 30 31 32 GND 26 RBC[0] 25 RBC[1] 24 REF _RATE 23 VDD 22 GND 33 EN_CDET 16 REFCLK[0] NC REFCLK[1] 34 GND 15 VDDQ RX[8] GND EWRAP RX[7] 35 NC 36 14 VDDP 13 21 * compliant Separate transmit byte clock (TBC) for latching parallel input data Highly Reliable Serial Interface * Separately selectable Tx and Rx data rates * Single, digital PLL architecture * Very-low -jitter PLL: 2.7 ps (random jitter), 24.6 ps * * * * (deterministic jitter) Adjustable PLL filter bandwidth Variable pre-emphasis control Variable on-chip termination resistor Full ESD tolerance to 2kV * ICs for the PC and the CE markets (2-5 Gbps, over 20M units shipped) Robust design for "noisy" environments RX[6] TX[9] 20 Narrow parallel I/O Interface * 10-bit interface with DDR for 2.125 Gbps mode * SSTL_2 and High-Speed Parallel Interface (HSPI)- VDD_SSTL TX_RATE 19 Cost Effective * Standard CMOS technology * Compact 64-pin, 14 x 14mm MQFP package * Compact 64-pin, 10 x 10mm TQFP package RX[2] 40 10 18 I/O Power dissipation at 2.125 Gbps: 425mW (typical), 665mW (maximum) VDD_SSTL 41 RBC_SYNC 17 * Proven Technology * MSL-based technology proven with PanelLink TBC SiI2020A 64-pin MQFP/TQFP (Top View) Low Power * Single 2.5V supply for core circuits and high-speed RX[9] GND Figure 1. SiI2020A Pin Diagram Revision A - Data Sheet Subject to Change without Notice SiI-DS-0073-A SiI2020A Functional Block Diagram TX+ Serializer Loop-back TX[0:9] Sync TBC Input Latch TX_RATE REFCLK[0:1] PLL PLLBW TX- 1.0625/2.125Gbps Transmit signal Tx Rx RX+ RX- 1.0625/2.125 Gbps receive signal RX_LOS Sampler Deserializer EWRAP Frame Aligner EN_CDET COM_DET RBC_SYNC RX[0:9] Data Output RBC[0:1] RX_RATE REF_RATE Figure 2. Functional Block Diagram Single PLL: Only one PLL is used in the SiI 2020A SerDes. The internal PLL generates multiple phases from an external reference (REFCLK[0:1]) to not only transmit but also to receive serial data. For data reception, multiple phases are used to extract the incoming data and clock via oversampling. By eliminating one PLL, the SerDes consumes less power and is easier to design even in noisy environments. Hence, issues such as injection locking and interference between the transmission and reception clocks that are common to multiple-PLL architectures are eliminated. 10-bit Input Latch and Sync: SiI 2020A latches 10-bit parallel data on the falling edge of TBC in 1.0625 Gbps mode (TX_RATE = 0) and on both edges of TBC in 2.125 Gbps mode (TX_RATE = 1). After the data is captured using TBC, the data is synced with an internal clock generated from the PLL, which is generated from REFCLK[0:1]. Therefore, REFCLK and TBC must be synchronous with each other. Serializer: The 10-bit parallel data are converted to high-speed serial data by the serializer. TX[0] is transmitted first and TX[9] is transmitted last. Pre-emphasis can be optionally added to the output streams. The amount of pre-emphasis is controlled by an external resistor. R-Term: The termination value is controlled by the RXZ_CNT pin. When RXZ_CNT is high, the termination value is 75 Ohms and when RXZ_CNT is low, the termination value is 50 Ohms. Sampler: The sampler oversamples the input data by a multiple factor of the input rate. This oversampled information is used to determine the correct sampling point of the incoming data. Frame Aligner: If EN_CDET is high, the frame aligner finds the special characters ("0011111xxx"). If a special character is detected, the frame aligner aligns the incoming data so that the next comma or data character will start at RX[0]. The Comma character will be aligned at the rising edge of RBC1 in SiI2020A. If the first Comma is detected at the rising edge of RBC0, which is the misaligned case, the RBC1 will be stretched by a half clock , but never slivered, after the first Comma misalignment detection. During this realignment after the first Comma Revision A - Data Sheet Notice 2 Subject to Change without SiI-DS-0073-A SiI 2020A misalignment detection, some data (less than 3 bytes after the first misaligned Comma) and possibly the first misaligned Comma may be lost or misaligned. However, the second Comma character and the subsequent data will be output correctly and properly aligned. Loop-back: Loop-back mode can be used for diagnostic testing. When loop-back mode is enabled (EWRAP set high), the TX[0:9] input data are synced to the internal clock, realigned, and sent out as the RX[0:9] output. The TX+/- outputs are disabled and set to a DC logic state of 1; the RX+/- inputs are ignored. For normal operation, EWRAP should be low. Electrical Specifications Absolute Maximum Conditions Symbol Description Min Typ Max Units VDD Supply Voltage 2.5V -0.3 4.0 V VI Input Voltage -0.3 VDD+ 0.3 V TSTG Storage Temperature -65 150 C JA Thermal Resistance (Junction to Ambient) 33 C/W Notes: Permanent device damage may occur if absolute maximum conditions are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions below. Normal Operating Symbol VDD TA Conditions Description Supply Voltage Ambient Temperature (with power applied) Revision A - Data Sheet 3 Min 2.375 0 Typ 2.5 25 Max 2.625 70 Units V C Subject to Change without Notice SiI-DS-0073-A SiI 2020A DC Digital I/O Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter VREFT Input reference voltage VIH High level input Voltage VIL Low level input Voltage Min 1.15 Typ 1.25 Max 1.35 Units V VDD+0.30 V -0.3 VREFT-0.35V V VREFT+0.35 VIHPECL High level LVPECL input Voltage for REFCLK[0:1] VDD -0.4 VDD +0.4 V VILPECL Low level LVPECL input Voltage for REFCLK[0:1] -0.3 VDD-0.7 V VIHLVTTL High level LVTTL input Voltage for REFCLK[0:1] 2.0 VILLVTTL Low level LVTTL input Voltage for REFCLK[0:1] 0.80 VOH High level output voltage 1.9 VOL Low level output voltage GND DC Specifications Under normal operating conditions unless Symbol Parameter VSOUT75 TX+/TX- differential peak-topeak voltage swing. otherwise specified. Conditions Terminated by 75 Ohms V V V 0.6 V Min 1100 Typ 1500 Max 1800 Units mV 800 1100 1500 mV 2000 mV VSOUT50 TX+/TX- differential peak-topeak voltage swing. VIN RX+/RX- differential peak-topeak input sensitivity VDIH RX+/RX- differential Input common-mode voltage [3] VDD V VDOH TX+/TX- differential Output common-mode voltage [3] 1.2 V PCC Power dissipation Terminated by 50 Ohms. 200 CLOAD =5pF 2.125 Gbps rate TX+/- = 50ohms terminated 425[1] 665[2] mW [1] Sending/Receiving Random Pattern [2] Sending/Receiving Worst Case (maximum transitions) Pattern [3] Self biased Revision A - Data Sheet 4 Subject to Change without Notice SiI-DS-0073-A SiI 2020A REFCLK[0:1], TBC Parameters Under normal operating conditions unless otherwise specified. Symbol Parameter TREF_FREQ Nominal Frequency Min Typ 106.25 Max Units MHz ppm TREF_J REFCLK[0:1] frequency tolerance -100 100 TREF_DUTY REFCLK[0:1] duty cycle 40% 60% TRT_SKEW REFCLK to TBC skew (REFCLK and TBC must be synchronous with each other) -2 2 ns Max Units ps Transmit Function AC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter TTXS TX[0:9] setup time to the falling edge of TBC (TX_RATE=0) Min 1400 Typ TTXH TX[0:9] hold time from the falling edge of TBC (TX_RATE=0) 1400 ps TTCT TX[0:9], TBC transition time (TX_RATE=1) TTCV TX[0:9], TBC valid/stable time (TX_RATE=1) TRISE TX+/TX- rise time into 50 Ohms. Measured from 20% and 80% of full swing. 200 ps TFALL TX+/TX- fall time into 50 Ohms. 20% and 80% of full swing. Measured from 200 ps TTXLAT Latency from TX[0:9] parallel input to TX+/TX- serial output 18 ns TTRJ TX+/TX- output random RMS jitter[4] [5] 2.7 ps TTDJ TX+/TX- output deterministic jitter[6] 24.6 ps 1880 2820 ps ps [4] Random jitter was measured according to "Fibre Channel Specification X3.230-1994 FC-PH, Annex A, Section A.4.4 (oscilloscope method)". [5] Histogram for random jitter is shown in Figure 11. [6] Deterministic jitter was measured according to "Fibre Channel Specification X3.230-1994 FC-PH, Annex A, Section A.4.3" Conditions: All parameters are measure to 50% of full swing except where noted. Revision A - Data Sheet 5 Subject to Change without Notice SiI-DS-0073-A SiI 2020A Receiver Function AC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter TAXS Mode A, RX[0:9] setup time to the rising edge of RBC[0:1] Min 3 Typ Max Units ns TAXH Mode A, RX[0:9] hold time to the rising edge of RBC[0:1] 2.5 ns TARR Mode A, RBC[1] to RBC[0] rising edge skew 8.8 TBXS Mode B, RX[0:9] setup time to the rising edge of RBC[0] , or falling edge of RBC[1] 3 ns TBXH Mode B, RX[0:9] hold time to the rising edge of RBC[0] , or falling edge of RBC[1] 3 ns TCXS Mode C, RX[0:9] setup time to the rising edge of RBC[0:1] 1.4 ns TCXH Mode C, RX[0:9] hold time to the rising edge of RBC[0:1] 1.4 ns TCRR Mode C, RBC[1] to RBC[0] rising edge skew 4.5 TDCT Mode D, RX[0:9] transition time TDCV Mode D, RX[0:9] valid/stable time TRRISE, TRFALL Parallel output rise/fall. 80% of full swing. Measured from 20% and TRDUTY Duty cycle of RBC[0:1]. 80% of full swing. Measured from 20% and TRXLAT Latency from RX+/RX- serial input to RX[0:9] parallel output TJUMP RCLKP/RCLKN cycle to cycle period variation. Phase jump of synthesized clock. 9.9 ns 4.9 ns 1.5 ns 3 ns 2 40% ns 60% 32 ns 1/3 RX0+/- bit time Typ Max 200 Units s 200 2500 bits Conditions: 1. RBC[1] /RBC[0] and RX[0:9] are loaded by 10pF to ground for these measurements. 2. All parameters are measure to 50% of full swing except where noted. PLL Parameters Under normal operating conditions unless otherwise specified. Symbol Parameter TPLLLOCK PLL Locking time TBSYNC Bit sync time Revision A - Data Sheet 6 Min Subject to Change without Notice SiI-DS-0073-A SiI 2020A AC Timing Transmit Timing TBC T TXS TX[0:9] TT X H Data[0:9] Data[0:9] Figure 3. Input Timing for TX_RATE = 0 (1.0625 Gbps mode) TBC T TCT TX[0:9] TX+/- Data[0:9] T TXLAT 5 6 T TCV Data[0:9] 7 8 0 1 2 Data[0:9] 3 4 Figure 4. Input Timing for TX_RATE = 1 (2.125 Gbps mode) Revision A - Data Sheet 7 Subject to Change without Notice SiI-DS-0073-A SiI 2020A Receive Timing RBC[0] RBC[1] 53.125 MHz RX[0:9] 106.25 Mbps RBC_SYNC = 0 Mode A COM_DET RX_RATE = 0 (Serial Rate = 1.0625 Gbps) RBC[0] RBC[1] 106.25 MHz RX[0:9] 106.25 Mbps RBC_SYNC = 1 Mode B COM_DET RBC[0] RBC[1] 106.25 MHz RX[0:9] 212.5 Mbps RBC_SYNC = 0 RX_RATE = 1 (Serial Rate = 2.125 Gbps) Mode C COM_DET RBC[0] RBC[1] 106.25 MHz RX[0:9] 212.5 Mbps RBC_SYNC = 1 Mode D COM_DET Figure 5. Parallel Output Modes RX[0:9] Data[0:9] TRXLAT RX+/- 0 1 2 3 4 Figure 6. RX Latency RBC[0] RBC[1] TAXS TAXH TAXS TAXH RX[0:9] TARR Figure 7. Mode A Timing Diagram (RX_RATE=0, RBC_SYNC=0) Revision A - Data Sheet 8 Subject to Change without Notice SiI-DS-0073-A SiI 2020A RBC[0] RBC[1] T BXS TBXH T BXS T BXH RX[0:9] Figure 8. Mode B Timing Diagram (RX_RATE=0, RBC_SYNC=1) RBC[0] RBC[1] T CXS TCXH T CXS T CXH RX[0:9] T CRR Figure 9. Mode C Timing Diagram (RX_RATE=1, RBC_SYNC=0) RBC[0] RBC[1] TDCV TDCT RX[0:9] Figure 10. Mode D Timing Diagram (RX_RATE=1, RBC_SYNC=1) Revision A - Data Sheet 9 Subject to Change without Notice SiI-DS-0073-A SiI 2020A Figure 11. TX+/TX- Output Random Jitter with Equalization Disabled (TX+) - (TX-) Maximum output level Steady-state output level TX+/- terminated by 50 ohms, VDD = 2.5V, T A = 25 C The maximum output level (EQ pin = 0V) = V_sout50 in the DC specifications. Figure 12. Waveform for Pre-emphasis Values Revision A - Data Sheet 10 Subject to Change without Notice SiI 2020A SiI-DS-0073-A Pins Descriptions Functional Pins Pin Name TX[0], TX[1], TX[2], TX[3], TX[4], TX[5], TX[6], TX[7], TX[8], TX[9] RX[0], RX[1] RX[2], RX[3], RX[4], RX[5], RX[6], RX[7], RX[8], RX[9] TX+ TX- Pin # 2, 3, 4, 6, 7, 8, 9, 11, 12, 13 45, 44, 43, 41, 40, 39, 38, 36, 35, 34 62 61 Type In - SSTL2 Description TX[0:9] : Input pins for the 10-bit encoded data character that is to be transmitted serially over the TX+,TX- differential outputs. The first serial bit transmitted will be TX[0]. Out - SSTL2 RX[0:9] : 10-bit received data. Out Out RX+ RXREFCLK[1], REFCLK[0] 54 52 22 23 In In TBC 1 In - SSTL2 RBC[1] RBC[0] 30 31 Out - SSTL2 REF_RATE 29 In - LVTTL RX_RATE 55 In - LVTTL TX_RATE 14 In - LVTTL NC NC 16 17 TX+, TX- : Serialized, high speed. When parallel loop-back is disabled (EWRAP=0) these pins are active. When EWRAP=1, these pins are driven to logic 1. RX+, RX- : Serialized, high speed, differential inputs. These pins are active when loop-back is disabled (EWRAP=0). REFCLK[0:1] are differential reference clock inputs. This clock source is used by both transmit and receive sections of the device. When REF_RATE=1, these pins are used to input a 53.125 MHz clock signal. When REF_RATE=0, these pins input a 106.25 MHZ clock signal. These pins can be driven by a differential PECL clock source, or by a LVTTL single-ended clock on REFCLK[1] with REFCLK[0] connecting to GND via 0.1F capacitor. Transmit byte clock. This clock is used to capture the parallel input data (TX[0:9]). When TX_RATE = 0, the falling edge of TBC is used to capture the parallel data. When TX_RATE=1, data is captured between both the rising and falling edges of TBC resulting in a doubling of the data rate. Recovered clock output. These clock outputs are used by external devices to capture the RX[0:9] parallel data. The two clocks are 180 degrees out of phase with each other. The relationship between these clocks and the parallel data depends on the settings of RX_RATE, RBC_SYNC (see output timing figures for details). Sets the rate of the input reference clock. REF_RATE=0, the reference clock frequency is 106.25 MHz. REF_RATE=1 the reference clock frequency is 53.125 MHz. Receiver rate. The setting of this signal determines the rate at which the receiver operates. RX_RATE=0, the incoming serial stream is sampled at 1.0625 Gbps and the parallel data is driven out on the rising edge of RBC[1]. RX_RATE=1, the incoming serial stream is sampled at 2.125 Gbps and the parallel data is driven out on the rising edge of RBC[1] and RBC[0]. Transmitter rate. The setting of this signal determines the rate at which the transmitter operates. TX_RATE=0, the incoming parallel data stream is sampled on the falling edge of TBC. The data is then serialized and transmitted at a rate of 1.0625 Gbps. TX_RATE=1, the incoming serial stream is sampled between BOTH edges of TBC. The data is then serialized and transmitted at a rate of 2.125 Gbps. No connect No connect Revision A - Data Sheet InLVPECL/LVTTL InLVPECL/LVTTL - 11 Subject to Change without Notice SiI 2020A Functional Pins (continued) Pin Name Pin # Type RBC_SYNC 10 In - SSTL2 EQ 56 In- Analog EWRAP 19 In - LVTTL EN_CDET COM_DET 24 27 In - LVTTL Out - SSTL2 RX_LOS 26 Out - SSTL2 VREFT 5 In - Analog VREFR 47 Out - Analog PLLBW 49 In - LVTTL RXZ_CNT 48 In - LVTTL Revision A - Data Sheet SiI-DS-0073-A Description When RX_RATE = 0, Setting RBC_SYNC determines the frequency of RBC, RBC=53.125 MHz for RBC_SYNC = 0, and RBC= 106.25 MHz for RBC_SYNC= 1. When RX_RATE = 1, setting RBC_SYNC = 1 the receiver parallel output data and clocks transition simultaneously. Equalization control. This pin is used to input a voltage reference that sets the amount of equalization on the TX+/- outputs. To disable equalization this pin must be connected to a voltage below 600mV. As the voltage input on the pin is raised above 600mV the strength of the equalization is increased, reaching a maximum when the voltage input on EQ equals VDD. The following list shows the typical amount of preemphasis obtained for three settings of the EQ voltage reference. See Figure 12 for reference. Voltage input = 0V: Maximum output level = 100% Steady-state output level = 95% Voltage input = 1.25V: Maximum output level = 125% Steady-state output level = 65% Voltage input = 2.0V: Maximum output level = 155% Steady-state output level = 30% Enable parallel loop-back mode. When loop-back is enabled, parallel input data is looped to the parallel output data, the serializer/deserializer circuits are bypassed. EWRAP=0 loop-back mode is disabled. EWRAP=1, loop-back mode is enabled. Enable comma detection (activated with high). Comma detection signal. This signal is driven high when a comma character of positive disparity (0011111xxx) is detected on the high-speed serial input lines. Indicates whether there is any valid signal on RX+/- pins. If RX+/- > 200mVp-p, RX_LOS = 0 If RX+/- < 200mVp-p and RX+/- > 75mV, RX_LOS = undefined If RX+/- < 75mVp-p, RX_LOS = 1, RX[0:9] = B'1111111111' Voltage reference input, set by external voltage divider to 1.25V for SSTL2 input. Voltage reference output, externally outputs the voltage reference corresponding to 1.25V for SSTL2 output. PLL bandwidth control. PLLBW = 0, PLL bandwidth is reduced for filtering input reference clock jitter PLLBW = 1, bandwidth is normal If this pin is left unconnected, it will be internally pulled high (normal bandwidth) by default. RX input impedance matching control RXZ_CNT = 0, RX differential inputs are terminated by 50 ohms RXZ_CNT = 1, RX differential inputs are terminated by 75 ohms If this pin is left unconnected, it will be internally pulled down (terminated by 50 ohms) by default. 12 Subject to Change without Notice SiI 2020A Power & Ground Pins Pin Name Pin # VDD 28, 57 VDD_RX 53 Type Power Power VDD_TX 59, 60, 63 Power GND Ground VDD_SSTL VDDQ 15, 21, 25, 32, 33, 46, 51, 58, 64 37, 42, 50 20 VDDP 18 Power Revision A - Data Sheet Power Power SiI-DS-0073-A Description Power supply for digital logic circuits. High Speed Receiver Supply. For the best performance, this supply should be as noise free as possible. High Speed Transmiter Supply. For the best performance, this supply should be as noise free as possible. Power ground for digital logic circuits. Power supply for I/O pads (2.5V). Power supply for internal PLL interface (2.5V). For the best performance, this supply should be as noise free as possible. Power supply for PLL (2.5V). For the best performance, this supply should be as noise free as possible. 13 Subject to Change without Notice SiI-DS-0073-A SiI 2020A Package Dimensions 64-pin MQPF Package Dimensions Lead Length 1.60 mm Lead Width 0.35 mm 64-pin Plastic MQFP Package Height 2.35mm max. SiI2020ACM64 LNNNNN.NLLL XXYY X.XX Footprint 17.20 mm Device # Lot # Date Code SiI Rev. # Body Size 14.00 mm Lead Pitch 0.80 mm Body Thickness 2.00 mm Clearance 0.25mm max. Body Size 14.00 mm Footprint 17.20mm JEDEC code MS -022 BB Figure 13. SiI2020ACM64 Package Diagram Revision A - Data Sheet 14 Subject to Change without Notice SiI-DS-0073-A SiI 2020A Package Dimensions 64-pin TQPF Package Dimensions Lead Length 1.00 mm Lead Width 0.22 mm 64-pin Plastic TQFP Package Height 1.15 mm max. SiI2020ACT64 LNNNNN.NLLL XXYY X.XX Footprint 12.00 mm Device # Lot # Date Code SiI Rev. # Body Size 10.00 mm Lead Pitch 0.50 mm Body Thickness 1.00 mm Clearance 0.15 mm max. Body Size 10.00 mm Footprint 12.00 mm JEDEC code MS -026 ACD Figure 14. SiI2020ACT64 Package Diagram Revision A - Data Sheet 15 Subject to Change without Notice SiI-DS-0073-A SiI 2020A Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce; transform to any other format, or send/transmit any part of this documentation without the express written permission of Silicon Image, Inc. Trademark Acknowledgment Silicon Image, the Silicon Image logo, MSL and PanelLink are trademarks or registered trademarks of Silicon Image, Inc. All other trademarks are the property of their respective holders. Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Part Ordering Number: SiI2020ACM64 (64 pin MQFP) SiI2020ACT64 (64 pin TQFP) Revision History: Revision A Comment Final Data Sheet Date 03/08/02 (c) 2002 Silicon Image, Inc. 03/08 SiI-DS-0073-A Silicon Image, Inc. 1060 E. Arques Ave Sunnyvale, CA 94085 USA Tel: (408) 616-4000, 1-888-PanelLink Fax: (408) 830-9530 E-mail: salessupport@siimage.com Web: www.siimage.com www.panellink.com Revision A - Data Sheet 16 Subject to Change without Notice