Preliminary ABPX1130
Advanced Programmable Clock
30332 Esperanza, Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 1
FEATURES
• Advanced programmable PLL design
• Very low Jitter and Phase Noise (< 40ps Pk-Pk typical)
• Output frequency up to 375MHz CMOS.
• Supports differential CMOS output to produce PECL, LVDS
inputs.
• Crystal inputs:
o Fundamental crystal: 10MHz-30MHz
o 3RD overtone crystal: Up to 75MHz
o Reference input: Up to 200MHz
• Accepts <1.0V reference signal input voltage
• One programmable I/O pin can be configured as
Output Enable (OE), or Frequency Selection input
(FSEL), or Reference clock.
• Single 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
• Available in 8-pin MSOP/SOIC, 6-pin SOT Green/RoHS compliant
packages.
PIN CONFIGURATION
DESCRIPTION
The ABPX1130 is a low-cost general purpose frequency synthesizer and a member of Abracon’s Advanced
Programmable Clock family. Abracon’s ABPX1130 product family can generate any output frequency up to 375
MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of up to 75Mhz. The
ABPX1130 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs.
BLOCK DIAGRAM
1
2
3
4 5
6
7
8
XIN/FIN
GND
CLK0
XOUT
DNC
VDD
1
2
3
4 5
6
7
8
CLK1
CLK2, OE, FSEL
SOP-8
MSOP-8
ABPX1130
Phase
Detecto
r
Charge
Pump Loop
Filte
r
VCO
Xtal
OSC
XIN/
FIN
XOUT
P
-
counte
r
( 5-
bit)
M
-
counte
r
( 6 -
bit)
R
- counte
r
CLK[0:1]
CLK2
F
Ref
OE
FSEL
F
VCO =
F
Ref. *
(
2 * M /R
)
FOut = FVCO / (2 * P)
CLoad
Programming
Logic
Programmable Function /1, /2
Preliminary ABPX1130
Advanced Programmable Clock
30332 Esperanza, Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 2
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ]
Output Frequency Output Drive
Strength Crystal
Load Programmable
Input/Output (pin #7)
# of
Register
Banks
Charge-Pump
Current
Fout = FIN * M / (R * P)
where M= 6 bit
R= 1
P= 5 bit
1. CLK[0:1]= VCO / 2 * P
2. CLK[2]= FIN or FIN/2
Std: 10mA
(default)
High: 24mA
+/- 200ppm
tuning.
One output pin can be
configured as
1. CLK2 = FIN or FIN/2
2. FSEL - input
3. OE - input
2
4 levels of pump
current setting
PIN DESCRIPTION
Pin #
Name (M)SOP-8 Type Description
XIN/FIN 1 I Crystal or Reference input pin
GND 2 P GND connection
CLK[0:1] 3,4 O Programmable Clock Output [note:CLK0=~CLK1]
VDD 5 P VDD connection
DNC 6 - Do No Connect
CLK2, OE, FSEL 7 B
This programmable I/O pin can be configured as CLK2
(FIN or FIN/2) output, or OE input, or Frequency
Selection (FSEL) input pin. This pin has an internal 60KΩ
pull up resistor.
State OE FSEL
0 Tristate
CLK[0:1]
Select Bank ’0’
ROM
1 (default) Normal
mode
Select Bank ‘1’
ROM
XOUT 8 O Crystal output pin
Preliminary ABPX1130
Advanced Programmable Clock
30332 Esperanza, Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 3
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS SYMBOL MIN. MAX. UNITS
Supply Voltage Range VDD -0.5 4.6 V
Input Voltage Range VI -0.5 VDD+0.5 V
Output Voltage Range VO -0.5 VDD+0.5 V
Data Retention @ 85º C 10 Years
Soldering Temperature 260 °C
Storage Temperature TS -65 150 °C
Ambient Operating Temperature -40 +85 °C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
AC SPECIFICATIONS
PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS
Fundamental Crystal 10 30 MHz
Crystal Input Frequency
3rd Overtone Crystal 75 MHz
Settling Time At power-up (after VDD increases over
1.62V) 10 ms
VDD Sensitivity Frequency vs. VDD+/-10% -2 2 ppm
15pF Load, 10/90%VDD, Standard drive 2.5 3.5 ns
Output Rise Time
15pF Load, 10/90%VDD, High drive 1.0 1.5 ns
15pF Load, 90/10%VDD, Standard drive 2.5 3.5 ns
Output Fall Time
15pF Load, 90/10%VDD, High drive 1.0 1.5 ns
Duty Cycle At VDD/2 45 50 55 %
Max. output skew between
same frequency clocks
Equal loading (15 pF). Equal frequency
& drive strength 500 ps
Period Jitter, peak-to-peak*
(measured from 10,000
samples)
With capacitive decoupling between VDD
and GND. Operating only one output. 40 ps
* Note: Jitter performance depends on the programming parameters.
Preliminary ABPX1130
Advanced Programmable Clock
30332 Esperanza, Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 4
DC SPECIFICATIONS
PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS
Supply Current, Dynamic,
with Loaded Outputs IDD At 10MHz, load=15pF 15 mA
Operating Voltage VDD 2.25 3.63 V
Output Low Voltage VOL I
OL = +4mA (Standard drive) 0.4 V
Output High Voltage VOH I
OH = -4mA (Standard drive) VDD – 0.4 V
IOSD VOL = 0.4V, VOH = 2.4V (Standard
drive) 10 mA
Output Current
IOHD V
OL = 0.4V, VOH = 2.4V (High Drive) 24 mA
Short-circuit Current IS ±50 mA
CRYSTAL SPECIFICATIONS
PARAMETERS SYMBOL MIN. TYP. MAX. UNITS
Fundamental Crystal Resonator Frequency FXIN 10 30 MHz
3rd Overtone Crystal Resonator Frequency FXIN 75 MHz
Crystal Loading Rating
(The IC can be programmed for any value in this range.) CL (xtal) 5 20 pF
Maximum Sustainable Drive Level 500 µW
Operating Drive Level 100 µW
Crystal Shunt Capacitance C0 6 pF
Effective Series Resistance, Fundamental, 10-30MHz RS 30
Ω
Effective Series Resistance, 3rd Overtone, 30-50MHz
[CO< 4pF, CL=5pF/8pF] ESR 100/70
Ω
Effective Series Resistance, 3rd Overtone, 50-65MHz,
[CO< 4pF, CL=5pF/8pF] ESR 60/40
Ω
Effective Series Resistance, 3rd Overtone, 65-75MHz
[CO< 4pF, CL=5pF/8pF ESR 45/30
Ω
Note: A detailed crystal specification document is also available for this part
Preliminary ABPX1130
Advanced Programmable Clock
30332 Esperanza, Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 5
Figure 1 below describes how to terminate the differential CMOS outputs of Abracon’s ABPX1130 Programmable QTC clock for
use with PECL or LVDS inputs.
The unique feature of differential CMOS outputs allows great flexibility for board designers. By standardizing on one termination
scheme you can use the ABPX1130 for all your LVDS and PECL clock requirements up to 375MHz.
50Ω line
50Ω line R3
R1
R1
R2
R2
R3
CMOS Output
Complementary
CMOS Output
0V
3.3V
1.59V
2.35V
+3.3V
+3.3V
Complementary
Input
Input
Component selection
For LVDS input
R1 = 360Ω
R2 = 82Ω
R3 = 130Ω
For PECL input
R1 = 130Ω
R2 = 82Ω
R3 = 130Ω
Notes:
Place R1 as close to the CMOS outputs as
possible.
Place R2 and R3 as close to the PECL/LVDS
inputs as possible.
PECL
1.10V
1.40V
LVDS
Figure 1
The above layout allows the ABPX1130 to drive either a PECL or LVDS input by simply changing the value of R1.
Preliminary ABPX1130
Advanced Programmable Clock
30332 Esperanza, Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 6
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
MSOP 8L
SOP 8L
Dimension in MM
Symbol Min. Max.
A --- 1.10
A1 0.05 0.15
A2 0.81 0.91
B 0.25 0.40
C 0.13 0.23
D 2.90 3.10
E 2.90 3.10
H 4.90 BSC
L 0.445 0.648
e 0.65 BSC
Dimension in MM
Symbol Min. Max.
A 1.35 1.75
A1 0.10 0.25
A2 1.25 1.50
B 0.33 0.53
C 0.19 0.27
D 4.80 5.00
E 3.80 4.00
H 5.80 6.20
L 0.40 0.89
e 1.27 BSC
C
L
A2
EH
D
A1
eb
A
C
L
A2
EH
D
A1
eb
A
Preliminary ABPX1130
Advanced Programmable Clock
30332 Esperanza, Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 7
ORDERING INFORMATION
Abracon Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Abra con is believed to be accurate and reliable. However, Abracon makes no guaran tee or warranty concern ing the accuracy of s aid
information and shall n ot be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY : Abracon’s products are not authorized for use as critical components in life support devices or systems without the express
written approval of the President of Abracon Corporation.
For part ordering, please contact our Sales Department:
30332 Esperanza., Rancho Santa Margarita, Ca 92688
Ph: 949-546-8000 Fax: 949-546-8001
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
APBX1130-XXX X X-T
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number.
* PhaseLink offers Green Package Only for this product family.
Part / Order Number Marking Package Option
ABPX1130-XXXSC A3XXX 8-Pin SOIC (Tube)
ABPX1130-XXXSC-T A3XXX 8-Pin SOIC (Tape and Reel)
ABPX1130-XXXMC A3XXX 8-Pin MSOP (Tube)
ABPX1130-XXXMC-T A3XXX 8-Pin MSOP (Tape and Reel)
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I = INDUSTRIAL
PACKAGE TYPE
S=SOIC
M=MSOP
3 DIGIT ID Code * NONE= TUBE
T=TAPE and REEL
