DS2505
020998 2/23
includes a unique 48–bit serial number, an 8–bit CRC,
and an 8–bit Family Code (0BH) plus 16k bits of user–
programmable EPROM. The power to program and
read the DS2505 is derived entirely from the 1–WireTM
communication line. Data is transferred serially via the
1–Wire protocol which requires only a single data lead
and a ground return. The entire device can be pro-
grammed and then write–protected if desired. Alterna-
tively, the part may be programmed multiple times with
new data being appended to, but not overwriting, exist-
ing data with each subsequent programming of the
device. Note: Individual bits can be changed only from a
logical 1 to a logical 0, never from a logical 0 to a logical
1. A provision is also included for indicating that a cer-
tain page or pages of data are no longer valid and have
been replaced with new or updated data that is now
residing at an alternate page address. This page
address redirection allows software to patch data and
enhance the flexibility of the device as a standalone
database. The 48–bit serial number that is factory–
lasered into each DS2505 provides a guaranteed
unique identity which allows for absolute traceability.
The TO–92 and TSOC packages provide a compact
enclosure that allows standard assembly equipment to
handle the device easily for attachment to printed circuit
boards or wiring. T ypical applications include storage of
calibration constants, maintenance records, asset
tracking, product revision status and access codes.
OVERVIEW
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS2505. The DS2505 has three main data compo-
nents: 1) 64–bit lasered ROM, 2) 16384–bits EPROM
Data Memory , and 3) 704–bits EPROM Status Memory.
The device derives its power for read operations entirely
from the 1–Wire communication line by storing energy
on an internal capacitor during periods of time when the
signal line is high and continues to operate off of this
“parasite” power source during the low times of the
1–Wire line until it returns high to replenish the parasite
(capacitor) supply. During programming, 1–Wire com-
munication occurs at normal voltage levels and then is
pulsed momentarily to the programming voltage to
cause the selected EPROM bits to be programmed. The
1–Wire line must be able to provide 12 volts and 10 mil-
liamperes to adequately program the EPROM portions
of the part. Whenever programming voltages are pres-
ent on the 1–Wire line a special high voltage detect cir-
cuit within the DS2505 generates an internal logic signal
to indicate this condition. The hierarchical structure of
the 1–Wire protocol is shown in Figure 2. The bus mas-
ter must first provide one of the four ROM Function
Commands, 1) Read ROM, 2) Match ROM, 3) Search
ROM, 4) Skip ROM. These commands operate on the
64–bit lasered ROM portion of each device and can sin-
gulate a specific device if many are present on the
1–Wire line as well as indicate to the bus master how
many and what types of devices are present. The proto-
col required for these ROM Function Commands is
described in Figure 8. After a ROM Function Command
is successfully executed, the memory functions that
operate on the EPROM portions of the DS2505 become
accessible and the bus master may issue any one of the
five Memory Function Commands specific to the
DS2505 to read or program the various data fields. The
protocol for these Memory Function Commands is
described in Figure 5. All data is read and written least
significant bit first.
64–BIT LASERED ROM
Each DS2505 contains a unique ROM code that is 64
bits long. The first eight bits are a 1–Wire family code.
The next 48 bits are a unique serial number. The last
eight bits are a CRC of the first 56 bits. (See Figure 3.)
The 64–bit ROM and ROM Function Control section
allow the DS2505 to operate as a 1–Wire device and fol-
low the 1–Wire protocol detailed in the section “1–Wire
Bus System”. The memory functions required to read
and program the EPROM sections of the DS2505 are
not accessible until the ROM function protocol has been
satisfied. This protocol is described in the ROM func-
tions flow chart (Figure 8). The 1–Wire bus master must
first provide one of four ROM function commands: 1)
Read ROM, 2) Match ROM, 3) Search ROM, or 4) Skip
ROM. After a ROM function sequence has been suc-
cessfully executed, the bus master may then provide
any one of the memory function commands specific to
the DS2505 (Figure 5).
The 1–Wire CRC of the lasered ROM is generated using
the polynomial X8 + X5 + X4 + 1. Additional information
about the Dallas Semiconductor 1–Wire Cyclic Redun-
dancy Check is available in the Book of DS19xx
iButton Standards. The shift register acting as the CRC
accumulator is initialized to zero. Then starting with the
least significant bit of the family code, one bit at a time is
shifted in. After the eighth bit of the family code has been
entered, then the serial number is entered. After the
48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits
of CRC should return the shift register to all zeroes.