MC100EPT22 3.3VDual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline 8-lead package and the single gate of the EPT22 makes it ideal for those applications where space, performance, and low power are at a premium. Because the mature MOSAIC 5 process is used, low cost and high speed can be added to the list of features. http://onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC-8 D SUFFIX CASE 751 1 Features 8 420 ps Typical Propagation Delay Maximum Frequency > 1.1 GHz Typical Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V PNP LVTTL Inputs for Minimal Loading Q Output Will Default HIGH with Inputs Open The 100 Series Contains Temperature Compensation. Pb-Free Packages are Available 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 KA22 ALYWG G DFN8 MN SUFFIX CASE 506AA 3S MG G * * * * * * * KPT22 ALYW G 1 4 A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. (c) Semiconductor Components Industries, LLC, 2008 August, 2008 - Rev. 12 1 Publication Order Number: MC100EPT22/D MC100EPT22 Table 1. PIN DESCRIPTION Q0 1 8 VCC Q0 2 7 D0 LVPECL Q1 Q1 LVTTL 3 6 4 5 D1 PIN FUNCTION Q0, Q1, Q0, Q1 LVPECL Differential Outputs D0, D1 LVTTL Inputs VCC Positive Supply GND Ground EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC-8 TSSOP-8 DFN8 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 4 kV > 200 V > 2 kV Pb Pkg Pb-Free Pkg Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 UL 94 V-0 @ 0.125 in 164 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100EPT22 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 6 V 6 to 0 V 50 100 mA mA -40 to +85 C VCC Power Supply GND = 0 V VI Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range Tstg Storage Temperature Range -65 to +150 C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC-8 SOIC-8 190 130 C/W C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC-8 41 to 44 C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP-8 TSSOP-8 185 140 C/W C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP-8 41 to 44 C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 C/W C/W Tsol Wave Solder 265 265 C qJC Thermal Resistance (Junction-to-Case) 35 to 40 C/W VI v VCC Pb Pb-Free (Note 2) DFN8 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) Table 4. TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V, TA= -40C to 85C Symbol Characteristic Condition Min Typ Max Unit 20 mA IIH Input HIGH Current VIN = 2.7 V IIHH Input HIGH Current MAX VIN = VCC 100 mA IIL Input LOW Current VIN = 0.5 V -0.6 mA VIK Input Clamp Voltage IIN = -18 mA -1.0 V VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 V 0.8 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 5. PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3) -40C Symbol Characteristic 25C 85C Min Typ Max Min Typ Max Min Typ Max Unit 32 43 55 35 45 60 37 46 62 mA ICC Power Supply Current VOH Output HIGH Voltage (Note 4) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Output parameters vary 1:1 with VCC. 4. All loading with 50 W to VCC - 2.0 V. http://onsemi.com 3 MC100EPT22 Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5) -40C Characteristic Symbol Min Typ 25C Max 85C Min Typ Max 0.8 1.1 250 420 675 Min Typ Max 0.8 1.1 300 500 700 ps Unit fmax Maximum Frequency (Figure 2) 0.8 1.1 tPLH, tPHL Propagation Delay to Output Differential 250 400 650 tskew Within-Device Skew (Note 6) Device-to-Device Skew (Note 7) 50 200 100 400 50 200 100 425 50 200 100 400 ps tJITTER Random Clock Jitter (Figure 2) 0.2 <1 0.2 <1 0.2 <1 ps tr tf Output Rise/Fall Times (20% - 80%) 110 200 120 220 140 250 ps Q, Q 50 60 70 GHz 900 9 800 8 700 7 600 6 500 5 400 4 300 3 200 2 EEEEEEEEEEEEEEE EEEEEEEEEEEEEEE 100 0 0 200 400 600 800 1000 FREQUENCY (MHz) Figure 2. Fmax/Jitter http://onsemi.com 4 1 (JITTER) 1200 1400 1600 JITTEROUT ps (RMS) VOUTpp (mV) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 6. Skew is measured between outputs under identical transitions and conditions on any one device. 7. Device-to-Device Skew for identical transitions at identical VCC levels. EE EE EE MC100EPT22 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC - 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping SOIC-8 98 Units / Rail MC100EPT22DG SOIC-8 (Pb-Free) 98 Units / Rail MC100EPT22DR2 SOIC-8 2500 / Tape & Reel MC100EPT22DR2G SOIC-8 (Pb-Free) 2500 / Tape & Reel MC100EPT22DT TSSOP-8 100 Units / Rail MC100EPT22DTG TSSOP-8 (Pb-Free) 100 Units / Rail MC100EPT22DTR2 TSSOP-8 2500 / Tape & Reel MC100EPT22DTR2G TSSOP-8 (Pb-Free) 2500 / Tape & Reel MC100EPT22MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb-Free) 1000 / Tape & Reel Device MC100EPT22D MC100EPT22MNR4G For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V) AN1503/D - ECLinPSt I/O SPiCE Modeling Kit AN1504/D - Metastability and the ECLinPS Family AN1568/D - Interfacing Between LVDS and ECL AN1672/D - The ECL Translator Guide AND8001/D - Odd Number Counters Design AND8002/D - Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics of ECL Devices http://onsemi.com 5 MC100EPT22 PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AH -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. A 8 5 S B 0.25 (0.010) M Y M 1 4 -Y- K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE -Z- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100EPT22 PACKAGE DIMENSIONS TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF M T U V S 0.25 (0.010) B -U- 4 M A -V- S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S F DETAIL E C 0.10 (0.004) -T- SEATING PLANE D -W- G DETAIL E http://onsemi.com 7 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100EPT22 PACKAGE DIMENSIONS DFN8 CASE 506AA-01 ISSUE D 1 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE CCC CCC CCC CCC 2X 0.10 C 2X TOP VIEW 0.10 C 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 --- 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100EPT22/D