© Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 12
1Publication Order Number:
MC100EPT22/D
MC100EPT22
3.3V Dual LVTTL/LVCMOS
to Differential LVPECL
Translator
Description
The MC100EPT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Because LVPECL (Positive ECL) levels are used
only +3.3 V and ground are required. The small outline 8lead
package and the single gate of the EPT22 makes it ideal for those
applications where space, performance, and low power are at a
premium. Because the mature MOSAIC 5 process is used, low cost
and high speed can be added to the list of features.
Features
420 ps Typical Propagation Delay
Maximum Frequency > 1.1 GHz Typical
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
PNP LVTTL Inputs for Minimal Loading
Q Output Will Default HIGH with Inputs Open
The 100 Series Contains Temperature Compensation.
PbFree Packages are Available
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G= PbFree Package
SOIC8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R ALYWG
G
KA22
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
8KPT22
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
3S MG
G
14
(Note: Microdot may be in either location)
MC100EPT22
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2
1
2
3
45
6
7
8
D0
GND
VCC
Figure 1. 8Lead Pinout (Top View) and Logic Diagram
Q0
D1Q1
Q1
Q0
LVPECL LVTTL
Table 1. PIN DESCRIPTION
PIN
Q0, Q1, Q0, Q1
D0, D1 LVTTL Inputs
FUNCTION
LVPECL Differential Outputs
VCC Positive Supply
GND Ground
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor N/A
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg
SOIC8
TSSOP8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 164 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EPT22
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3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Power Supply GND = 0 V 6 V
VIInput Voltage GND = 0 V VI v VCC 6 to 0 V
Iout Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range 40 to +85 °C
Tstg Storage Temperature Range 65 to +150 °C
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
SOIC8
SOIC8
190
130
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase) Standard Board SOIC841 to 44 °C/W
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
TSSOP8
TSSOP8
185
140
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase) Standard Board TSSOP841 to 44 °C/W
qJA Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol Wave Solder Pb
PbFree
265
265
°C
qJC Thermal Resistance (JunctiontoCase) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
Table 4. TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V, TA= 40°C to 85°C
Symbol Characteristic Condition Min Typ Max Unit
IIH Input HIGH Current VIN = 2.7 V 20 mA
IIHH Input HIGH Current MAX VIN = VCC 100 mA
IIL Input LOW Current VIN = 0.5 V 0.6 mA
VIK Input Clamp Voltage IIN = 18 mA 1.0 V
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
ICC Power Supply Current 32 43 55 35 45 60 37 46 62 mA
VOH Output HIGH Voltage (Note 4) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
VOL Output LOW Voltage (Note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Output parameters vary 1:1 with VCC.
4. All loading with 50 W to VCC 2.0 V.
MC100EPT22
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4
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5)
Symbol Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
fmax Maximum Frequency (Figure 2) 0.8 1.1 0.8 1.1 0.8 1.1 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
250 400 650 250 420 675 300 500 700 ps
tskew WithinDevice Skew (Note 6)
DevicetoDevice Skew (Note 7)
50
200
100
400
50
200
100
425
50
200
100
400
ps
tJITTER Random Clock Jitter (Figure 2) 0.2 < 1 0.2 < 1 0.2 < 1 ps
tr
tf
Output Rise/Fall Times Q, Q
(20% 80%)
50 110 200 60 120 220 70 140 250 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
6. Skew is measured between outputs under identical transitions and conditions on any one device.
7. DevicetoDevice Skew for identical transitions at identical VCC levels.
0
100
200
300
400
500
600
700
800
900
0 200 400 600 800 1000 1200 1400 1600
1
2
3
4
5
6
7
8
9
Figure 2. Fmax/Jitter
FREQUENCY (MHz)
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
VOUTpp (mV)
JITTEROUT ps (RMS)
ÉÉ
ÉÉ
ÉÉ
MC100EPT22
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5
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC 2.0 V
ORDERING INFORMATION
Device Package Shipping
MC100EPT22D SOIC898 Units / Rail
MC100EPT22DG SOIC8
(PbFree)
98 Units / Rail
MC100EPT22DR2 SOIC82500 / Tape & Reel
MC100EPT22DR2G SOIC8
(PbFree)
2500 / Tape & Reel
MC100EPT22DT TSSOP8100 Units / Rail
MC100EPT22DTG TSSOP8
(PbFree)
100 Units / Rail
MC100EPT22DTR2 TSSOP82500 / Tape & Reel
MC100EPT22DTR2G TSSOP8
(PbFree)
2500 / Tape & Reel
MC100EPT22MNR4 DFN8 1000 / Tape & Reel
MC100EPT22MNR4G DFN8
(PbFree)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
MC100EPT22
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6
PACKAGE DIMENSIONS
SOIC8 NB
CASE 75107
ISSUE AH
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC100EPT22
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7
PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
U
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
MC100EPT22
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8
PACKAGE DIMENSIONS
DFN8
CASE 506AA01
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
A
D
E
B
C0.10
PIN ONE
2 X
REFERENCE
2 X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
8 X
A1
SEATING
PLANE
e/2 e
8 X
K
NOTE 3
b
8 X 0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K0.20 −−−
L0.25 0.35
1
14
85
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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PUBLICATION ORDERING INFORMATION
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81357733850
MC100EPT22/D
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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