7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 1 Rev 2 July 18, 2017
IDTF1950
DATASHEET
GENERAL DESCRIPTION
This document describes the specification for the F1950
Digital Step Attenuator. The F1950 is part of a family of
Glitch-FreeTM
DSAs optimized for the demanding
requirements of communications Infrastructure. These
devices are offered in a compact 4x4 QFN package with
50 Ω impedances for ease of integration into the radio
system.
COMPETITIVE ADVANTAGE
Digital step attenuators are used in Receivers and
Transmitters to provide gain control. The F1950 is a 7-
bit step attenuator optimized for these demanding
applications. The silicon design has very low insertion
loss and low distortion (+65 dBm IP3I). The device has
pinpoint accuracy and settles to final attenuation value
within 400 ns. Most importantly, the F1950 includes
IDT’s
Glitch-FreeTM
technology which results in less than
0.6 dB of overshoot ringing during MSB transitions. This
is in stark contrast to competing DSAs that
glitch as
much as 10 dB
during MSB transitions (see p.10).
Lowest insertion loss for best SNR
Glitch-FreeTM when transitioning –
won’t damage PA or ADC
Extremely accurate with low
distortion
APPLICATIONS
Base Station 2G, 3G, 4G, TDD radiocards
Repeaters and E911 systems
Digital Pre-Distortion
Point to Point Infrastructure
Public Safety Infrastructure
WIMAX Receivers and Transmitters
Military Systems, JTRS radios
RFID handheld and portable readers
Cable Infrastructure
PART# MATRIX
Part#
Freq range
Resolution
/ Range
Control
IL
Pinout
F
F1
19
95
50
0
1
15
50
0
-
-
4
40
00
00
0
0
0.
.2
25
5
/
/
3
31
1.
.7
75
5
P
Pa
ar
ra
al
ll
le
el
l
&
&
S
Se
er
ri
ia
al
l
-
-1
1.
.3
3
P
PE
E
F1951
100 - 4000
0.50 / 31.5
Serial Only
-1.2
HITT
F1952
100 – 4000
0.50 / 15.5
Serial Only
-0.9
HITT
FEATURES
Glitch-FreeTM
, < 0.6 dB transient overshoot
Spurious Free Design
3V to 5V supply
Attenuation Error < 0.3 dB @ 2 GHz
Low Insertion Loss < 1.3 dB @ 2 GHz
Excellent Linearity +65 dBm IP3I
Fast settling time, < 400 ns
Class 2 JEDEC ESD (> 2kV HBM)
Serial & Parallel Interface 31.75 dB Range
4 x 4 mm Thin QFN 24 pin package
DEVICE BLOCK DIAGRAM
ORDERING INFORMATION
RF1
Bias
VDD
VMODE
DEC
D[6:0]
7
CLK
SPI
LEDATA
RF2
0.8 mm height
package
Green
Industrial
Temp range
Tape &
Reel
Omit IDT
prefix
RF product Line
Glitch-FreeTM
Glitch-FreeTM
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 2 Rev 2 July 18, 2017
IDTF1950
DATASHEET
ABSOLUTE MAXIMUM RATINGS
VDD to GND -0.3 V to +5.5 V
D[6:0], DATA, CLK,LE, VMODE -0.3 V to 3.6 V
RF Input Power (RF1, RF2) calibration and testing +29 dBm
RF Input Power (RF1, RF2) continuous RF operation +23 dBm
θJA (Junction – Ambient) +50 °C/W
θJC (Junction – Case) The Case is defined as the exposed paddle +3 °C/W
Operating Temperature Range (Case Temperature) TC = -40 °C to +100 °C
Maximum Junction Temperature 140 °C
Storage Temperature Range -65 °C to +150 °C
Lead Temperature (soldering, 10s) +260 °C
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 3 Rev 2 July 18, 2017
IDTF1950
DATASHEET
F1950 SPECIFICATION (31.75 dB Range)
Specifications apply at VDD = +3.3V, fRF = 2000MHz, and TC= +25°C, EVkit losses are de-embedded (see p. 17) for spec purposes
Parameter
Comment
Sym.
Min
Typical
Max
Units
Logic Input High
CLK, LE, DATA, D[6:0], VMODE
VIH
2.3
3.6
V
Logic Input Low
CLK, LE, DATA, D[6:0], VMODE
VIL
0.7
V
Logic Current
VMODE
IIH, IIL
-5
+5
μA
Supply Voltage(s)
Main Supply
VDD
3.0
3.30
5.25
V
Supply Current
Total
IDD
0.25
0.51
mA
Temperature Range
Operating Range (Case)
TC
-40
+100
°C
Frequency Range
Operating Range
FRF
150
4000
MHz
RF1, RF2 Return Loss
dB(s11), dB(s22)
S11, S22
-22
dB
Minimum Attenuation
D[6:0] = [0000000]
AMIN or IL
1.3
1.9
dB
Maximum Attenuation
D[6:0] = [1111111]
AMAX
32.6
33.0
dB
Minimum Gain Step
Least Significant Bit
LSB
0.25
dB
Phase Delta
Phase change AMIN vs. AMAX
ΦΔ
34
deg
Differential Non-Linearity
Max error between
adjacent steps
DNL
0.10
dB
Integral Non-Linearity
Max Error vs. line (AMIN ref) to
13.75 dB ATTN
INL1
0.02
0.30
dB
Integral Non-Linearity
Max Error vs. line (AMIN ref) to
31.75 dB ATTN
INL2
0.27
0.45
dB
Input IP3
D[6:0] = [0000000] = AMIN
D[6:0] = [0111111] = A15.75
D[6:0] = [1111111] = AMAX
PIN = +10 dBm per tone
50 MHz Tone Separation
IP3I1
IP3I2
IP3I3
+602
+59
+57
+63
+61
+61
dBm
0.1 dB Compression
Please note ABS MAX
Input power on Page 2
D[6:0] = [0001010] = A2.5
Baseline PIN = 20 dBm
P0.1
27.5
dBm
Settling Time
Start LE rising edge > VIH
End +/-0.10 dB Pout settling
15.75 – 16.00 transition
TLSB
400
ns
Serial Clock Speed
SPI 3 wire bus
FCLK
20
50
MHz
Parallel to Serial Setup
SPI 3 wire bus
A
100
ns
Serial Data Hold Time
SPI 3 wire bus
B
10
ns
LE delay from final
serial clock rising edge
SPI 3 wire bus
C
10
ns
SPECIFICATION NOTES:
1 – Items in min/max columns in bold italics are Guaranteed by Test
2 – All other Items in min/max columns are Guaranteed by Design Characterization
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 4 Rev 2 July 18, 2017
IDTF1950
DATASHEET
SERIAL CONTROL MODE
Serial mode is selected by floating VMODE (pin3) or pulling it to a voltage > VIH. In serial mode data is clocked in LSB
first. Note the timing diagram below.
Note – The F1950 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is
not being programmed. When Latch enable is high (> VIH), the CLK input is disabled and DATA will not be clocked into
the shift register. It is recommended that LE be pulled high (> VIH) when the device is not being programmed.
SERIAL REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)
SERIAL MODE DEFAULT CONDITION:
When the device is powered up it will default to the Maximum Attenuation setting as described below:
Note that for the F1950 in all cases (High or 1) = Attenuation Stepped IN. (0 or Low) = Attenuation Stepped OUT.
SERIAL MODE TIMING TABLE:
Interval
Symbol
Description
Min
Spec
Max
Spec
Units
A
Parallel to Serial Setup Time
100
ns
B
Serial Data Hold Time
10
ns
C
LE delay from final serial clock rising edge
10
ns
Data Word 8 bits
D0 D1 D5D2 D4
D3
0.5 dB
CLK
DATA
Data Word
Latched into
Active Register
LSB D7
0.25 dB
1 2 3 4 5 6 7 8 9
1 dB 2 dB 4 dB 8 dB 16 dB
MSB
X
D6 RSV
LE
VMODE
Spec
Interval A B C
Time
Default Register Settings
1
01 1 1 1 1 1
D7 D6 D2D5 D3
D4
RSV D0
MSB D1 LSB
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 5 Rev 2 July 18, 2017
IDTF1950
DATASHEET
PARALLEL CONTROL MODE
The user has the option of running in one of two parallel modes: Direct Parallel Mode or Latched Parallel
Mode.
DIRECT PARALLEL MODE:
Direct Parallel Mode is selected when VMODE (pin 3) is < VIL and LE (pin 16) is > VIH. In this mode the
device will immediately react to any voltage changes to the parallel control pins [pins 19, 20, 21, 22, 23,
24, 1]. Use direct parallel mode for the fastest settling time.
LATCHED PARALLEL MODE:
Latched Parallel Mode is selected when VMODE (pin 3) is < VIL and LE (pin 16) is toggled from < VIL to > VIH
To utilize Latched Parallel Mode:
Set LE < VIL
Adjust pins [19, 20, 21, 22, 23, 24, 1] to the desired attenuation setting. (Note the device will not
react to these pins while LE < VIL.)
Pull LE > VIH. The device will then transition to the attenuation settings reflected by these pins.
Latched Parallel Mode implies a default state for when the device is powered up with VMODE < VIL and LE < VIL.
In this case the default setting is MAXIMUM Attenuation.
LATCHED PARALLEL MODE TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)
LATCHED PARALLEL MODE TIMING TABLE:
Interval
Symbol
Description
Min
Spec
Max
Spec
Units
A
Serial to Parallel Mode Setup Time
100
ns
B
Parallel Data Hold Time
10
ns
C
LE minimum pulse width
10
ns
D
Parallel Data Setup Time
10
ns
D[6:0]
Data Word
Latched into
Active Register
LE
VMODE
Spec
Intervals
A
DCB
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 6 Rev 2 July 18, 2017
IDTF1950
DATASHEET
TYPICAL OPERATING PARAMETRIC CURVES (EVKit loss de-embedded unless otherwise noted)
Insertion Loss vs. Frequency [AMIN]
S11 vs. Frequency [TCASE = +25C, 0.75 dB steps]
S11 vs. Attenuation State
Attenuation vs. Freq [TCASE = +25C, 0.75 dB steps]
S22 vs. Frequency [TCASE = +25C, 0.75 dB steps]
S22 vs. Attenuation State
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
200
600
1000
1400
1800
2200
2600
3000
3400
3800
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
RF Frequency (MHz)
Insertion Loss (dB)
-40
-35
-30
-25
-20
-15
-10
-5
0
200
600
1000
1400
1800
2200
2600
3000
3400
3800
RF Frequency (MHz)
RF1 Return Loss (dB)
-40
-35
-30
-25
-20
-15
-10
-5
0
0
4
8
12
16
20
24
28
-40 degC - 3.3 V - 900 MHz
-40 degC - 3.3 V - 2000 MHz
25 degC - 3.3 V - 900 MHz
25 degC - 3.3 V - 2000 MHz
100 degC - 3.3 V - 900 MHz
100 degC - 3.3 V - 2000 MHz
RF1 Return Loss (dB)
ATTN Setting (dB)
-35
-30
-25
-20
-15
-10
-5
0
200
600
1000
1400
1800
2200
2600
3000
3400
3800
RF Frequency (MHz)
DSA Loss (dB)
RF Frequency (MHz)
DSA Loss (dB)
RF Frequency (MHz)
DSA Loss (dB)
-40
-35
-30
-25
-20
-15
-10
-5
0
200
600
1000
1400
1800
2200
2600
3000
3400
3800
RF Frequency (MHz)
RF2 Return Loss (dB)
-40
-35
-30
-25
-20
-15
-10
-5
0
0
4
8
12
16
20
24
28
-40 degC - 3.3 V - 900 MHz
-40 degC - 3.3 V - 2000 MHz
25 degC - 3.3 V - 900 MHz
25 degC - 3.3 V - 2000 MHz
100 degC - 3.3 V - 900 MHz
100 degC - 3.3 V - 2000 MHz
RF2 Return Loss (dB)
ATTN Setting (dB)
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 7 Rev 2 July 18, 2017
IDTF1950
DATASHEET
TOCS CONTINUED (-2-)
Phase vs. Frequency
Supply Current IDD
Input IP3 [fRF = 1900 MHz]
Phase vs. Attenuation Setting
Input IP3 [fRF = 900 MHz]
Compression [fRF = 2000 MHz, ATTN = 2.5 dB]
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
200
600
1000
1400
1800
2200
2600
3000
3400
3800
-40 degC - 31.75 dB
-40 degC - 0.00 dB
25 degC - 31.75 dB
25 degC - 0.00 dB
100 degC - 31.75 dB
100 degC - 0.00 dB
RF Frequency (MHz)
S21 Phase (degrees)
0.0
0.2
0.4
0.6
0.8
1.0
0
5
10
15
20
25
30
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
IDD (mA)
10
20
30
40
50
60
70
80
90
0
4
8
12
16
20
24
28
-40 degC - 5.00 V
-40 degC - 2.97 V
25 degC - 5.00 V
25 degC - 2.97 V
100 degC - 5.00 V
100 degC - 2.97 V
Attenuation Setting (dB)
Input IP3 (dBm)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
4
8
12
16
20
24
28
150 MHz
400 MHz
900 MHz
1400 MHz
1900 MHz
2400 MHz
2900 MHz
3400 MHz
3900 MHz
Attenuation Setting (dB)
S21 Phase (degrees)
10
20
30
40
50
60
70
80
90
0
4
8
12
16
20
24
28
-40 degC - 5.0 V
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 5.0 V
100 degC - 3.3 V
Attenuation Setting (dB)
Input IP3 (dBm)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
20 21 22 23 24 25 26 27 28 29
Loss Compression (dB)
Input Power (dBm)
-40 degC - 5.0 V
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 5.0 V
100 degC - 3.3 V
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 8 Rev 2 July 18, 2017
IDTF1950
DATASHEET
TOCS CONTINUED (-3-)
DNL [150 MHz]
DNL [900 MHz]
DNL [2800 MHz]
DNL [450 MHz]
DNL [1900 MHz]
Worst Setting DNL
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Step Error (dB)
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Step Error (dB)
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Step Error (dB)
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Step Error (dB)
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Step Error (dB)
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
100 600 1100 1600 2100 2600 3100 3600 4100
Worst Setting Step Error (dB)
RF Frequency (MHz)
5V min DNL
5V max DNL
3.3V min DNL
3.3V max DNL
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 9 Rev 2 July 18, 2017
IDTF1950
DATASHEET
TOCS CONTINUED (-4-)
INL [150 MHz]
INL [900 MHz]
INL [2800 MHz]
INL [450 MHz]
INL [1900 MHz]
Worst Setting INL
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Absolute Error (dB)
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Absolute Error (dB)
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Absolute Error (dB)
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Absolute Error (dB)
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0
4
8
12
16
20
24
28
-40 degC - 3.3 V
25 degC - 5.0 V
25 degC - 3.3 V
100 degC - 3.3 V
Attenuation Setting (dB)
Absolute Error (dB)
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
100 600 1100 1600 2100 2600 3100 3600 4100
Worst Setting Absolute Error (dB)
RF Frequency (MHz)
5V min DNL
5V max DNL
3.3V min DNL
3.3V max DNL
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 10 Rev 2 July 18, 2017
IDTF1950
DATASHEET
TOCS CONTINUED (-5-) [fRF = 900 MHz]
Transient [ 15.75 to 16.00 (MSB+) 3.3V
F1950
]
The graphs above show the transient overshoot and
settling time performance for both the MSB+ and
MSB- cases for the F1950. The device settles very
quickly (~400) nsec with benign (~0.5) dB overshoot.
Transient [ 15.75 to 16.00 (MSB+)
Standard DSA
]
Transient [ 16.00 to 15.75 (MSB-) 5.0V
F1950
]
The graphs below show the transient overshoot and
settling time performance for a popular competing
DSA.
N
No
ot
te
e
t
th
he
e
o
ov
ve
er
rs
sh
ho
oo
ot
t/
/u
un
nd
de
er
rs
sh
ho
oo
ot
t
e
ex
xc
cu
ur
rs
si
io
on
n
o
of
f
a
al
lm
mo
os
st
t
1
10
0
d
dB
B
and the very long settling time. For the
MSB- case, the settling time is off the scale, ~ 3 usec.
Transient [ 16.00 to 15.75 (MSB-)
Standard DSA
]
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-11.88
-10.88
-9.88
-8.88
-7.88
-6.88
-5.88
-4.88
-3.88
-2.88
-1.88
-100 0100 200 300 400 500 600 700
LE Trigger (volts)
Envelope Power (dBm)
Time (nsec)
Glitch< 0.6 dB
Pwr (dBm)
Trigger
Settling Time = 400 nsec (+/- 0.1 dB)
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-15.20
-14.20
-13.20
-12.20
-11.20
-10.20
-9.20
-8.20
-7.20
-6.20
-5.20
-100 0100 200 300 400 500 600 700
LE Trigger (volts)
Envelope Power (dBm)
Time (nsec)
Pwr (dBm)
Trigger
Settling Time = 600nsec (+/- 0.1 dB)
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-12.13
-11.13
-10.13
-9.13
-8.13
-7.13
-6.13
-5.13
-4.13
-3.13
-2.13
-100 0100 200 300 400 500 600 700
LE Trigger (volts)
Envelope Power (dBm)
Time (nsec)
Glitch< 0.60 dB
Pwr (dBm)
Trigger
Settling Time = 350 nsec (+/- 0.1 dB)
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-13.57
-12.57
-11.57
-10.57
-9.57
-8.57
-7.57
-6.57
-5.57
-4.57
-3.57
-100 0100 200 300 400 500 600 700
LE Trigger (volts)
Envelope Power (dBm)
Time (nsec)
Pwr (dBm)
Trigger
Settling Time >> 1 usec
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 11 Rev 2 July 18, 2017
IDTF1950
DATASHEET
PIN DIAGRAM (F1950)
GND
VMODE
D1
D2
D5
D3
GND
*RF2
CLK
GND
*RF1
GND
LE
VDD
D4
D0 Exposed Pad
D6
GND
GND
GND
GND
2
1
3
5
4
6
Package Drawing
4 mm x 4 mm package dimension
2.60 mm x 2.60 mm exposed pad
0.5 mm pitch
24 pins
0.75 mm height
0.25 mm pad width
0.40 mm pad length
14
13
15
17
16
18
87 9 1110 12
20 192123 2224
GND
GND
DATA
CO 0.35 mm
* Device is RF Bi-Directional
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 12 Rev 2 July 18, 2017
IDTF1950
DATASHEET
PACKAGE DRAWING (4X4 24 PIN)
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 13 Rev 2 July 18, 2017
IDTF1950
DATASHEET
PIN DESCRIPTIONS
Pin #
Pin
Name
Pin Function
1
D0
Parallel Control – 0.25 dB attenuation step. Pull high for 0.25 dB Attenuation.
2
VDD
Main Supply. Use 3.3V or 5V. Current is < 1 mA.
3
VMODE
Pull low for parallel mode. Pull high or leave unconnected for serial mode.
4
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
5
RF1
Device RF input or output (bi-directional). Must AC couple to this pin.
6
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
7
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
8
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
9
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
10
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
11
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
12
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
13
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
14
RF2
Device RF input or output (bi-directional). Must AC couple to this pin.
15
GND
Connect directly to paddle ground or as close as possible to pin with thru via.
16
LE
Latch Enable. Serial Data latched into active register on rising edge.
17
CLK
Serial Clock Input
18
DATA
Serial Data Input
19
D6
Parallel Control – 16 dB attenuation step. Pull high for 16 dB Attenuation.
20
D5
Parallel Control – 8 dB attenuation step. Pull high for 8 dB Attenuation.
21
D4
Parallel Control – 4 dB attenuation step. Pull high for 4 dB Attenuation.
22
D3
Parallel Control – 2 dB attenuation step. Pull high for 2 dB Attenuation.
23
D2
Parallel Control – 1 dB attenuation step. Pull high for 1 dB Attenuation.
24
D1
Parallel Control – 0.5 dB attenuation step. Pull high for 0.5 dB Attenuation.
EP
Exposed
Paddle
Connect to Ground with multiple vias for good thermal relief.
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 14 Rev 2 July 18, 2017
IDTF1950
DATASHEET
EVKIT SCHEMATIC
The diagram below describes the recommended applications / EVkit circuit:
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 15 Rev 2 July 18, 2017
IDTF1950
DATASHEET
EVKIT OPERATION (Email: RFsupport@IDT.com to request an EVkit, Serial Control HW/SW, or TRL cal board)
The picture and graphic below describe how to operate the EVkit
RF1
DC Power
Serial
Control Port
Unused
RF2
DATA
Clock
Latch Enable
Set to 0 to use
DIP switch
0.25 dB LSB 16 dB MSB
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 16 Rev 2 July 18, 2017
IDTF1950
DATASHEET
EVKIT BOM
TOPMARKINGS
F1950 BOM Rev 02 PCB Rev 01
Item # Value Size
Desc Mfr. Part # Mfr. Part Reference Qty
11000pF 0402
CAP CER 1000PF 50V C0G 0402 GRM1555C1H102JA01D MURATA C13,14 2
210nF 0402
CAP CER 10000PF 16V 10% X7R 0402 GRM155R71C103KA01D MURATA C2,12 2
3
0.1uF 0402 CAP CER 0.1UF 16V 10% X7R 0402 GRM155R71C104KA88D MURATA C1,11 2
4 Header 2 Pin TH 2
CONN HEADER VERT SGL 2POS GOLD 961102-6404-AR 3M J5,7 2
5 Header 4 Pin TH 4 CONN HEADER VERT SGL 4POS GOLD 961104-6404-AR 3M J8 1
6 Header 8 Pin TH 8 CONN HEADER VERT SGL 8POS GOLD 961108-6404-AR 3M J6 1
7 SMA_END_LAUNCH .062
SMA_END_LAUNCH (Small) 142-0711-821 Emerson Johnson J2,3,4 3
8 0 0402
RES 0.0 OHM 1/10W 0402 SMD ERJ-2GE0R00X Panasonic R1-8,12 9
93K 0402 RES 3.00K OHM 1/10W 1% 0402 SMD
ERJ-2RKF3001X Panasonic R9-11 3
10 100K 0402 RES 100KOHM 1/10W 0402 SMD ERJ-2GEJ104X Panasonic R13,14 2
11 DIPSwitch TH 10
8 POSITION DIP SWITCH KAT1108E E-Switch U1 1
12
Digital Step Attenuator F1950Z F1950Z IDT U2 1
13 PCB
PCB Rev 01 F195XS Evkit Rev 01 1
Total 30
IDTF19
50NBGI
Z206AGA
●
Lot Code
Part Number
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 17 Rev 2 July 18, 2017
IDTF1950
DATASHEET
EVKIT THROUGH-REFLECT-LINE (TRL) CALIBRATION
The “Through-Reflect-Line” (TRL) method [1] is used to de-embed the evaluation board losses from the S-parameter measurements of the
F1950. This method requires the use of three standards: a through, a reflection, and a line. The TRL method has the advantage over other
calibration methods in that it requires only one of these three standards to be well defined.
The TRL through which is used for the F1950 TRL calibration was constructed identically to the evaluation board, minus the DUT and its
corresponding length. Therefore, the through corresponds to a precise zero length connection between the input and output reference
planes of the DUT. This through satisfies the requirement of the TRL method that one of the three standards be precisely specified.
The TRL reflection standard used is constructed identically to the input and output lines of the evaluation board, with a short placed at the
reference plane of the DUT. In accordance with the TRL method’s requirements, the actual magnitude and phase were not accurately
specified, but the phase was known to within 90 degrees and the TRL reflection standard has a magnitude close to one.
The TRL line standard is identical to the TRL through, but with an additional length of 0.8 inches (2 cm). This satisfies the TRL method’s
requirement that the TRL be a different length than the TRL through, that it have the same impedance and propagation constant as the
through, and that the phase difference between the through and the line be between 20 degrees and 160 degrees. The difference in length
yields a phase difference of approximately 20 degrees at 500 MHz, and a phase difference of 160 degrees at 4 GHz.
For characterization of performance from 150 to 500 MHz a separate TRL board with different “Line” length is used.
Standards used for F195x TRL calibration
F1950 evaluation circuit
Engen, G.F.; Hoer, C.A.; “Thru-Reflect-Line: An Improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer,” IEEE
Transactions on Microwave Theory and Techniques, Volume: 27 Issue:12, pp. 987 – 993, Dec 1979
7-bit 0.25 dB Digital Step Attenuator 150 MHz to 4000 MHz
Glitch-FreeTM Digital Step Attenuator 18 Rev 2 July 18, 2017
IDTF1950
DATASHEET
REVISION HISTORY SHEET
Rev
Date
Page
Description of Change
2
2017-Jul-18
2
18
Corrected Absolute Maximum Supply Voltage.
Added Revision History Sheet.
1
2013-Jan-15
3
5
Corrected Footer
Corrected Maximum Insertion Loss.
Added Parallel Latch Diagram.
O
2012-Nov-04
Initial Release
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