AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
FEATURES
Unique 1-Wire® Int er face Requires Onl y O ne
P o r t P in for Co mmunication
Each Dev ice has a Unique 64-Bit Serial Code
S to re d in an On-Boar d RO M
Multidrop Capability Simplifies Distributed
Temperat u r e S ensing Appl icatio ns
R equires No Exter nal Components
Can Be Po w er ed fr om Data Line. Power
Supp ly Ra nge is 3.0V to 5.5V
Measure s T emper atur es from -55°C to
+125°C (-67°F to +257°F)
±0.5°C Accuracy from -10°C to +85°C
9-Bit Thermom ete r Resolution
Co nverts Temperatur e in 750ms ( max)
User-Definab le No nvolat ile (NV) Alarm
Settings
Ala rm Se a rch Command Id e ntifie s and
Addresses De v ices Whose Temperatur e is
Outsid e P rogrammed Limits (T emper atur e
A l a rm C on dition )
Applications Include T her mostat ic Co nt ro ls,
Indu strial Syste ms, Consu mer Products,
Thermometers, o r Any Ther mally Se nsitive
System
PIN CONFIGURATIONS
DESCRIPTION
The DS18S20 digital thermometer provides 9-bit Celsius temperature measurements and has an alarm
function with nonvolatile user-programmable upper and lower trigger points. The DS18S20
communicates over a 1-Wire bus that by definition requires only one data line (and ground) for
co mmu nicat io n with a ce ntral micro pro cesso r. It has an o perat ing t emperat ure r ange o f 55°C to +125°C
and is ac curat e to ±0.5°C o ver t he range o f 10°C to +85°C. In addit io n, t he DS18S20 can der ive power
d irectly from t he data line (p ar asite po w er ”) , eliminating the need for an external power supply.
Each DS18S20 has a unique 64-bit ser ial code, whic h allo ws mu lt iple DS18S20s t o fu nc tio n o n t he sa me
1-Wire bus. Thus, it is simple to use one microprocessor to control many DS18S20s distributed over a
large area. Applications that can benefit from this feature include HVAC environmental controls,
temperature monitoring systems inside buildings, equipment, or machinery, and process monitoring and
con trol sy stems.
1-Wire is a regi stered trademark of Maxim Integrated Products, Inc.
TO-92
(DS18S20)
1
(BOTTOM VIE W)
2
3
MAXIM
DS1820
GND
DQ
V
DD
2
3
SO ( 150 mil s)
(DS18S20Z)
N.C.
N.C.
N.C.
N.C.
GND
DQ
V
DD
N.C.
6
8
7
5
3
1
2
4
DS1820
19-5474; Rev 8/10
DS18S20
High-Precision 1-
Wire Digital Thermometer
DS18S20
2 of 23
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
DS18S20
55°C to +125°C
3 TO-92
DS18S20+
55°C to +125°C
3 TO-92
DS18S20/T&R
55°C to +125°C
3 TO-92 (2000 P iece)
DS18S20+T&R
55°C to +125°C
3 TO-92 (2000 P iece)
DS18S20-SL/T&R
55°C to +125°C
3 TO-92 (2000 P iece)*
DS18S20-SL+T&R
55°C to +125°C
3 TO-92 (2000 P iece)*
DS18S20Z
55°C to +125°C
8 SO
DS18S20Z+
55°C to +125°C
8 SO
DS18S20Z/T&R
55°C to +125°C
8 SO (2500 Piece)
DS18S20Z+T&R
55°C to +125°C
8 SO (2500 Piece)
+Denotes a lead(Pb)-free/RoHS-compliant package. A “+appears on t he to p mark of le ad(Pb)-f re e pac k ages .
T&R = Tape and reel.
*TO-92 pack ages in ta pe an d re el ca n be or der ed w ith s tra ight or fo rmed lea ds. Ch oose “ SL ” for s tra ight leads . B ulk TO -92 or de rs are s t raigh t
leads only.
PIN DESCRIPTION
PIN NAME FUNCTION
TO-92 SO
1 5 GND Ground
2 4 DQ
Data Inp ut/ Outp ut. Op e n-dr ain 1 -Wire interface pin. Also p r ovid es
power to the devi ce whe n used in parasite power mode (see the
Powering the DS18S20 section.)
3 3 VDD
O p tional V
DD
. V
DD
must be grounded for o per at io n in parasite
po wer mo de.
1, 2, 6, 7,
8 N.C. No Connection
OVERVIEW
Figure 1 shows a block diagram of the DS18S20, and pin descriptions are given in the Pin Description
t able. The 64-bit ROM stores the device’ s unique serial code. The scratchpad memo ry co nt ains the 2-byte
t emper atu re reg ister t hat stor es the d ig it a l out put fro m t he te mper at ure senso r. In addit io n, t he scrat chpad
provides access to the 1-byte upper a nd low er alarm trigg er registers (T H a nd TL) . The TH and TL registers
are non vo lat ile (EE PROM) , so t hey will retain data when t he device is po wer ed do wn.
The DS18S20 uses Maxim’s exclusive 1-Wire bus protocol that implements bus communication using
one co ntrol signal. The control line require s a weak pullup resistor since all devices are linked to the bus
via a 3-state or open-drain port (the DQ pin in the case of the DS18S20). In this bus system, the
micro p ro cesso r (the mast er dev ice) identifies and addr esses de v ices on the bus using each de vice’s unique
64-bit code. Because each device has a unique code, the number o f devices t hat can be addressed on one
bus is virtually unlimited. The 1-Wire bus pr otocol, including det a iled explanatio ns o f the commands and
“t ime slots,” is covered in the 1-Wire Bus S yst e m section.
Another feature of the DS18S20 is the ability to operate without an external power supply. Power is
instead supplied through the 1-Wire pullup resistor via the DQ pin when the bus is high. The high bus
signal also charges an internal capacitor (CPP), whic h then supplies po wer to the device w hen t he bus is
low. This method of deriving power from the 1-Wire bus is referred to as “parasite power.” As an
alt er native , the DS1 8S 20 may als o be pow er ed by a n exte rnal s upply on V DD.
DS18S20
3 of 23
Figure 1. DS18S20 Block Diagram
OPERATIONMEASURING TEMPERATURE
The core fu nct ionality of t he DS18S20 is it s direc t-to-dig it al temperature sensor. The temperatur e sensor
output has 9-bit resolution, which corresponds to 0.5°C steps. The DS18S20 powers-up in a low-power
idle st at e; to init iat e a t emperat ur e measure ment and A-to-D co nver sio n, t he mast er mu st issue a Co nvert
T [44h] command. Following the conversion, the resulting thermal data is stored in the 2-byte
temperat ure register in the scrat chpad memor y and the DS18S20 ret ur ns t o it s idle state. If the DS18S20
is powered by an external supply, the master can issue read-time slots” (see the 1-Wire Bus System
section) after the Convert T command and the DS18S20 will respond by transmitting 0 while the
t emperat ur e convers io n is in prog r ess and 1 whe n the convers io n is do ne. If the DS18S2 0 is po wer ed wit h
parasite power, this notificat ion technique cannot be used since the bus must be pulled high by a strong
pu llup during the entir e temp er atur e conversion. T he bus require ment s for p ar as ite power are explained in
detail in the Powering the DS18S20 section.
The DS18S20 out put data is ca librated in degrees cent igrade; fo r Fahr enheit applicatio ns, a lookup table
or conversion routine must be used. The temperature data is stored as a 16-bit sign-extended two’s
complement number in the temperature register (see Figure 2). The sign bits (S) indicate if the
temperature is positive or negative: for posit ive numbers S = 0 and for negative numbers S = 1. Table 1
gives examples of digital output data and the corresponding temperature read ing.
Reso lu t io ns great er t han 9 bits can be ca lculat ed using t he dat a fro m t he t e mp erat ure, COUNT RE MAI N
and COUNT PER °C registers in t he scratchpad. Note that the COUNT PE R °C register is hard-w ir e d to
16 (10h). After reading the scratchpad, the TEMP_READ value is obtained by truncating the 0.5°C bit
(bit 0) from the temperature data (see Figure 2). The extended resolution temperature can then be
calculat ed using the follow ing equation:
CPERCOUNT REMAINCOUNTCPERCOUNT
READTEMPETEMPERATUR __ ___
25.0_
+=
V
PU
4.7k
POWER-
SUPPLY
SENSE
64-BIT ROM
AND
1-Wir e POR T
DQ
VDD
INTERNAL V
DD
C
PP
PARASITE POWER
CIRCUIT
MEMORY CONTROL
LOGIC
SCRATCHPAD
8-BIT CRC GENERATOR
TEM PERATU RE SENS OR
ALARM HIGH TRIGGER (T
H
)
REGISTER (EEPROM)
ALARM LOW TRIGGER (T
L
)
REGISTER (EEPROM)
GND
DS18S20
DS18S20
4 of 23
Figure 2. Tem p eratu r e Register Format
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
L S BYTE
26 25 24 23 22 21 20 2-1
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
MS BYT E
S S S S S S S S
S = SIGN
Table 1. Temperatur e/D ata Relationsh ip
TEMPERATURE
(
°
C) DIG ITAL OUTPUT
(BINARY) DIGITA L O U TPUT
(HEX)
+85.0*
0000 0000 1010 1010
00AAh
+25.0 0000 0000 0011 0010 0032h
+0.5
0000 0000 0000 0001
0001h
0
0000 0000 0000 0000
0000h
-0.5
1111 1111 1111 1111
FFFFh
-25.0
1111 1111 1100 1110
FFCEh
-55.0
1111 1111 1001 0010
FF92h
*The power-on reset value of the temperature register i s +85°C.
OPERATIONALARM SIGNALING
After the DS18S20 performs a temperature conversion, the temperature value is compared to the user-
defined twos complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure 3).
The s ig n bit ( S) in d ic at e s if the va lu e is pos itive o r negative: for posit ive numbers S = 0 and for negative
numbers S = 1. The TH and TL registers are nonvolatile (EEPROM) so they will retain data when the
device is po wered do wn. T H and T L can be access ed t hrough byt e s 2 and 3 o f t he scr at chpad as e xp laine d
in the Memory section.
Figure 3. TH and TL Register Format
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
S 26 25 25 25 22 21 20
Only bits 8 through 1 of the temperature register are used in the TH and TL compar ison since TH and TL
are 8-bit registers. If the measured temperature is lo we r t han or equa l t o TL or higher than TH, an alar m
condit ion exists and an alarm flag is set inside the DS18S20. This flag is updated a ft er ever y t e mper atur e
measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next
temper atur e conversion.
The mast er dev ice can c heck the alar m flag st atus o f all DS18S20s on t he bus by issuing an A lar m Sear ch
[ECh] command. Any DS18S20s with a set alarm flag will respond to the command, so the master can
deter mine exact ly which DS18S20s ha ve experienced an alarm condition. If an alar m co ndition e xist s and
t he T H or TL sett ings have c ha nged , a not her t emp era ture conver s io n s hould be do ne to va lida te t he ala r m
condition.
DS18S20
5 of 23
POWERING THE DS18S20
The DS18S20 can be powered by an e xter nal supply on the VDD pin, or it ca n o perat e in “paras ite power
mode, which allows the DS18S20 to function without a local external supply. Parasite power is very
useful for applications that require remote temperature sensing or those with space constraints.
Figure 1 shows the DS18S20’s parasite-power control circuitry, which “steals” power from the 1-Wire
bus via the DQ pin when the bus is high. The stolen charge powers the DS18S20 while the bus is high,
and so me o f t he charge is st ored on t he parasite po wer capacit or (CPP) to pro vide power when t he bus is
low. Whe n t he DS18S 20 is used in parasite power mo d e, t he VDD pin must be conne cte d to g r ound .
In parasite power mode, the 1-Wire bus and CPP can provide sufficient current to the DS18S20 for most
operations as long as the specified timing and voltage requirements are met (see the DC Electrical
Characteristics and the AC Electrical Characteristics). However, when the DS18S20 is performing
t emper atu re convers io ns o r copying data fro m the scrat chpad me mo r y to EEPROM, the oper at ing cur rent
can be as high as 1.5mA. This current can cause an unacceptable voltage drop across the weak 1-Wire
pu llup res ist or and is more cur r ent than can be supplied by CPP. T o assure that t he DS18S 20 ha s suf fi cient
supply current, it is necessary to provide a strong pullup on the 1-Wire bus whenever temperature
conversions are taking place or data is being copied from the scratchpad to EEPROM. This can be
accomplished by using a MOSFET to pull the bus directly to the rail as shown in Figure 4. The 1-Wire
bus must be sw it ched to t he strong pullup w it hin 1 0µs (ma x) a fter a Convert T [44h] or Copy Scratchpa d
[48h] comma nd is issued, and t he bus must be held high by t he pu llup for the duration of t he conve rsion
(tCONV) or data transfer (tWR = 1 0ms). No o ther act iv ity ca n t ake place on t he 1-Wire bu s w h i le the pullup
is enab le d.
The DS18S 20 can also be powered by the conventional metho d of connecting an exter nal power supp ly to
the VDD pin, as shown in Figure 5. The advantage of this method is that the MOSFET pullup is not
requir ed , and the 1-Wire bus is free t o car r y other traffic during the temperat u r e conver sion time.
The use of parasite po w er is not recommended for temp er atur es above 1 00 °C since the DS18S20 may not
be able to sust ain communicat io ns due t o t he higher leakage cur rents t hat can e xist at t hese te mperat ur es.
For applicat ions in which suc h t emperat ures are likely, it is strongly reco mmended that the DS18S20 be
po wered by an ext er nal power supply.
In so me sit uat ions t he bu s ma st er ma y no t know whet her t he DS 18S2 0s o n t he bus ar e par asit e p ow er ed
o r powere d by ext ernal sup plies. The mast er need s t his in fo r mat ion t o det er mine if t he st ro ng bus p u llup
shou ld be used during temperat ur e co nversions. To g et t h is information, the mast er can issue a Skip ROM
[CCh] command followed by a Read Power Supply [B4h] command followed by a “read-time slot”.
During the read-time slot, parasite powered DS18S20s will pull the bus low, and externally powered
DS18S20s will let the bus re main hig h. I f t he bus is pu lled lo w, t he master knows t hat it must supp ly the
strong pullup o n t he 1-Wire bus dur ing temperat ure conversions.
DS18S20
6 of 23
Figure 4. Supplying the Parasite-Pow er ed DS18S 20 During Temperature Conversions
Figure 5. Powering the DS18S20 with an External Supply
64-BIT LASERED ROM CODE
Each DS18S20 co ntains a uniqu e 64-bit code (see Figure 6) stor ed in ROM . The leas t signif icant 8 b its of
the ROM code contain the DS18S20’s 1-Wire family code: 10h. The next 48 bits contain a unique ser ia l
numb er . The mos t sign ificant 8 bit s contain a cyclic redundancy check (CRC) byte t hat is calculat ed from
the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in the CRC
Generation section. The 64-bit ROM code and associated ROM function control logic allow the
DS18S20 to opera te as a 1-Wire device using the protocol detailed in the 1-Wir e Bus S yst e m section.
Figure 6. 64-Bit Lasered ROM Code
8-BIT CRC
48-BIT SERIAL NUMBER
8-BIT FAMI LY CODE (10h)
V
PU
V
PU
4.7k
1-Wire BUS
µ
P
DS18S20
GND
V
DD
DQ
TO OTHER
1-WIRE DEVICES
V
DD
(EXTER NAL SUPPL Y)
DS18S20
GND
V
DD
DQ
V
PU
4.7k
TO OTHER
1-WIRE DEVICES
1-Wire BUS
µ
P
MSB
MSB
LSB
LSB
LSB
MSB
DS18S20
7 of 23
MEMORY
The DS18S20’s memory is organized as shown in Figure 7. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL).
Note t hat if the DS18S2 0 alarm fu nction is not used, the TH and TL registers can ser ve a s general-purpose
memory. All memo ry commands ar e des c ribe d in detail in the DS18S20 Function Commands section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respect ivel y. T hese byt es are read-o nly. Byt e s 2 and 3 provide access to TH and T L reg isters. Bytes 4 and
5 are r es er ved for inte rnal use b y the dev ice and c annot be ove rw rit te n; these byt es wil l re tu rn all 1s when
read. Bytes 6 a nd 7 co ntain t he COUNT REMAI N and CO UNT PER ºC registers, which can be u sed to
calculat e ext ended r esolution resu lts as exp lained in the Operation—Measuring Temperature section.
Byte 8 of t he scr atchpad is read-on ly a nd c o nt ai ns the C R C code fo r byt e s 0 through 7 o f t he scratchpad.
The DS18S20 generates this CRC using the method described in the CRC Generation section.
Data is written to bytes 2 and 3 of the scratchpad using the Write Scratchpad [4Eh] command; the data
must be transmitted to the DS18S20 starting with the least significant bit of byte 2. To verify data
integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the least
signif ica nt bit of byte 0. T o transfer the TH and T L data from the scratchpad t o EEP ROM, t he mast er must
issue t he Co py Scr atchpad [48h] command.
Data in t he EEPROM registers is reta ined when t he de vic e is power ed down; at power-up t he EE PROM
dat a is r eload ed into the corresponding scratchpad locations. D ata ca n also be reloaded fr om EEP ROM to
the scratchpad at any time using the Recall E2 [B8h] command. The master can issue “read-time slots”
(see t he 1-Wire B us Sy ste m sect io n) follo w ing t he Reca ll E2 command and t he DS18S20 w ill indicate t he
st atu s of the reca ll by tr ansmitting 0 while t he recall is in pro g r ess and 1 when the reca ll is done.
Figure 7. DS18S20 Memory Map
SCRATCHPAD
(POWER-UP STATE)
Byte 0 Temperature LSB (AAh)
Byte 1 Temperat ur e MSB (00h) EEPROM
Byte 2 TH Reg ister o r User B yte 1* TH Reg ister o r User B yte 1
Byte 3 TL Register or User Byte 2* TL Reg ist er o r User Byte 2
Byte 4 Reserved (FFh)
Byte 5 Reserved (FFh)
Byte 6 COUNT RE MAIN (0Ch)
Byte 7 COUN T PER °C (1 0h)
Byte 8 CRC*
*
Power-up st ate depends on value(s) stored i n EEPROM.
(85°C)
DS18S20
8 of 23
CRC GENERATION
CRC byt es are provided as p art of the DS18S20’s 64-bit ROM co de a nd in t he 9t h byt e of t he scrat chpad
memory. The ROM co de CRC is ca lcu lat ed fro m t he first 5 6 b it s of t he ROM cod e and is co nt ained in t he
most significant byte of the ROM. The scratchpad CRC is calculated from the data stored in the
scrat chpad, and t here fore it changes when the data in the scratchpad chang es. The CRCs pro vide the bus
mast er with a method o f data validation when data is read fr om the DS18S2 0. To ver ify that data has been
read correctly, the bus master must re-calculate the CRC from the received data and then compare this
value to eit her the ROM co de CRC ( for ROM reads) or to the scrat chpad CRC ( for scrat chpad reads). If
t he calcu lated CRC mat ches the read C RC, the dat a ha s been rece ived err or free. T he comparison of CRC
values a nd t he dec ision to co ntinue w it h a n oper ation are det er mined e nt ir ely by t he bus mast er. T here is
no circuitry inside the DS18S20 that prevents a command sequence from proceeding if the DS18S20
CRC (ROM or scr atchpad) d oes not mat ch t he va lue generat ed by the bus mast er .
T he equivalent p olynom i al f unction of the C RC (ROM or s cr atc hpad) is:
CRC = X8 + X5 + X4 + 1
The bus master can re-calcu lat e the CRC and compare it to the CRC valu es from the DS18S20 using t he
po lyno mial generator shown in Figure 8. This circuit consists of a shift register and XOR gates, and the
shift register bits are init ialized to 0. Starting with the least significant bit o f the ROM code or the least
significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After
shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the
po lyno mial generator will cont ain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC
from the DS18S20 must be shifted into the circuit. At this po int, if the re-calcu lat ed CRC was corr ect, the
sh ift re gis ter w ill contain all 0s . Ad ditional info rm a tio n abou t t he M axim 1-Wire cyclic redundancy check
is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim
iButton Products.
Figure 8. CRC Generator
(MSB) (LSB)
XOR XOR
XOR
INPUT
DS18S20
9 of 23
1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18S20 is
always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”
s ys tem; the sys tem is multid rop if t he re a re multiple s laves on the bu s .
All data and commands are t r ansmitted least signif ica nt bit f irst ov er the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
co nfiguration, transaction sequence, a nd 1-Wire signaling (sig nal types and timing) .
HARDWARE CONFIGURATION
The 1-Wire bus has by definit io n only a single data line. Each device (master or slave) interfaces to the
data line via an open drain or 3-state port. This allows each device to “release” the data line when the
device is no t t ransmitt ing data so t he bus is available for use by another device. The 1-Wire port of the
DS1 8S 20 ( the DQ p in) is ope n dr ain with a n internal cir cuit eq ui valent to tha t shown in Figure 9.
The 1-Wire bus requires an external pullup resistor of approximately 5k; thus, the idle state for the
1-Wire bus is high. If for any r eason a trans action ne eds to be s uspend e d, the bus M US T be left i n the idl e
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inact ive ( hig h) st ate during the reco very period. If t he bus is held low fo r more t han 480µs,
all c omponents on t he bus wi ll be reset.
Figure 9. Hardware Configuration
V
PU
4.7k
5μA
TYP
Rx
Tx
DS18S20 1-Wire PORT
100
MOSFET
TX
Rx
Rx = RECEIVE
Tx = TRANSMIT
1-Wire BUS
DQ
PIN
DS18S20
10 of 23
TRANSACTION SEQUENCE
The t r ansaction sequence for access ing the DS18S20 is as fo llows:
S tep 1. Initialization
S tep 2. ROM Command (follo wed by an y required data exchange)
S tep 3. DS18S20 Function Comma nd ( followed by any r equired dat a exchange)
I t is very im porta nt t o follow th is se qu ence every time the DS18S20 is acces sed, a s t he DS18S 20 w i ll not
respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search
ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM commands, the
master must r eturn to Step 1 in the seque nce.
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
sla ve(s). T he presence pulse let s the bus master kn ow that slave devices ( such as t he DS18S 20 ) ar e on t h e
bus a nd are read y t o op erate. T iming for t he re set and pre se nce pu lses is det a iled in t he 1-Wire Sign aling
section.
ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM command. These commands
operate on the unique 64-bit ROM co des of each sl ave de vice a nd a llow the mast er to single o ut a specific
device if many are present on the 1-Wire bus. These co mmands also allow the ma ster to determine how
many and what types of devices are present on the bus or if any device has experienced an alarm
condition. There are five ROM commands, and each command is 8 bits long. The master device must
issue an appropriate ROM command before issuing a DS18S20 function command. A flowchart for
op er ation of the R OM c ommands is shown in Figure 14.
SEARCH ROM [F0h]
When a system is initially powered up, the master must identify the ROM codes of all slave devices on
the bus, which allows the master to determine the number of slaves and their device types. The master
learns t he ROM codes t hrough a process o f elimination that r eq uires the ma ster to per for m a Search RO M
cycle ( i. e. , Sear ch RO M co mma nd fo llo wed b y d at a exchange) as many t imes as neces sar y t o ide nt ify al l
of t he slave devices. If t here is o nly one slave on t he bus, the simpler Read ROM co mmand (see be low )
can be used in place of the Search ROM process. For a detailed explanation of the Search ROM
procedure, refer to the iButton® Book of Standards at www.maxim-ic.com/ibuttonbook. After every
Search ROM cyc le, the bu s mast er must ret ur n to St ep 1 (Initia lization) in the t r ansact io n sequ ence.
READ ROM [33h]
This co mmand ca n o nly be used when there is one slave o n the bu s. It allo ws the bu s mast er to read the
s la ve s 6 4-bit ROM code w it ho ut using t he Se arch ROM procedure. I f t his command is us ed when there
is more than one slave present on the bus, a data collision will occur when all the slaves attempt to
respond at the same t ime.
MATCH ROM [55h]
The match ROM co mmand follo wed by a 64-bit ROM code sequence allow s the bus master to address a
specific slave device on a multidrop or single-drop bus. Only the slave that exactly matches the 64-bit
ROM code sequence will respond to the function command issued by the master; all other slaves on the
bus will wa it fo r a r eset p ulse.
iButton is a registered trademark of Maxim Integrated Products, Inc.
DS18S20
11 of 23
SKIP ROM [CCh]
The master can use this co mmand to address all devices on the bus simultaneously without sending out
any ROM code information. For example, the master can make all DS18S20s on the bus perform
simultaneous temperature convers io ns by issuing a Skip ROM co mmand fo llowed by a Convert T [44h]
command.
Note that the Read Scratchpad [BEh] command can follow the Skip ROM command only if there is a
single slave device on the bus. In this case, time is saved by allowing the master to read from the slave
without sending the device’s 64-bit ROM code. A Skip ROM command followed by a Read Scratchpad
command wil l ca us e a data coll ision on the bus i f there is mor e th an one slave sin ce multiple devices wi ll
attempt to transmit data simultan eously.
ALARM SEARCH [ECh]
The operation of this command is identical to the operation of the Search ROM command except that
only slaves with a set alarm flag will respond. This command allows the master device to determine if
any DS18S20s experienced an alarm condition during the most recent temperature conversion. After
every A lar m S earc h c ycle ( i. e., Alar m Search co mmand fo llo wed by d at a exc ha nge), t he bus ma st er must
return to Step 1 (Init ialization) in the transaction sequence. See the Operation—Alarm Signaling section
for an e xpla natio n o f alar m flag op er ation.
DS18S20 FUNCTION COMMANDS
After the bus master has used a ROM command to address the DS18S20 with which it wishes to
communicate, t he mast er can issue o ne o f t he DS18S20 funct ion co mma nd s. These co mmands allow the
mast er to write to and read from the DS18S 20 s s cratchpad memory, initiat e te mperat ur e convers io ns and
determine the power supply mode. The DS18S20 function commands, which are described below, are
su mma r iz ed in Table 2 and il lustr ated b y the flowchart in Figure 15.
CONVERT T [44h]
This co mmand init iates a single temperature convers io n. Follo w ing t he c onvers io n, t he resu lt ing t he r ma l
dat a is st or ed in t he 2-byt e t emperat ur e register in t he scratchpad memo r y and t he DS18S20 r et urns to it s
low-power idle state. If the device is being used in parasite power mode, within 10µs (max) after this
command is issued the master must enable a strong pullup on the 1-Wire bus for the duration of the
co nvers io n (t CONV) as descr ibed in the Powe ring the DS18S20 section. I f the DS18S20 is powered by an
ext erna l su pp ly, t he ma ster can issue read-time slot s aft er t he Co nvert T co mma nd a nd the DS18S 20 wi ll
respond by transmitt ing 0 while the temperature conversion is in progress and 1 when t he conversio n is
done. In parasite power mode this notification technique cannot be used since the bus is pulled high by
t he st ro ng pullup dur ing the conversion.
WRITE SCRATCHPAD [4Eh]
This command allows the master to write 2 bytes of data to the DS18S20’s scratchpad. The first byte is
wr itt en int o t he T H reg ist er (byte 2 o f the scrat chpad), and t he second byte is writt en into t he T L register
(byte 3 of the scratchpad). Data must be transmitted least significant bit first. Both bytes MUST be
written be fore the mast er issues a r eset, or the data may be cor r u pt ed.
READ SCRAT CHPAD [BEh]
This co mmand allo ws t he ma ster to read t he contents of the scratchpad. The data transfer starts w it h t he
least significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8 CRC) is
read. The master may issue a reset t o ter minate reading at any t ime if only part of the scrat chpad d at a is
needed.
DS18S20
12 of 23
COPY SCRATCHPAD [48h]
This co mmand cop ies the cont ents of the scrat chpad TH and TL r egist ers (byt es 2 and 3) to E EPROM. I f
the device is being used in parasite power mode, within 10µs (max) after this command is issued the
master mu st enable a strong pu llup on the 1-Wire bus fo r at least 10ms as descr ibed in the Powe rin g the
DS18S20 section.
RECALL E2 [B8h]
T his comma nd r ec a lls t he ala r m tr igg e r va lu e s ( T H and TL) fr o m E EP ROM and p laces t he dat a in bytes 2
and 3, respect ively, in the scratchpad memo ry. The mast er device can issue read-time s lo t s follo w in g t he
Recall E2 command and the DS18S20 will indicate the status of the recall by transmitting 0 while the
recall is in progr ess a nd 1 w hen t he reca ll is do ne . The recall operat io n happe ns aut omat ic ally at power-
up, so valid dat a is avai la ble in the scratchpad as soon as power is applied to the device.
READ POWER SUPPLY [B4h]
The mast er dev ice issues this command fo llowed by a read-t ime slot to determine if any DS18S20 s on the
bus are using par as ite power. D uring the read-time slot, parasite powered DS18S20s will pu ll t he bus lo w,
and externally powered DS18S20s will let the bus remain high. See the Powering the DS18S20 section
for usage info rmation for this comma nd.
Table 2. DS18S20 Function Command Set
COMMAND DESCRIPTION PROTOCOL
1-Wire BUS ACTIVITY
AFTER COMM AND IS
ISSUED
NOTES
TEMPERATURE CONVERSION COM MANDS
Convert T
Initiates temperature
conversion. 44h
DS18S20 tran smits conv ersion
st atu s to mast er ( not applicable
for p ar as ite-powered
DS18S20s).
1
MEMORY COM MANDS
Read
Scratchpad
Reads t he ent ire
scratchpad including the
CRC byt e . BEh
DS18S20 transmits up to 9
dat a b yt es to ma ster. 2
Write
Scratchpad
Writ es data int o
scratchpad bytes 2 and 3
(TH and TL).
4Eh
Master t r ansmits 2 data bytes
to DS18S20. 3
Copy
Scratchpad
Copies T
H
and T
L
data
fr om the scrat chpad to
EEPROM.
48h
None
1
Recal l E
2
Recal ls T
H
and T
L
data
from EEPROM to the
scratchpad.
B8h
DS18S20 tran smits recall
status to master.
Read Power
Supply
S ignals DS18S20 power
supply mode to the
master.
B4h
DS18S20 tran smits supply
status to master.
Note 1:
For par a sit e-powered DS18S20s, the m aster must enabl e a strong pullup on the 1-Wire bus during tempe rature
conver sions and copies from the scratch pad to EEPROM. No oth er bus activity may take place during this time.
Note 2:
The master can interrupt the transmission of data at any time by issuin g a reset.
Note 3:
Both byt es must be written befor e a reset is issued.
DS18S20
13 of 23
1-WIRE SIGNALING
The DS18S20 uses a strict 1-Wire co mmunication protocol to ensure data integrity. Several signal types
are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All these
signa ls, with the exception of the prese nce pu lse, are initiat ed b y t he bus master.
INIT IALIZATION PROCEDURERESET AN D PRESENCE PULSES
All co mmunicat io n w ith t he DS18S20 beg ins with an in it ia liz at ion sequen ce that co nsist s of a reset pu lse
from the master fo llowed by a presence pulse from the DS18S20. This is illustrated in Figure 10. Whe n
the DS18S20 sends the presence pulse in response to the reset, it is indicating to the master that it is on
the bus and r eady to operate.
Dur ing t he init ializatio n sequ ence t he bu s master transmits (T X) t he reset pu lse by pu lling t he 1-Wire bus
low for a minimum of 480µs. The bus master then releases the bus and goes into receive mode (RX).
When t he bus is released, the 5k pullup re sist o r pu lls t he 1-Wire bus high. When the DS18S20 detects
this rising edge, it wait s 15µs to 60µs and then transmit s a presence pulse by pu lling t he 1-Wire bus low
for 60µs to 240µs.
Figure 10. Initializati on Timing
READ/WRITE TIME SLOTS
The bus master writes data to the DS18S20 during write time slots and reads data from the DS18S20
dur ing read-t ime slots. One bit o f data is t r ansmitted over t he 1-Wire bus per time slo t.
WRITE TIME SLOTS
There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master
uses a Wr it e 1 time slo t to wr it e a lo g ic 1 t o t he DS18S20 and a Write 0 time slo t to wr it e a lo g ic 0 to t he
DS18S20. All wr it e time slot s must be a minimum o f 60µs in dur atio n with a mini mum of a 1µs recovery
t ime bet ween ind ivid ua l wr it e s lo t s. Bo t h type s o f wr it e t ime s lot s a re init iat ed by the mast er pu llin g t he
1-Wire bus low (see Figure 11).
To generat e a Writ e 1 t ime slo t , after p ulling t he 1-Wire bus lo w, t he bus mast er mu st r elease t he 1-Wire
bus wit hin 15µs. When the bus is relea sed, the 5k pullup resistor will pull the bus high. To generate a
Write 0 time slo t, aft er pulling the 1-Wire bus low, t he bu s ma st er mu st co nt inue t o ho ld the bus low for
the duration of the time slot (at least 60µs). The DS18S20 samples t he 1-Wire bu s dur ing a w ind ow t hat
lasts from 15µs to 6 0 µs after the master initiat es the write time slot . If the bus is high during t he sa m pling
wind ow, a 1 is w ritte n to the DS18S20. I f the line is low, a 0 is writ ten to the DS18S20.
LINE TYPE LEGEND
Bus master pulling low
DS 18S20 pull ing low
Resistor pul lu p
VPU
GND
1-WIRE BUS
480µs minimum
480µs minimum
DS18S20 T
X
presence pulse
60-240
µ
s
MASTER T
X
RESET PULSE
MASTER R
X
DS18S20
waits 15-60
µ
s
DS18S20
14 of 23
READ-TIME SLOTS
The DS18S 20 ca n on ly tr ansmit dat a to the mast er whe n the mast er issues r ead-time s lo t s. T he r e fo r e , t he
master must generat e read-time slots immed iately a ft er issuing a Read Scratchpad [BE h] or Read Power
Supp ly [B4h] co mmand, so t hat the DS18S20 can pro vide t he r equested dat a. In addition, t he mast er can
generat e read-t ime slo t s a ft er iss u ing Conve r t T [ 44 h] or Re ca ll E 2 [ B8h] co mma nds t o find o ut the st at us
of the operation as expla ined in the DS18S20 Function Commands section.
All read-time slots must be a minimum of 60µs in duration with a minimum of a 1µs recovery time
between slots. A read-time slot is initiated by the master device pulling the 1-Wire bus low for a
minimum o f 1µs a nd t hen r e lea sin g t he bus ( see Figure 11) . Aft er the ma ster init iates t he r ead-time slot,
t he DS18S20 w ill beg in t ransmit t ing a 1 or 0 on bus. T he DS18S20 t ransmits a 1 by lea ving t he bus hig h
and t ransmit s a 0 by pulling t he bus low. When transmitting a 0, t he DS18S20 will re lease t he bus by the
end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output
data from t he DS18S20 is valid for 15µs after t he fall ing edge t hat initiated the read-t ime s lo t . T herefore,
t he master must r elease t he bus and the n samp le t he bus st ate wit hin 15µs from the start of the slot.
Figure 12 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less t han 15µs for a read-time slot.
Figure 13 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by locating the mast er sample time dur ing read -time slots to war d s the end of the 15µs perio d.
Figure 11. Read/Write Time Slot Timing Diagram
45
µ
s
15
µ
s
VPU
GND
1-WIRE BUS
60µs < T
X
0” < 120µs
1
µ
s < TREC <
DS18S20
Samples
MIN TYP MAX
15µs
30µs
> 1
µ
s
MASTER WRITE “0” SLOT
MASTER WRITE “1” SLOT
VPU
GND
1-WIRE BUS
15µs
MASTER READ “0” SLOT
MASTER READ “1” SLOT
Master samples
Master samples
START
OF SLOT
START
OF SLOT
> 1
µ
s
1
µ
s < TREC <
15µs
15µs
30µs
15
µ
s
DS18S20 Samples
MIN TYP MAX
> 1µs
LINE TYPE LEGEND
Bus master pulling low DS 18S20 pull ing low
Resis tor pull up
DS18S20
15 of 23
Figure 12. Detailed Master Read 1 Timing
Figure 13. Reco mmended Master Read 1 Timing
V
PU
GND
1-WIRE B US
15µs
VIH of Master
T
RC
T
INT
> 1µs
Master samples
LINE TYPE LEGEND
Bus master pulling low
Resistor pul lu p
V
PU
GND
1-WIRE B US
15µs
VIH of Master
T
RC
=
small
T
INT
=
small
Master samples
DS18S20
16 of 23
Figure 14. ROM Commands Flowchart
CCh
SKIP ROM
COMMAND
MASTER TX
RESET PULSE
DS18S20 T
X
PRESENCE
PULSE
MASTER T
X
ROM
COMMAND
33h
READ ROM
COMMAND
55h
MATCH ROM
COMMAND
F0h
SEARCH ROM
COMMAND
ECh
ALARM SEARCH
COMMAND
MASTER T
X
BIT 0
DS18S20 T
X
BIT 0
DS18S20 TX BIT 0
MASTER TX BIT 0
BIT 0
MATCH?
MASTER TX
BIT 1
BIT 1
MATCH?
BIT 63
MATCH?
MASTER T
X
BIT 63
N
Y Y Y Y Y
N
N
N
N
N
N
N
Y
Y
Y
DS18S20 TX BIT 1
DS18S20 TX BIT 1
MASTER T
X
BIT 1
DS18S20 TX BIT 63
DS18S20 TX BIT 63
MASTER TX BIT 63
BIT 0
MATCH?
BIT 1
MATCH?
BIT 63
MATCH?
N
N
N
Y
Y
Y
DS18S20 TX
FAMILY CODE
1 BYTE
DS18S20 TX
SERIAL NUMBER
6 BYTES
DS18S20 TX
CRC BYTE
DS18S20 TX BIT 0
DS18S20 TX BIT 0
MASTER TX BIT 0
N
Y
DEVICE(S)
WITH ALARM
FLAG SET?
Initialization
Sequence
MASTER TX
FUNCTION
COMMAND
(FIGURE 15)
DS18S20
17 of 23
Figure 15. DS18S20 Function Commands Flowchart
MASTER TX
FUNCTION
COMMAND
Y
N
44h
CONVERT
TEMPERATURE
?
PARASITE
POWER
?
N
Y
DS18S20 BEGINS
CONVERSION
DEVICE
CONVERTING
TEMPERATURE
?
N
Y
MASTER
RX “0s”
MASTER
RX “1s”
MASTER ENABLES
STRONG PUL LUP ON DQ
DS18S 20 CONVERTS
TEMPERATURE
MASTER DISABLES
STRONG PUL LUP
Y
N
48h
COPY
SCRATCHPAD
?
PARASITE
POWER
?
N
Y
MASTER ENABLES
STRONG PULL-
UP ON DQ
DATA COPIED FROM
SCRATCHPAD TO EEPROM
MASTER DISABLES
STRONG PUL LUP
MASTER
RX “0s”
COPY IN
PROGRESS
?
Y
MASTER
R
X
“1s
N
RETURN TO INI TIALIZA TION
SEQUENCE (FIGURE 14) FOR
NEXT TRANSACTION
B4h
READ
POWER SUPPLY
?
Y
N
PARASITE
POWERED
?
N
MASTER
RX “1s”
MASTER
RX “0s”
Y
MASTER TX TH BYTE
TO SCRATCHPAD
Y
N
4Eh
WRITE
SCRATCHPAD
?
MASTER TX TL BYTE
TO SCRATCHPAD
Y
N
Y
BEh
READ
SCRATCHPAD
?
HAVE 8 BYTES
BEEN READ
?
N
MASTER
TX RESET
?
MASTER R
X
DATA BYTE
FROM SCRATCHPAD
N
Y
MASTER RX SCRATCHPAD
CRC BYTE
MASTER
RX “1s”
Y
N
B8h
RECALL E2
?
MASTER BEGINS DATA
RECALL FROM E2 PROM
DEVICE
BUSY RECALLING
DATA
?
N
Y
MASTER
RX “0s”