T6817-FP - Atmel Corporation

T6817

Preliminary Information

Rev. A2, 10-Jul-01 1 (14)

Dual Triple DMOS Output Driver with Serial Input Control

Description

The T6817 is a fully protected driver interface designed

in 0.8-µm BCDMOS technology. It is used to control up

to 6 different loads by a microcontroller in automotive

and industrial applications.

Each of the 3 high-side and 3 Low-side drivers is capable

to drive currents up to 600 mA. The drivers are freely con-

figurable and can be controlled separately from a standard

serial data interface. Therefore, all kinds of loads such as

bulbs, resistors, capacitors and inductors can be com-

bined. The IC design especially supports the applications

of H-bridges to drive DC motors.

Protection is guaranteed in terms of short-circuit condi-

tions, overtemperature, under- and overvoltage. Various

diagnosis functions and a very low quiescent current in

standby mode open a wide range of applications. Auto-

motive qualification referring to conducted interferences,

EMC protection and 2 kV ESD protection gives added

value and enhanced quality for the exacting requirements

of automotive applications.

Features

DThree high-side and three low-side drivers

DOutputs freely configurable as switch, half bridge or

H-bridge

DCapable to switch all kinds of loads such as DC

motors, bulbs, resistors, capacitors and inductors

D0.6 A continuous current per switch

DLow-side: RDSon < 1.5 Ω vs. total temperature range

DHigh-side: RDSon < 2.0 Ω vs. total temperature range

DVery low quiescent current Is < 20 µA in standby

mode

DOutputs short-circuit protected

DOvertemperature prewarning and protection

DUndervoltage and overvoltage protection

DVarious diagnosis functions such as s h o r t e d o u t p u t ,

o p e n l o a d, overtemperature and power supply fail

DSerial data interface

DDaisy chaining possible

DLoss of ground protection

DSSO20 package

Ordering Information

Extended Type Number Package Remarks

T6817-FP SSO20 Power package

T6817

Rev. A2, 10-Jul-01

Preliminary Information

2 (14)

Block Diagram

HS1HS2HS3

CLK

INH

OV–

protection

UV–

protection

VSVcc

Serial interface

Input Register

Output Register

Dn.

Fault

Detect

Fault

Detect Fault

Detect

GND

Fault

Detect Fault

Detect

LS1LS2LS3

Vcc

Thermal

protection

Osc

Control

logic

Vcc

P ower-on

Reset

u. n.

12 14 16

815 17

GND

Figure 1. Block diagram

T6817

Preliminary Information

Rev. A2, 10-Jul-01 3 (14)

Pin Description

1234567810

19 18 17 16 1415 13 12 1120

CLK INH VS VS LS3 n.c.

DI CS

LS1 HS1 LS2 HS2 GND HS3VCC DO

GND

T6817

Leadframe

Figure 2. Pinning

Pin Description

Pin Symbol Function

1 GND Ground; reference potential; internal connection to Pin 10, 1 1, 13 and 20; cooling tab

2 DI Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the

control device, DI expects a 16-bit control word with LSB being transferred first

3 CS Chip-select input; 5-V CMOS logic level input with internal pull-up;

low = serial communication is enabled, high = disabled

4 CLK Serial clock input; 5-V CMOS logic level input with internal pull down;

controls serial data input interface and internal shift register (fmax = 2 MHz)

5 INH Inhibit input; 5-V logic input with internal pull-down; low = standby,

high = normal operating

6, 7 VS Power supply output stages HS1, HS2 and HS3

8 LS3 Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by

active zenering; short-circuit protection; diagnosis for short and open load

9 n.c. Not connected

10 GND Ground, see Pin 1

11 GND Ground, see Pin 1

12 HS3 High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by

active zenering; short-circuit protection; diagnosis for short and open load

13 GND Ground, see Pin 1

14 HS2 High-side driver output 2; see Pin 12

15 LS2 Low-side driver output 2; see Pin 8

16 HS1 High-side driver output 1; see Pin 12

17 LS1 Low-side driver output 1; see Pin 8

18 DO Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit sta-

tus information to the mC (LSB is transferred first); output will remain tristated unless device is selected by

CS = low, therefore, several ICs can operate on one data output line only.

19 VCC Logic supply voltage (5 V)

20 GND Ground, see Pin 1

T6817

Rev. A2, 10-Jul-01

Preliminary Information

4 (14)

Functional Description

Serial Interface

SRR LS1 HS1 LS2 HS2 LS3 HS3 n.u. n.u. n.u. n.u. n.u. n.u. OLD SCT SI

CLK

DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 n.u. n.u. n.u. n.u. n.u. n.u. SCD INH PSF

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Figure 3 . Data transfer

Data transfer starts with the falling edge of the CS signal.

Data must appear at DI synchronized to CLK and are

accepted on the falling edge of the CLK signal. LSB

(bit 0, SRR) has to be transferred first. Execution of new

input data is enabled on the rising edge of the CS signal.

When CS is high, Pin DO is in tristate condition. This

output is enabled on the falling edge of CS. Output data

will change their state with the rising edge of CLK and

stay stable until the next rising edge of CLK appears. L S B

(bit 0, TP) is transferred first.

Input Data Protocol

Bit Input Register Function

0 SRR Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the

output data register are set to low)

1 LS1 Controls output LS1 (high = switch output LS1 on)

2 HS1 Controls output HS1 (high = switch output HS1 on)

3 LS2 See LS1

4 HS2 See HS1

5 LS3 See LS1

6 HS3 See HS1

7 n.u. Not used

8 n.u. Not used

9 n.u. Not used

10 n.u. Not used

11 n.u. Not used

12 n.u. Not used

13 OLD Open load detection (low = on)

14 SCT Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown

delay high / low = 100 ms / 12.5 ms, overvoltage shutdown delay high / low = 14 ms / 3.5 ms

15 SI Software inhibit; low = standby, high = normal operation

(data transfer is not af fected by standby function because the digitalpart is still powered)

After power-on reset, the input register has the following status:

T6817

Preliminary Information

Rev. A2, 10-Jul-01 5 (14)

Bit 15

(SI) Bit 14

(SCT) Bit 13

(OLD) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6

(HS3) Bit 5

(LS3) Bit 4

(HS2) Bit 3

(LS2) Bit 2

(HS1) Bit 1

(LS1) Bit 0

(SRR)

H H H n.u. n.u. n.u. n.u. n.u. n.u. L L L L L L L

Output Data Protocol

Bit Output (Status) Register Function

0 TP Temperature prewarning: high = warning (overtemperature shut down see remark below)

1Status LS1 Normal operation: high = output is on, low = output is off

Open-load detection: high = open load, low = no open load (correct load condition is detected

if the corresponding output is switched off)

2Status HS1 Normal operation: high = output is on, low = output is off

Open-load detection: high = open load, low = no open load (correct load condition is detected

if the corresponding output is switched off)

3Status LS2 Description see LS1

4Status HS2 Description see HS1

5Status LS3 Description see LS1

6Status HS3 Description see HS1

7 n.u. Not used

8 n.u. Not used

9 n.u. Not used

10 n.u. Not used

11 n.u. Not used

12 n.u. Not used

13 SCD Short circuit detected: set high, when at least one output is switched off by a short circuit

condition

14 INH Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit

(Pin 17). High = standby, low = normal operation

15 PSF Power supply fail: over- or undervoltage at Pin VS detected

Remark: Bit 0 to 15 = high: overtemperature shutdown

Power Supply Fail

In case of over- or undervoltage at Pin VS, an internal

timer is started. When the over- or undervoltage delay

time (tdOV/tdUV) programmed by the SCT bit is reached,

the power supply fail bit (PSF) in the output register is set

and all outputs are disabled. When normal voltage is pres-

ent again the outputs are enabled immediately. The PSF

bit remains high until it is reset by the SRR bit in the input

Open-Load Detection

If the open-load detection bit (OLD) is set to low, a

pull-up current for each high-side switch and a pull-down

current for each low-side switch is turned on (open-load

detection current IHS1–3, ILS1–3). If VVS–VHS1–3 or

VLS1–3 is lower than the open-load detection threshold

(open-load condition), the corresponding bit of the output

in the output register is set to high. Switching on an output

stage with OLD bit set to low disables the open-load

function for this output. If bit SI is set to low, the open-

load function is also switched off.

Overtemperature Protection

If the junction temperature exceeds the thermal

prewarning threshold, TjPW set, the temperature

prewarning bit (TP) in the output register is set. When the

temperature falls below the thermal prewarning

threshold, TjPW reset, the bit TP is reset. The TP bit can be

read without transferring a complete 16-bit data word:

with CS = high to low, the state of TP appears at Pin DO.

After the mC has read this information, CS is set high and

the data transfer is interrupted without affecting the state

of input and output registers.

If the junction temperature exceeds the thermal shutdown

threshold, Tj switch off, the outputs are disabled and all bits

in the output register are set high. The outputs can be

enabled again when the temperature falls below the

thermal shutdown threshold, Tj switch on, and when a high

has been written to the SRR bit in the input register.

T6817

Rev. A2, 10-Jul-01

Preliminary Information

6 (14)

Thermal prewarning and shutdown threshold have

hysteresis.

Short-Circuit Protection

The output currents are limited by a current regulator.

Current limitation takes place when the overcurrent

limitation and shutdown threshold (IHS1–3, ILS1–3) are

reached. Simultaneously, an internal timer is started. The

shorted output is disabled when during a permanent short

the delay time (tdSd) programmed by the short-circuit

timer bit (SCT) is reached. Additionally, the short-circuit

detection bit (SCD) is set. If the temperature prewarning

bit TP in the output register is set during a short, the

shorted output is disabled immediately and SCD bit is set.

By writing a high to the SRR bit in the input register, the

SCD bit is reset and the disabled outputs are enabled.

Inhibit

There are two ways to inhibit the T6817:

1. Set bit SI in the input register to zero

2. Switch Pin 5 (INH) to 0 V

In both cases, all output stages are turned off but the serial

interface stays active. The output stages can be activated

again by bit SI = 1 and by Pin 5 (INH) switched back to

5 V.

Absolute Maximum Ratings

All values refer to GND pins

Parameters Symbol Value Unit

Supply voltage Pins 6, 7 VVS – 0.3 to 40 V

Supply voltage tt0.5 s; ISu–2 A Pins 6, 7 VVS – 1 V

Supply voltage difference |VS_Pin6 – VS_Pin7|DVVS 150 mV

Supply current Pins 6, 7 IVS 1.4 A

Supply current t < 200 ms Pins 6,7 IVS 2.6 A

Logic supply voltage Pin 19 VVCC –0.3 to 7 V

Input voltage Pin 5 VINH –0.3 to 17 V

Logic input voltage Pins 2 to 4 VDI, VCS, VCLK –0.3 to VVCC + 0.3 V

Logic output voltage Pin 18 VDO –0.3 to VVCC + 0.3 V

Input current Pins 5, 2 to 4 IINH, IDI, ICS, ICLK –10 to +10 mA

Output current Pin 18 IDO –10 to +10 mA

Output current Pins 8, 12, 14 to 17 ILS1 to ILS3

IHS1 to IHS3

Internal limited, see

output specification

Reverse conducting current Pins 12, 14, 16,

(tPulse = 150 ms) towards Pins 6, 7 IHS1 to IHS3 17 A

Junction temperature range Tj–40 to 150 °C

Storage temperature range TSTG –55 to 150 °C

Operating Range

All values refer to GND pins

Parameters Test Conditions /

Pins Symbol Min. Typ. Max. Unit

Supply voltage Pins 6, 7 VVS VUV 1) 40 2) V

Logic supply voltage Pin 19 VVCC 4.5 5 5.5 V

Logic input voltage Pin 2 to 4 and 5 VINH, VDI, VCLK, VCS –0.3 VVCC V

Serial interface clock frequency Pin 4 fCLK 2 MHz

Junction temperature range Tj–40 150 °C

1) Threshold for undervoltage detection 2) Outputs disabled for VVS > VOV (threshold for overvoltage detection)

T6817

Preliminary Information

Rev. A2, 10-Jul-01 7 (14)

Thermal Resistance

All values refer to GND pins

Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit

Junction – pin Measured to GND

Pins 1, 10, 11, 13 and 20 RthJP 25 K/W

Junction ambient RthJA 65 K/W

Noise and Surge Immunity

Parameters Test Conditions Value

Conducted interferences ISO 7637-1 Level 4 1)

Interference Suppression VDE 0879 Part 2 Level 5

ESD (Human Body Model) ESD STM 5.1 – 1998 2 kV

ESD (Machine Model) JEDEC EIA / JESD 22 – A115-A 150 V

1) Test pulse 5: VSmax = 40 V

Electrical Characteristics

7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; –40°C < Tj < 150°C; unless otherwise specified,

all values refer to GND pins.

Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit

Current Consumption

Quiescent current (VS) VVSt16 V, INH or

bit SI = low Pins 6, 7 IVS 40 mA

Quiescent current (VCC) 4.5 VtVVCC t5.5 V,

INH or bit SI = low Pin 19 IVCC 20 mA

Supply current (VS) VVSt16 V normal operat-

ing, all output stages off,

Pins 6, 7

IVS 0.8 1.2 mA

Supply current (VS) VVS < 16 V normal operat-

ing, all output stages on, no

load Pins 6, 7

IVS 10 mA

Supply current (VCC) 4.5 V < VVCC < 5.5 V,

normal operating Pin 19 IVCC 150 mA

Internal Oscillator Frequency

Frequency (time-base for delay

timers) fOSC 19 45 kHz

Over- and Undervoltage Detection, Power-On Reset

Power-on reset threshold Pin 19 VVCC 3.4 3.9 4.4 V

Power-on reset delay time After switching on VVCC tdPor 30 95 160 ms

Undervoltage detection thresh-

old Pins 6, 7 VUV 5.5 7.0 V

T6817

Rev. A2, 10-Jul-01

Preliminary Information

8 (14)

Electrical Characteristics (continued)

7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; –40°C < Tj < 150°C; unless otherwise specified,

all values refer to GND pins.

UnitMax.Typ.Min.SymbolTest Conditions / PinsParameters

Undervoltage detection hyste-

resis Pins 6, 7 DVUV 0.4 V

Undervoltage detection delay tdUV 7 21 ms

Overvoltage detection threshold Pins 6, 7 VOV 18.0 22.5 V

Overvoltage detection hysteresis Pins 6, 7 DVOV 1 V

Overvoltage detection delay Input register

bit 14 (SCT) = high

bit 14 (SCT) = low tdOV

tdOV

1.75 21

5.25 ms

Thermal Prewarning and Shutdown

Thermal prewarning TjPWset 125 145 165 °C

Thermal prewarning TjPWreset 105 125 145 °C

Thermal prewarning hysteresis DTjPW 3 20 K

Thermal shutdown Tj switch off 150 170 190 °C

Thermal shutdown Tj switch on 130 150 170 °C

Thermal shutdown hysteresis DTj switch 3 20 K

Ratio thermal shutdown / ther-

mal prewarning Tj switch off/

TjPW set 1.05 1.17

Ratio thermal shutdown / ther-

mal prewarning Tj switch on/

TjPW reset 1.05 1.2

Output Specification (LS1 – LS3, HS1 – HS3) 7.5 V < VVS < VOV

On resistance IOut = 600 mA

Pins 8, 15 and 17 RDS OnL 1.5 W

On resistance IOut = –600 mA

Pins 12, 14 and 16 RDS OnH 2.0 W

Output clamping voltage ILS1–3 = 50 mA

Pins 8, 15 and 17 VLS1–340 60 V

Output leakage current VLS1-3 = 40 V

all output stages off

Pins 8, 15 and 17 ILS1-3 10 mA

Output leakage current VHS1–3 = 0 V

all output stages off

Pins 12, 14 and 16 IHS1-3 –10 mA

Inductive shutdown energy Pins 8, 12, 14 to 17 Woutx 15 mJ

Output voltage edge steepness Pins 8, 12, 14 to 17 dVLS1-3/dt

dVHS1-3/dt 50 200 400 mV/ms

Overcurrent limitation and shut-

down threshold Pins 8, 15 and 17 ILS1-3 650 950 1250 mA

T6817

Preliminary Information

Rev. A2, 10-Jul-01 9 (14)

Electrical Characteristics (continued)

7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; –40°C < Tj < 150°C; unless otherwise specified,

all values refer to GND pins.

UnitMax.Typ.Min.SymbolTest Conditions / PinsParameters

Overcurrent limitation and shut-

down threshold Pins 12, 14 and 16 IHS1-3 –1250 –950 –650 mA

Overcurrent shutdown delay

time Input register

bit 14 (SCT) = high

bit 14 (SCT) = low tdSd

tdSd

8.75 100

12.5 140

17.5 ms

Open load detection current Input register bit 13 (OLD)

=low, output off

Pins 8, 15 and 17

ILS1-3 60 200 mA

Open load detection current Input register bit 13 (OLD)

=low, output off

Pins 12, 14 and 16

IHS1-3 –150 –30 mA

Open load detection current ra-

tio ILS1-3 /

IHS1-3

1.2

Open load detection threshold Input register bit 13 (OLD)

=low, output off

Pins 8, 15 and 17

VLS1-3 0.6 4 V

Open load detection threshold Input register bit 13 (OLD)

=low, output off

Pins 12, 14 and 16

VVS-

VHS1-3

0.6 4 V

Output Switch on delay 1) RLoad = 1 kWtdon 0.5 ms

Output Switch off delay 1) RLoad = 1 kWtdoff 1 ms

Inhibit Input

Input voltage low level thresh-

old Pin 5 VIL 0.3

VVCC

Input voltage high level thresh-

old Pin 5 VIH 0.7

VVCC

Hysteresis of input voltage Pin 5 ∆VI100 700 mV

Pull-down current VINH = VVCC Pin 5 IPD 10 80 mA

Serial Interface – Logic Inputs DI, CLK, CS

Input voltage low level thresh-

old Pins 2–4VIL 0.3

VVCC

Input voltage high level thresh-

old Pins 2–4VIH 0.7

VVCC

Hysteresis of input voltage Pins 2–4∆VI50 500 mV

Pull-down current Pin DI, CLK VDI, VCLK = VVCC

Pins 2 and 4 IPDSI 2 50 mA

Pull-up current Pin CS VCS= 0 V Pin 3 IPUSI –50 –2mA

1) Delay time between rising edge of CS after data transmision and switch on/off output stages to 90% of final level

T6817

Rev. A2, 10-Jul-01

Preliminary Information

10 (14)

Electrical Characteristics (continued)

7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; –40°C < Tj < 150°C; unless otherwise specified,

all values refer to GND pins.

Parameter Test Conditions / Pins Symbol Min. Typ. Max. Unit

Serial Interface – Logic Output DO

Output voltage low level IOL = 3 mA Pin 18 VDOL 0.5 V

Output voltage high level IOL = –2 mA Pin 18 VDOH VVCC–1V V

Leakage current

(tristate) VCS = VVCC, 0 VtVDOtVVCC

Pin 18 IDO –10 10 mA

Parameters Test

Conditions Timing

Chart No. Symbol Min. Typ. Max. Unit

Serial Interface – timing

DO enable after CS falling edge CDO = 100 pF 1 tENDO 200 ns

DO disable after CS rising edge CDO = 100 pF 2 tDISDO 200 ns

DO fall time CDO = 100 pF –tDOf 100 ns

DO rise time CDO = 100 pF –tDOr 100 ns

DO valid time CDO = 100 pF 10 tDOVal 200 ns

CS setup time 4 tCSSethl 225 ns

CS setup time 8 tCSSetlh 225 ns

CS high time Input register

Bit 14 (SCT) =

high

9 tCSh 140 ms

CS high time Input register

Bit 14 (SCT) =

low

9 tCSh 17.5 ms

CLK high time 5 tCLKh 225 ns

CLK low time 6 tCLKl 225 ns

CLK period time –tCLKp 500 ns

CLK setup time 7 tCLKSethl 225 ns

CLK setup time 3 tCLKSetlh 225 ns

DI setup time 11 tDIset 40 ns

DI hold time 12 tDIHold 40 ns

T6817

Preliminary Information

Rev. A2, 10-Jul-01 11 (14)

1 2

CLK

10 12

Inputs DI, CLK, CS: High level = 0.7 × VCC, Low level = 0.3 × VCC

Output DO: High level = 0.8 × VCC, Low level = 0.2 × VCC

Figure 4. Serial interface timing diagram with chart numbers

T6817

Rev. A2, 10-Jul-01

Preliminary Information

12 (14)

Application Circuit

BATT

13V

U5021M

WATCHDOG

Vcc

Reset

Trigger

Enable

Vcc

BYT41D

HS1HS2HS3

CLK

INH

OV–

protection

UV–

protection

VS Vcc

Serial interface

Input Register

Output Register

Dn.

Fault

Detect

Fault

Detect Fault

Detect

GND

Fault

Detect Fault

Detect

LS1LS2LS3

Vcc

Thermal

protection

Osc

Control

logic

Vcc

P ower-on

Reset

u. n.

12 14 16

81517

GND

Figure 5. Application circuit

Application Notes

It is strongly recommended to connect the blocking

capacitors at V CC and VS as close as possible to the power

supply and GND pins.

Recommended value for capacitors at VS:

electrolythic capacitor C > 22 µF in parallel with a

ceramic capacitor C = 100 nF. Value for electrolytic

capacitor depends on external loads, conducted interfer-

ences and reverse conducting current IHSX (see: Absolut

Maximum Ratings).

Recommended value for capacitors at VCC:

electrolythic capacitor C > 10 µF in parallel with a

ceramic capacitor C = 100 nF.

To reduce thermal resistance it is recommended to place

cooling areas on the PCB as close as possible to GND

pins.

T6817

Preliminary Information

Rev. A2, 10-Jul-01 13 (14)

Package Information

technical drawings

according to DIN

specifications

Package SSO20

Dimensions in mm 6.75

6.50

0.25

0.65 5.85

1.30

0.15

0.05

5.7

5.3

4.5

4.3

6.6

6.3

0.15

20 11

110

T6817

Rev. A2, 10-Jul-01

Preliminary Information

14 (14)

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