ZL30165 Quad Clock Translator Data Sheet March 2015 Features * Four independent clock channels * Four programmable digital PLLs/Numerically Controlled Oscillators (NCOs) * Programmable synthesizers generate any clockrate from 1 kHz to 750 MHz * Four precision synthesizers generate clocks with low jitter of 0.63 ps RMS for 10 G PHYs * * Ordering Information ZL30165GDG2 144 Pin LBGA Trays Pb Free Tin/Silver/Copper -40oC to +85oC Package Size: 13 x 13 mm * Eight LVPECL outputs and eight LVCMOS outputs * Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz Operates from a single crystal resonator or clock oscillator * Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates Customer defined default device configuration available via OTP (One Time Programmable) memory, including input/output frequencies * Dynamically configurable via SPI/I2C interface and volatile configuration registers * Digital PLLs filter jitter at 5.2 Hz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz * Automatic hitless reference switching and digital holdover on reference fail * Eight reference inputs configurable as single ended or differential 1 Microsemi Corporation Copyright 2015, Microsemi Corporation. All Rights Reserved. ZL30165 Applications * OTN muxponders and transponders * 10 Gigabit line cards * Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W * SONET/SDH, Fibre Channel, XAUI 2 Zarlink Semiconductor Inc. Data Sheet ZL30165 Data Sheet Change History Below are the changes from the February 2014 issue to the March 2015 issue: Page Item Change 1 Added Features Bullet Included availability of customer defined default configurations 11 GPIO pin description Updated GPIO[5:6] power-up settings 17 Precise Frequency Monitor (PFM) Clarified the PFM measurement interval 18 Guard Soak Timer (GST) Corrected the GST description 31 Figure 14 "Typical Power-Up Reset and Configuration Circuit" Updated GPIO[5:6] power-up settings 32 5.1, "ZL30165 Configuration programming" Added section 5.1 85 Register Name: phasemem_limit_ref0 Corrected the 1ms phase memory limit example in the register description. 118 Register Name: dpll0_df_offset Corrected the f_out equation in the register description. 162 13.0, "Package Markings" Added section 13.0 for package markings Below are the changes from the January 2014 issue to the February 2014 issue: Page Item Change 21 Frequency Synthesizer Added paragraph to match note 2 from 0x1BA:0x1BB register description 50 Register Map Added Basic Procedure for Refreshing Latest Device Status from Sticky Read (StickyR) Registers when using an Interrupt Handler (event or polling) 138 Quadrature Phase Shift Added a note to the register description for the quadrature phase shift. Below are the changes from the December 2013 issue to the January 2014 issue: Page Item Change 1 Document status Moved from preliminary to released Below are the changes from the October 2013 issue to the December 2013 issue: Page Item Change 154 AC Electrical Characteristics* - Input To Output Timing (see Figure 27 and Figure 28) Update input frequency to output delay for differental signals Below are the changes from the September 2013 issue to the October 2013 issue: Below are the changes from the April 2013 issue to the September 2013 issue: 3 Microsemi Corporation ZL30165 Data Sheet Page Item Change 51 Register Summary: chip_revision Updated default value 60 Register Summary: dpll0_fast_lock_ctrl Updated default value 60 Register Summary: dpll1_fast_lock_ctrl Updated default value 60 Register Summary: dpll2_fast_lock_ctrl Updated default value 60 Register Summary: dpll3_fast_lock_ctrl Updated default value 62 Register Name: chip_revision Updated default value 146 Register Name: dpll0_fast_lock_ctrl Updated default value 146 Register Name: dpll1_fast_lock_ctrl Updated default value 147 Register Name: dpll2_fast_lock_ctrl Updated default value 147 Register Name: dpll3_fast_lock_ctrl Updated default value Page Item Change 17 Precise Frequency Monitor (PFM) Added note about non-integer frequencies 49 Basic Procedure for Refreshing Latest Device Status from Sticky Read (StickyR) Registers without Interrupt Handler Updated heading title 83 Register Name: pfm_limit_ref1_0 Added note about non-integer frequencies 123 Register Name: synth0_freq_multiple Added note 159 Section 10.1, "Output Clocks Jitter Generation" Updated table titles Below are the changes from the March 2013 issue to the April 2013 issue: Page Item Change 20 Section 4.3.2, "DPLL States" Updated descriptive text 22 Section 4.5, "Dividers and Skew Management" Updated coarse phase adjustment range in descriptive text 32 Section 5.0, "Configuration and Control" Updated descriptive text 63 Register Name: central_freq_offset Added note 3 64 Register Name: Spurs_supression Added note 99 Register Name: dpll0_mode_refsel Updated descriptive text in register description 150 DC Electrical Characteristics - Power - Core Update power consumption 151 DC Electrical Characteristics - Power - Clock Outputs Update power consumption per output 152 DC Electrical Characteristics - High Performance Outputs Update table notes for clarity 4 Microsemi Corporation ZL30165 Data Sheet Table of Contents 1.0 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.0 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Input Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Input Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 Digital Phase Locked Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 DPLL General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.2 DPLL States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.3 DPLL Rate Conversion Function and FEC Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.4 DPLL Input to Output and Output to Output Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 Dividers and Skew Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 Output Clocks Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 Input Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.9 Master Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.9.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10 Power Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.11 Power Supply Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.12 Reset and Configuration Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.0 Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 ZL30165 Configuration programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.1 Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.2 Custom OTP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.3 SPI/I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Registers Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.1 Input Reference Configuration and Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.2 DPLL Configuration and Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.3 Output Multiplexer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.4 Synthesizer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.5 Output Dividers and Output Phase Offset (skew) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.6 Output Drivers Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 GPIO Indication and Control Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4 State Control and Reference Switch Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4.1 Un-managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4.2 Managed (Manual) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.0 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.1 Least Significant Bit (LSb) First Transmission Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.2 Most Significant Bit (MSb) First Transmission Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.3 SPI Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.4 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.0 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.1 Output Clocks Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.2 DPLL Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.0 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5 Microsemi Corporation ZL30165 Data Sheet 12.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.0 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 13.1 144-pin BGA. Package Top Mark Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6 Zarlink Semiconductor Inc. ZL30165 Data Sheet List of Figures Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3 - Application Diagram: Frequency Generation for OTN Client Clock Generation . . . . . . . . . . . . . . . . . . 16 Figure 4 - Output Clocks Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5 - Terminating LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6 - Terminating AC coupled LVPECL outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7 - Terminating LVCMOS outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8 - Differential DC Coupled LVPECL Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 9 - Differential AC Coupled LVPECL Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10 - Differential DC Coupled LVDS Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11 - Differential AC Coupled LVDS Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12 - Single Ended CMOS Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 13 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 14 - Typical Power-Up Reset and Configuration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 15 - Serial Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 16 - Serial Peripheral Interface Functional Waveforms - LSb First Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 17 - Serial Peripheral Interface Functional Waveforms - MSb First Mode . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 18 - Example of a Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 19 - I2C Data Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 20 - I2C Data Read Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 21 - I2C 7-bit Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 22 - I2C Data Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 23 - I2C Data Read Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 24 - Accessing Multi-byte Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 25 - Timing Parameter - Output Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 26 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 27 - Input To Output Timing for hpoutclk0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 28 - Input To Output Timing To hpdiff0_P/N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 29 - Output Timing Referenced To hpclkout0/clkout0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 30 - Serial Peripheral Interface Timing - LSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 31 - Serial Peripheral Interface Timing - MSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 32 - I2C Serial Microport Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 33 - Non-customized Device Top Mark. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Figure 34 - Custom Factory Programmed Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7 Microsemi Corporation ZL30165 Data Sheet List of Tables Table 1 - Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2 - Frequency Out of Range Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3 - DPLL Phase Slope Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4 - Master Clock Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5 - Custom Configuration power-up settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 6 - Serial Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 7 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 8 - Serial Peripheral Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 9 - I2C Serial Microport Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 10 - Jitter Generation Specifications - LVPECL Differential (HPDIFF) Outputs . . . . . . . . . . . . . . . . . . . . . 159 Table 11 - Jitter Generation Specifications - LVCMOS Single-ended (HPOUT) Outputs . . . . . . . . . . . . . . . . . . 159 Table 12 - DPLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 13 - Thermal Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 14 - Package Marking Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8 Microsemi Corporation ZL30165 1.0 Data Sheet Pin Diagram TOP VIEW 1 2 3 4 hpdiff0_p VDD0 NC VDD1 hpdiff0_n VSS NC hpdiff1_p hpdiff1_n VDD7 1 5 6 7 8 osco_1V8 VDD2 osco_3V3 osci_3V3 VSS osci_1V8 VSS XOin VDD5 VSS VSS VCORE1 VSS hpoutclk0 hpoutclk1 VSS VDD9 VDD10 VSS 9 10 11 VDD3 NC VDD4 VCORE0 VSS NC VSS VSS VSS VSS VDD6 VSS VSS VSS hpoutclk3 hpoutclk2 VSS VDD8 VSS VSS VSS VSS VSS VDD11 IC1 NC 12 A hpdiff2_p B hpdiff2_n C hpdiff3_n hpdiff3_p D E NC F NC trst_b hpoutclk4 hpoutclk5 VSS VSS VSS VSS hpoutclk6 hpoutclk7 pwr_b NC tdi tdo tms VSS VSS VSS VSS VSS VDD12 gpio1 gpio0 IC2 hpdiff4_p hpdiff4_n tck VSS VSS VSS VSS VSS VCORE2 gpio2 hpdiff6_n hpdiff6_p VSS gpio4 VSS VSS VSS VSS VSS VCORE3 gpio3 VSS hpdiff5_n gpio5 gpio6 VSS VCORE4 cs_b_asel0 sck_scl si_sda so_asel1 hpdiff7_n hpdiff7_p G H J VDD13 VDD14 K hpdiff5_p L VDD15 VSS ref1_p ref1_n ref3_p ref3_n ref5_p ref5_n ref6_n NC NC NC VCORE5 VSS ref0_p ref0_n ref2_p ref2_n ref4_p ref4_n ref6_p ref7_p ref7_n NC M 1 - A1 corner is identified by metallized markings. Figure 2 - Package Description 9 Microsemi Corporation ZL30165 2.0 Data Sheet Pin Description All device inputs and outputs are LVCMOS unless specifically stated to be differential.For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O). Ball # Name I/O Description ref0_p ref0_n ref1_p ref1_n ref2_p ref2_n ref3_p ref3_n ref4_p ref4_n ref5_p ref5_n ref6_p ref6_n ref7_p ref7_n I Input References 0 to 7. Input reference sources used for synchronization. The positive and negative pair of these inputs accepts a differential input signal. The refx_p input terminal accept a CMOS input reference. D3 D4 D10 D9 F3 F4 F9 F10 hpoutclk0 hpoutclk1 hpoutclk2 hpoutclk3 hpoutclk4 hpoutclk5 hpoutclk6 hpoutclk7 O A1 B1 C1 C2 A12 B12 C12 C11 H1 H2 K1 K2 H12 H11 K12 K11 hpdiff0_p hpdiff0_n hpdiff1_p hpdiff1_n hpdiff2_p hpdiff2_n hpdiff3_p hpdiff3_n hpdiff4_p hpdiff4_n hpdiff5_p hpdiff5_n hpdiff6_p hpdiff6_n hpdiff7_p hpdiff7_n O Input Reference M3 M4 L3 L4 M5 M6 L5 L6 M7 M8 L7 L8 M9 L9 M10 M11 Maximum frequency limit on single ended inputs is 177.5 MHz, and 750 MHz on differential inputs. Output Clocks High Performance Output Clocks 0 to 7. These outputs can be configured to provide any one of the single ended high performance clock outputs. Maximum frequency limit on single ended LVCMOS outputs is 177.5 MHz. High Performance Differential Output Clocks 0 to 7 (LVPECL). These outputs can be configured to provide any one of the available high performance differential output clocks. Maximum frequency limit on differential outputs is 750 MHz. Table 1 - Pin Description 10 Microsemi Corporation ZL30165 Ball # Name Data Sheet I/O Description Control and Status F11 pwr_b I Power-on Reset. A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. The pwr_b pin should be held low for 2 ms after all power supplies are stabilized. This pin is internally pulled-up to VDD. User can access device registers either 125 ms after pwr_b goes high, or after bit 7 in register at address 0x000 goes high (which can be determined by polling). G11 G10 H10 J10 J3 K3 K4 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 I/O General Purpose Input and Output pins. These are general purpose I/O pins. Available GPIO functions include: * DPLL lock indicators * DPLL holdover indicators * Reference fail indicators * Reference select control or monitor * Differential output clock enable * High performance LVCMOS outputs enable * Host Interrupt Output to flag status changes. Pins 5:0 are internally pulled down to GND and pin 6 is internally pulled up to VDD. Unused GPIO pins can be left unconnected. After power on reset, device GPIO[0,1,3,4] configure basic device function. GPIO3 sets I2C or SPI control mode, GPIO[1,0] sets master clock rate selection. The GPIO[0,1,3] pins must be either pulled low or high with an external 1 kohms resistor for their assigned functions at reset; or they must be driven low or high for 125 ms after reset, and released and then used for normal GPIO functions. The GPIO4 pin must be either pulled low with an external 1 kohms resistor or it must be driven low for 125 ms after reset. It then can released and used for normal GPIO functions. GPIO[5,6] are not used during power up for generic devices. For custom configured devices they select one of the four OTP configurations stored in the device and must be either pulled low or high with an external 1kohm resistor; or driven low or high for 125ms after reset, then released and used for normal GPIO functions. Host Interface K8 sck_scl I/O Clock for Serial Interface. Provides clock for serial micro-port interface. This pin is also the serial clock line (SCL) when the host interface is configured for I2C mode. As an input this pin is internally pulled up to VDD. K9 si_sda I/O Serial Interface Input. The serial input data stream holds the access command, the address and the write data bits. This pin is also the serial data line (SDA) when host interface is configured for I2C mode. This pin is internally pulled up to VDD. Table 1 - Pin Description (continued) 11 Microsemi Corporation ZL30165 Data Sheet Ball # Name I/O Description K10 so_asel1 I/O Serial Interface Output. Serial interface output stream. As an output the serial stream holds the read data bits. This pin is also part of the I2C address when host interface is configured for I2C mode. K7 cs_b_asel0 I Chip Select for Serial Interface. Serial interface chip select, this is an active low signal. This pin is also part of the I2C address when host interface is configured for I2C mode.This pin is internally pulled up to VDD. I Internal Connection. Connect this pin to GND. JTAG (IEEE 1149.1) and Test G12 IC2 E11 IC1 G2 tdo O Test Serial Data Out. JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. G1 tdi I Test Serial Data In. JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. F2 trst_b I Test Reset. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be held low or pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. H3 tck I Test Clock. Provides the clock for the JTAG test logic. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. G3 tms I Test Mode Select. JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. A-I/O Internal Connection. Leave unconnected. Master Clock Note: The osci_1V8/osco_1V8 pins are preferred to connect a crystal to the device. The XOin pin is preferred to connect a crystal oscillator (XO) to the device. A7 osco_3V3 A8 osci_3V3 A5 osco_1V8 A-O 3.3V Crystal Master Clock Output. For the alternative connection method for a crystal, the crystal is connected from this pin to osci_3V3. Not suitable for driving other devices. For clock oscillator operation or the use of a crystal between osci_1V8 and osco_1V8, this pin should be left unconnected. I 3.3V Crystal Master Clock Input. For the alternative connection method for a crystal, the crystal is connected from this pin to osco_3V3. For clock oscillator operation or the use of a crystal between osci_1V8 and osco_1V8, this pin should be grounded. A-O 1.8V Crystal Master Clock Output. For the primary connection method for a crystal, the crystal is connected from this pin to osci_1V8. Not suitable for driving other devices. For clock oscillator operation or the use of a crystal between osci_3V3 and osco_3V3, this pin should be left unconnected. Table 1 - Pin Description (continued) 12 Microsemi Corporation ZL30165 Data Sheet Ball # Name I/O Description B5 osci_1V8 I 1.8V Crystal Master Clock Input. For the primary connection method for a crystal, the crystal is connected from this pin to osco_1V8. For clock oscillator operation or the use of a crystal between osci_3V3 and osco_3V3, this pin should be grounded. B7 XOin I XO Master Clock Output. For clock oscillator operation, this pin is connected to the output of the oscillator. For crystal operation using either method, this pin should be grounded. Power and Ground B8 C6 H9 J9 K6 M1 VCORE0 VCORE1 VCORE2 VCORE3 VCORE4 VCORE5 Positive Supply Voltage. +1.8VDC nominal. A2 A4 A6 A9 A11 C3 C10 D1 D12 E2 E3 E10 G9 J1 J12 L1 VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 Positive Supply Voltage. +3.3VDC nominal. These pins should not be connected together on the board. Please refer to ZLAN-327 for recommendations. These pins should not be connected together on the board. Please refer to ZLAN-327 for recommendations. Table 1 - Pin Description (continued) 13 Microsemi Corporation ZL30165 Ball # Name B2 B4 B6 B9 B11 C4 C5 C7 C8 C9 D2 D11 E4 E9 G4 H4 H5 H6 H7 H8 J2 J4 J5 J6 J7 J8 J11 K5 L2 M2 D5 D6 D7 D8 E5 E6 E7 E8 F5 F6 F7 F8 G5 G6 G7 G8 VSS I/O Data Sheet Description Ground. 0 Volts. Table 1 - Pin Description (continued) 14 Microsemi Corporation ZL30165 Ball # Name I/O Data Sheet Description No connection A3 A10 B3 B10 E1 E12 F1 F12 L10 L11 L12 M12 NC No Connection. These pins should be left open. Table 1 - Pin Description (continued) 15 Microsemi Corporation ZL30165 3.0 Data Sheet Application Example Optical Transport Network (OTN) Transponders and Muxponders require de-synchronizers (PLLs) to filter gapped clock jitter introduced in demapping process. Figure 3 shows a typical OTN Muxponder with four different clients: SONET/SDH, Ethernet, Fiber Channel and Digital Video. ZL30165 has four independent desynchronizers capable of locking and generating any frequency between 1 kHz and 750 MHz. Hence, ZL30165 can handle any OTN client rate. In addition, an additional ZL30165 could be used to generate a free-running master clock for the OTN Transmit line. Figure 3 - Application Diagram: Frequency Generation for OTN Client Clock Generation 16 Microsemi Corporation ZL30165 4.0 Data Sheet Functional Description The functional block diagram of the device is shown in Figure 1 with its detailed operation is described in the following sections. 4.1 Input Sources The device has nine input sources: eight input references (single ended or differential) and one master clock source (oscillator or crystal). The device master clock frequency is configured on reset via external voltage levels on GPIO[1:0] pins. The recommended frequency of the master clock is 49.152 MHz. The device synchronizes (locks) to any input reference which is a 1 kHz multiple, or it synchronizes (locks) to any input reference which is an M/N x 1 kHz multiple (FEC rate) where M and N are 16 bits wide. The device input reference frequency is programmed during initialization, which can be changed during operation by setting the DPLL into the holdover mode before a frequency change. The device accepts an input reference with a maximum frequency of 177.5 MHz through single ended LVCMOS input or 750 MHz frequency through differential inputs. If the frequency of an input reference exceeds 400 MHz, the reference must be divided by 2 before being fed to DPLL (Refer to ref_pre_divide registers). 4.2 Input Reference Monitoring The input references are monitored by reference monitor indicators which are independent for each reference. They indicate abnormal behavior of the reference signal, for example; drift from its nominal frequency or excessive jitter. Loss of Signal Monitor (LOS) LOS is an external signal, fed to one of ZL30165 GPIO pins. LOS is typically generated by a PHY device whose recovered clock is fed to one of the reference inputs. The PHY device will generate a LOS signal when it cannot reliably extract the clock from the line. The user can set one of GPIO pins as a LOS input by programming corresponding GPIO register. Coarse Frequency Monitor (CFM) The CFM monitors the input reference frequency for 1.25 ms so that it can quickly detect large changes in frequency. CFM limit for each input reference can be selected in corresponding scm_cfm_limit_ref registers with range from 0.1% to 50%. If the CFM limit is exceeded, then CFM failure is declared for corresponding reference. For frequencies below 16 kHz, the CFM and SCM limits should be set to the same value for proper operation. Precise Frequency Monitor (PFM) The PFM block measures the frequency accuracy of the reference over a 10 second interval, the indicator bit is updated every second. The PFM provides a level of hysteresis to prevent a failure indication from toggling between valid and invalid for input references that are on the edge of the acceptance range. PFM limit for each reference can be selected in the pfm_limit_ref registers. When determining the frequency accuracy of the reference input, the PFM uses the external master clock oscillator's frequency as its reference. PFM supports any reference (input) frequency from 1 Hz to 750 MHz except for non integer (in Hz) frequencies below 5,000,000 Hz. For example 1 Hz, 8 kHz, 2.048 MHz, 156.25*66/64 MHz are supported frequencies but 0.5 Hz and 1.5 Hz are not supported. The PFM limit should be set based on the following table in pfm_limit_ref registers: 17 Microsemi Corporation ZL30165 Data Sheet Value Acceptance Range Rejection Range Typical Application 000 +/- 9.2 ppm +/- 12 ppm Stratum 3, G.813 option 1, G.8262 EEC 1 & 2 100 +/- 13.8 ppm +/- 18 ppm 101 +/- 24.6 ppm +/- 32 ppm 110 +/- 36.6 ppm +/- 47.5 ppm 001 +/- 40 ppm +/- 52 ppm 111 +/- 52 ppm +/- 67.5 ppm 010 +/- 64 ppm +/- 83 ppm Stratum 4, G.824 011 +/- 100 ppm +/- 130 ppm G.823 SONET Minimum Clock, G.813 option 2 Table 2 - Frequency Out of Range Limits Single Cycle Monitor (SCM) This detector measures the rising to rising edge and falling to falling edge periods of the input reference. If either exceeds the predefined SCM limit then a SCM failure is declared. The SCM limit for each input reference can be selected in the corresponding scm_cfm_limit_ref registers with range from 0.1% to 50%. The limits are input frequency dependent. Please refer to the description in scm_cfm_limit_ref registers. For frequencies below 16 kHz, the CFM and SCM limits should be set to the same value for proper operation. For frequencies above 400 MHz, SCM (and the GST) should not be used. Guard Soak Timer (GST) When selected, the guard soak timer adds extra time to qualify and disqualify a reference. The default time to wait to disqualify a reference is 50 ms after a CFM and SCM failure is detected. When qualifying a reference, the time starts when the CFM or SCM failure is cleared. The default qualification time is 4 times the disqualification time A PFM failure does not effect this timer. For frequencies above 400 MHz, the GST should not be used because the single cycle monitor (SCM) will never be valid. Holdover and Reference Switching Masks These bit fields control which of the reference monitoring signals on the selected reference are used to trigger a reference switch or transition to holdover. The dplln_ref_fail_mask and dplln_pfm_fail_mask fields control the action taken when any of the reference monitoring signals is triggered. Please note that the GST mask bit should not be enabled without either the SCM or the CFM bit for either reference switching or holdover. Also, the holdover mask has higher priority than the reference switching mask when both have the same signal unmasked. For return from holdover, the mask refers to the highest priority reference and will prevent the start of transition to lock mode if the indicated conditions are active. 4.3 Digital Phase Locked Loop (DPLL) The device supports four independent digital PLL modules. All four DPLLs are enabled by default. Each DPLL can be enabled/disabled through the host registers. With four DPLLs, the device can synchronize to four independent reference clocks. 4.3.1 DPLL General Characteristics 18 Microsemi Corporation ZL30165 Data Sheet Pull-in Hold-in range The DPLL supports pull-in/hold-in of +/-12 ppm, +/-52 ppm, +/-83 ppm,+/-130 ppm, +/-400 ppm or unlimited. DPLL bandwidth (jitter/wander transfer) The DPLL supports the following first order filtering cut-off frequencies: 5.2 Hz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz and 896 Hz. The DPLL bandwidth is typically determined during the initialization. When changing the bandwidth dynamically, it is recommended to put the DPLL in Holdover mode first and then change the bandwidth. After the bandwidth has been changed, the DPLL is then set back to the Normal mode. For the line card bandwidths in the ZL30165 (5.2 Hz and above), it is recommended that the fast lock mode be enabled when phase slope limiting is used. It should be disabled with an unlimited PSL. This can be done in the dplln_fast_lock_ctrl register. The DPLL locks to an input reference and provides a stable low jitter output clock when the selected loop bandwidth is less than 1/30th the input reference frequency. As an example, a 19.44 MHz reference could use a bandwidth up to 896 Hz, and a 1 kHz input reference could be used a loop bandwidth of up to 14 Hz. For 8 kHz reference the recommended maximum loop bandwidth is 56 Hz. Jitter/Wander Generation Jitter and wander generation performances are provided in section 10.0, "Performance Characterization". Phase Transients and Phase Slope Lmiting When a reference switch occurs with phase tracking active (i.e., TIE clear disabled or hitless reference switching), the DPLL transitions the phase of the output smoothly, limited by the selected loop bandwidth and by the selected phase slope limit. The device offers the following selectable phase slope limiting options: 61 usec/sec, 7.5 usec/sec, 0.885 usec/sec or unlimited. If the required phase slope limit is 0.885 usec/sec or 7.5 usec/sec, the user should first set the device to unlimited phase slope and wait for PLL to achieve lock before changing it to desired phase slope limit The phase slope limit is set in register dpllX_ctrl as shown in Table 3. dpll_phase_slope_limit Phase Slope Limiting Application 00 61 s/s GR-1244 Stratum 3 01 7.5 s/s G.813 option 1 10 885 ns/s GR-1244 Stratum 3 (objective) 11 Unlimited Default setting Table 3 - DPLL Phase Slope Limiting Note: Under certain configurations, the output of the DPLL may exceed these phase slope limit values. This depends on the input transient (phase or frequency) and the bandwidth of the DPLL. Holdover Stability DPLL initial holdover accuracy is better than 50 ppb for a jittered input and better than 10 ppb for a jitter-free input. Input Tolerance Criteria Input tolerance indicates that the device tolerates certain jitter, wander and phase transients at its input reference while maintaining outputs within an expected performance and without experiencing any alarms, reference switching or holdover conditions. Input tolerance is associated with input reference source characteristics and the standards associated with input reference type. 19 Microsemi Corporation ZL30165 Data Sheet DPLL Monitoring The DPLL provides lock and holdover indicators using the default lock indicator conditions. The lock time is dependent on employed loop bandwidth. The device has a lock time of less than 2 sec for all available DPLL loop bandwidth selections with phase slope limit set to unlimited. For more information, please refer to Section 10.2. 4.3.2 DPLL States The DPLL in the device support five modes: free-run, forced holdover, automatic, forced reference lock and numerically controlled oscillator (NCO). To lock the DPLL to a reference, automatic or forced reference mode should be used. In each of the locked modes, there are three states: acquiring, normal (locked) and holdover. (The acquiring state is temporary between the availability of a reference and the completion of the locking process.) In the automatic mode, the DPLL may go between the states depending on the availability of all the references (with a priority above "never lock"). In forced reference mode, the device will go into holdover if the reference selected is unavailable even if other references are available. The availability of a reference is determined by the reference qualification process. In the holdover state, the device provides output clocks which are not locked to an external reference signal, but are based on an estimate of the frequency during the previous time in the locked state. To force the DPLL into the holdover state even with good references present, the forced holdover mode is used. In addition, the DPLL can be put into the free-run mode. This is used when the synchronization to a reference is not required or is not possible. Typically, this is used immediately following system power-up. In the free-run mode, the device provides timing and synchronization signals which are based on the master clock frequency only, and are not synchronized to the reference input signals. The free-run accuracy of the output clock is equal to the accuracy of the master clock. So if a 20 ppm free-run output clock is required, the master clock must also be 20 ppm. The freerun mode: * The DPLL has to generate all its output clocks based only on the device master clock input. * The DPLL will not lock or switch to a reference or go into holdover. * The reference switch mask and the reference holdover mask are ignored. The forced holdover mode: * All references are ignored and the DPLL has to go to holdover (based on last selected reference) * The reference switch mask and the reference holdover mask are ignored. The forced reference lock mode: * The DPLL will try to lock to the host-specified reference. * The reference switch mask is ignored. No reference switching will be performed. * If the holdover mask is set, then the device will switch to holdover if the selected reference fails. * If the holdover mask is not set, then the device will attempt to lock to the selected reference, even if it is failing one of the reference monitors. The automatic mode: * Reference selection and holdover is automatically handled by the device, based on the holdover and reference switch masks, and the reference priority. * If the reference switch mask is set, then reference will be selected based on availability and priority. If all enabled references are bad, then the device will enter holdover. * If holdover mask is set (and ref. switch mask cleared), then device switches to holdover on ref failure. * If neither ref switch nor holdover mask are set, then device will keep trying to lock to a failed ref. The NCO mode: 20 Microsemi Corporation ZL30165 * Data Sheet The DPLL is run in free-run mode. The output clock is the requested synthesizer frequency with an offset specified by the dpll_df_offset register. This write-only register will change the output frequency of the DPLL. 4.3.3 DPLL Rate Conversion Function and FEC Support The DPLL provides up scaling and down scaling functions. It has the ability to switch from normal rate (before FEC is negotiated) to FEC rate and vice versa. The DPLL supports: * Simple rate conversion (i.e., take in 19.44 MHz and create 255/238 FEC SONET/SDH clock of 666.51 MHz), * Double rate conversion (i.e., take in 19.44 MHz, create FEC 10 GbE clock of 644.5313, which is 66/64 rate converted 625 MHz, or create 690.5692 which is 255/238 x 66/64 rate converted 625 MHz) The following is just an example of the frequencies that can be supported at the input and output independently (many more frequencies can be supported): * * GbE: * 25 MHz * 125 MHz XAUI (chip to chip interface, which is a common chassis to chassis interface): * * * 156.25 MHz or x2 or x4 version OC-192/STM-64: * 155.52 MHz or x2 or x4 version * 155.52 MHz x 255/237 (standard EFEC for long reach) or x2 or x4 version * 155.52 MHz x 255/238 (standard GFEC for long reach) or x2 or x4 version 10 GbE: * 156.25 MHz which is 125 MHz x 10/8 or x2 or x4 version * 155.52 MHz x 66/64 or x2 or x4 version * Long reach 10 GE might require the following frequencies with simple rate conversion: (156.25 MHz x 255/237) and (156.25 MHz x 255/238). * The following frequencies with double rate conversion: (155.52 MHz x 66/64 x 255/237) or (155.52 MHz x 66/64 x 255/238) and (156.25 MHz x 66/64 x 255/238) or (156.25 MHz x 66/64 x 255/238). Also, user can use x2 or x4 version of the listed frequencies. Application Note ZLAN-447 explains how to generate the most common frequencies. 4.3.4 DPLL Input to Output and Output to Output Phase Alignment Techniques offered for Phase Alignment When the output clock is locked to a jitter free and wander free input clock, input to output latency is expected to have a typical error of 0 nsec. The coarse and fine phase adjustments allow for input to output and output to output latency corrections to compensate for PCB load delay, as detailed in 4.5, "Dividers and Skew Management". 4.4 Frequency Synthesizer 21 Microsemi Corporation ZL30165 Data Sheet The device frequency synthesizers can generate output clocks which meet the jitter generation requirements for various timing requirements detailed in section 10.0, "Performance Characterization". The frequency synthesis engines can generate any clock frequency between 1 GHz and 1.5 GHz. The frequency for each synthesizer is programmed as 16 * B * K * M/N Hz where B, K, M and N are 16 bits wide registers. For proper operation of the synthesizer, Bs x Ks x Ms / Ns must not be a multiple any of the following frequencies: 65,536,000; 69,632,000; 73,728,000; 77,824,000; 81,920,000; 86,016,000 or 90,112,000. 4.5 Dividers and Skew Management Each frequency synthesizer has four independent output dividers. Two dividers are associated with differential LVPECL outputs that can generate clocks from 1 Hz to 750 MHz and the other two dividers are associated with single ended LCVCMOS outputs that can generate clocks between 1 Hz and 177.5 MHz. Each synthesizer with associated dividers supports fine and coarse phase (skew) adjustment of output clocks. The fine phase adjustment affects equally all four outputs driven by a particular synthesizer, while the coarse phase affects independently each LVCMOS output. The fine phase adjustment allows the user to advance simultaneously all four outputs of each synthesizer in 256 steps where each step is 1/256 of the Synthesizer clock period. For example if the synthesizer is programmed to generate 1.5GHz clock, the maximum fine advancement is 666.6 ps with the step size of only 2.6 ps. The coarse phase adjustment allows the user to advance or delay each LVCMOS output in steps equal to the period of the synthesizer clock frequency with the maximum range equal to +/-4096 synthesizers clock periods. For example, if the synthesizer is programmed to generate 1.5 GHz clock, the step size will be 1/1.5GHz = 666.6ps and the maximum range will be +/-4096 * 666.6 ps. 22 Microsemi Corporation ZL30165 4.6 Output Clocks Configuration Figure 4 shows relationship between synthesizers, dividers and output dividers. Figure 4 - Output Clocks Configuration 23 Microsemi Corporation Data Sheet ZL30165 4.7 Data Sheet Output Drivers The device has eight high performance (HP) differential (LVPECL) outputs. and eight high performance (HP) single ended outputs. High Performance (HP) single ended driver (LVCMOS) supports a maximum clock frequency of 177.5 MH and the high performance (HP) differential driver (LVPECL) supports a maximum clock frequency of 750 MHz, the jitter performance is detailed in section 10.0, "Performance Characterization". The LVPECL outputs should be terminated as shown in Figure 5. Terminating resistors provide 50 equivalent Thevenin termination as well as biasing for the output LVPECL driver. Terminating resistors should be placed as close as possible to input pins of the LVPECL receiver. If the LVPECL receiver has internal biasing then AC coupling capacitors should be added. 3.3 V 3.3 V Microsemi Device LVPECL driver LVPECL 127 127 receiver 82 82 Zo = 50 Zo = 50 3.3 V 3.3 V 127 127 10 nF 5% 10 nF 5% 82 Figure 5 - Terminating LVPECL Outputs 24 Microsemi Corporation 82 LVPECL receiver with internal biasing ZL30165 Data Sheet If the transmission line is required to be AC coupled then the termination shown in Figure 6 should be implemented. 200 resistors are used to provide DC biasing for LVPECL driver. Both AC coupling capacitor and biasing resistors should be placed as close as possible to output pins. Thevenin termination (127 and 82 resistor provide 50 termination as well as biasing of the input LVPECL receiver. If the LVPECL receiver has internal DC biasing then the line should be terminated with 100 termination resistor between positive and negative input. In both cases termination resistors should be places as close as possible to the LVPECL receiver pins. Some LVPECL receivers have internal biasing and termination. In this case no external termination should be present. 3.3 V 3.3 V Microsemi Device LVPECL driver 82 82 127 127 10 nF 5% LVPECL receiver Zo = 50 10 nF 5% Zo = 50 200 200 LVPECL receiver with internal biasing 100 LVPECL receiver with internal biasing and termination Figure 6 - Terminating AC coupled LVPECL outputs High performance LVCMOS outputs (hpoutclkx) should be terminated at the source with 22 resistor as shown in Figure 7. Microsemi Device LVCMOS driver LVCMOS receiver 22 Zo = 50 Figure 7 - Terminating LVCMOS outputs 25 Microsemi Corporation ZL30165 4.8 Data Sheet Input Buffers The ZL30165 has eight reference inputs ref[7:0]_p/ref[7:0]_n that can work as either single ended or differential. By default all reference inputs are single ended. This can be changed by programming ref_config register. The Input frequency range for differential inputs is: 1 kHz to 750 MHz; for single ended inputs is: 1 kHz to 177.5 MHz. Differential reference inputs need to be properly terminated and biased as shown in Figure 8 and Figure 9 for LVPECL and Figure 10 and Figure 11 for LVDS drivers. When terminating LVPECL signal, it is necessary either to adjust termination resistors for DC coupling or to AC couple the LVPECL driver because ZL30165 differential inputs have different common mode (bias) voltage than LVPECL receivers. Thevenin termination (182 and 68 resistors) provide 50 ohm equivalent termination as well as biasing of the input buffer for DC coupled line. For AC coupled line, Thevenin termination with 127 and 82 resistors should be used as shown in Figure 9. The value of the AC coupling capacitors will depend on the minimum reference clock frequency. The value of 10 nF is good for input clock frequencies above 100 MHz. For lower clock frequencies capacitor values will have to be increased accordingly. Terminations for DC and AC coupled LVDS line are shown in Figure 10 and Figure 11 respectively. Differential input biasing is provided by LVDS driver in case of DC coupling (Figure 10), whereas for AC coupling (Figure 11) biasing is generated by 12 k and 8.2 k resistors. In both cases, the line is terminated with 100 resistor. For single ended CMOS inputs, refx_n input needs to be connected to the ground as shown in Figure 12. The value of series termination resistor will depend on CMOS output driver but the most common values are 33 and 22 . 3.3 V 3.3 V 182 LVPECL driver 182 refx_p Zo = 50 Microsemi Device refx_n Zo = 50 68 68 Figure 8 - Differential DC Coupled LVPECL Termination 26 Microsemi Corporation ZL30165 3.3 V Data Sheet 3.3 V 127 LVPECL driver 127 10 nF 5% refx_p Zo = 50 Microsemi Device 10 nF 5% refx_n Zo = 50 200 200 82 82 Figure 9 - Differential AC Coupled LVPECL Termination LVDS driver refx_p Zo = 50 Microsemi Device 100 refx_n Zo = 50 Figure 10 - Differential DC Coupled LVDS Termination 3.3 V 3.3 V 12.7 k LVDS driver 10 nF 5% 12.7 k refx_p Zo = 50 Microsemi Device 100 10 nF 5% refx_n Zo = 50 8.2 k 8.2 k Figure 11 - Differential AC Coupled LVDS Termination 27 Microsemi Corporation ZL30165 CMOS driver 33 Data Sheet refx_p Zo = 50 Microsemi Device refx_n Figure 12 - Single Ended CMOS Termination 4.9 Master Clock Interface The master oscillator determines the DPLL's free-run frequency accuracy and holdover stability. The reference monitor circuitry also uses this frequency as its point of reference (0 ppm) when making frequency measurements. The master clock interface was designed to accept either a free-running clock oscillator (XO) or a crystal (XTAL). Refer to the Application Note for a list of recommended clock oscillators. 4.9.1 Clock Oscillator When using a clock oscillator as the master timing source, connect the oscillator's output clock to the XOin pin as shown in Figure 13. The connection to XOin should be direct and not AC coupled. The osci_1V8 and osci_3V3 pins must be grounded. The osco_1V8 and osco_3V3 pins must be left unconnected. When using crystal resonator as the master timing source, connect the crystal between osci_1V8 and osco_1V8 pins as shown in Figure 13. (While it is not preferred, the crystal can also be connected between the osci_3V3 and osco_3V3 pins.) The crystal should have bias resistor of 1 Mand load capacitances C1 and C2. Value of the load capacitances is dependent on the crystal and should be per the crystal's datasheet. The crystal should be a fundamental mode type -- not an overtone. When using 24.576 or 49.152 MHz, the user should maintain the default value of the central_freq_offset register (0x046AAAAB). 28 Microsemi Corporation ZL30165 Data Sheet Microsemi Device XOin osci_3V3 osci_1V8 Master Clock = XOin or osci_3V3 or osci_1V8 3.3 V XOin 49.152 MHz TCXO/OCXO/XO Microsemi Device osci_3V3 osco_3V3 Unconnected osci_1V8 osco_1V8 Unconnected XOin C1 osci_1V8 Microsemi Device 1 M 49.152 MHz crystal C2 osco_1V8 osci_3V3 osco_3V3 Load Capacitors C1 and C2 Unconnected values should be as per crystal specification Figure 13 - Clock Oscillator Circuit The device internal system clocks are generated off the device master clock input (oscillator or a crystal employing an on-chip buffer/driver). The master clock selection is done at start-up using the GPIO [1:0] pins, right after pwr_b gets de-asserted. The GPIO[1:0] pins are required to be in desired configuration (high or low) for 125 ms after the de-assertion of pwr_b, and then they can be released and used as regular GPIOs. Alternatively, these pins can be pulled high or low with 1 kresistors. GPIO [1:0] Master Clock Frequency 00 24.576 MHz 01 49.152 MHz 10 20 MHz 11 reserved Table 4 - Master Clock Frequency Selection 29 Microsemi Corporation ZL30165 4.10 Data Sheet Power Up/Down Sequence The 3.3 V supply should be powered before or simultaneously with the 1.8 V supply. The 1.8 V supply must never be greater than the 3.3 V supply by more than 0.3 V. The power-down sequence is less critical, however it should be performed in the reverse order to reduce transient currents that consume power. 4.11 Power Supply Filtering Jitter levels on the output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the device should be isolated from noise on power planes connected to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Microsemi Application Note ZLAN-327. 30 Microsemi Corporation ZL30165 4.12 Data Sheet Reset and Configuration Circuit To ensure proper operation, the device must be reset by holding the pwr_b pin low for at least 2 ms after power-up when 3.3V and 1.8V supplies are stable. Following reset, the device will operate under specified default settings. The reset pin can be controlled with on-board system reset circuitry or by using a stand-alone power-up reset circuit as shown in Figure 14. This circuit provides approximately 2 ms of reset low time. The pwr_b input has Schmidt trigger properties to prevent level bouncing. Microsemi recommends that the power-on reset (pwr_b) signal be controlled by an on-board reset circuit or by a commercially available voltage supervisory device. It may also be possible to use a standalone power-up RC reset circuit. It is important to note that this circuit works reasonably well for power-up as long as the power supply rise time is fast with respect to the RC time constant, which may not always be the case. It is the board designer's responsibility to ensure that the circuit is properly tuned to each power supply's specific situation. As an example, for the capacitor C of 1 F, the resistor should be 10 k or higher. 3.3 V Optional: Populate to enable hpdiff0 1 k 3.3 V Populate for I2C 3.3 V 1 k 1 k gpio1 gpio0 gpio2 GPIO [5:6] are unused on power up for generic devices. Used to select one of four OTP configurations for OTP programmed devices. 3.3 V R Microsemi Device gpio3 gpio4 pwr_b gpio5 gpio6 Populate for SPI 1 k 1 k C 1 k Figure 14 - Typical Power-Up Reset and Configuration Circuit General purpose pins gpio[0,1,3,4] are used to configure device on power up. They have to be pulled up/down with 1 k resistors as shown in Figure 14 or they can be held at the desired level for at least 125 ms after pwr_b goes high and then they can be released and used as general purpose I/O as described in Section 6.0. By default all outputs are disabled to allow programing of required frequencies for different outputs and enabling corresponding outputs. During the prototype phase, hardware designer can verify if the device is working properly even before software driver is implemented just by pulling up gpio2 pin which enables hpdiff0 output (generates 622.08 MHz by default). 31 Microsemi Corporation ZL30165 5.0 Configuration and Control 5.1 ZL30165 Configuration programming Data Sheet The ZL30165 configuration is composed of 768 x 8 bits. The configuration registers are assigned their values by any one of the following three methods: 1. Default Configuration 2. Custom OTP (One Time Programmable) configuration 3. SPI/I2C configuration 5.1.1 Default Configuration At power-up the device sets its configuration registers to the default values. 5.1.2 Custom OTP Configuration At power-up the device sets its configuration registers to the defined custom configuration values stored in its one time programmable memory. Custom configurations can be generated using Microsemi's ClockCenter+ GUI (ZLS30CCPLUS). Up to four unique custom configurations can be stored in the OTP memory and selected via GPIO pins 5,6 as follows: GPIO 5 GPIO 6 Custom Configuration stored in slot 0 0 0 0 1 1 1 0 2 1 1 3 Table 5 - Custom Configuration power-up settings For custom configured devices contact your local Microsemi Field Applications Engineer or Sales Manager. 5.1.3 SPI/I2C Configuration The SPI/I2C host interface allows field programmability of the device's configuration registers. As an example, the user might start the device at nominal SONET rate, then switch to an FEC rate once the link's FEC rate is negotiated. Configurations set via the SPI/I2C interface are volatile and will need to be re-written if the device is reset or powered down. 5.2 Registers Configuration This section refers to configuration registers that are set by the user to control operation of the device. 5.2.1 Input Reference Configuration and Programmability The following parameters can be configured for the reference input: * Input reference frequency * Default input reference selection 32 Microsemi Corporation ZL30165 Data Sheet * Reference selection priority * Automatic or manual reference switching * Glitch-less or hit-less reference switching * Reference switch based on single cycle monitor, coarse frequency monitor, guard soak timer and precise frequency monitor 5.2.2 DPLL Configuration and Programmability The following parameters can be configured for each DPLL: D * Input reference * Loop bandwidth * Phase slope limiter * Pull-in range 5.2.3 Output Multiplexer Configuration The following parameter can be configured: * 5.2.4 Select which DPLL drives which Synthesizer Synthesizer Configuration The following parameters can be configured for each Synthesizer: * Synthesizer can be configured to be locked to any DPLL, freerun or disabled * Synthesizer frequency between 1 GHz and 1.5 GHz 5.2.5 Output Dividers and Output Phase Offset (skew) Configuration The following parameters can be configured: * Output divider enable/disable * Divider ratio * Output phase offset (fine and coarse) 5.2.6 Output Drivers Configuration The following parameters can be configured: * 5.3 Output enable/disable GPIO Configuration The device GPIO is configured using the SPI/I2C. The following is an example of control inputs and status reporting outputs that can be accomplished using the GPIOs: Status Outputs * DPLL lock indicators * DPLL holdover indicators * Reference fail indicators 33 Microsemi Corporation ZL30165 * Data Sheet Interrupt Control Inputs * Select DPLLs reference * External Loss Of Signal (LOS) indications for references 0 to 7 * Enable/disable differential and single ended outputs * Enable/disable TIE Clear * Stop/start output clocks The following table defines the functions of the GPIO pin when configured as a control input pin. Configuring the value in bit 6:0 in gpio_function_pinX register enables the desired function. Value Name Description Default 0x00 Default GPIO defined as an input. No function assigned. Input References 0x10 Ref0 external LOS signal Ref0 external Loss Of Signal (LOS) - indicates to DPLLs that Ref0 has failed. This signal is used by DPLLs locked to Ref0 to do the reference switch or go to the holdover mode if another good reference is not available. 0x11 Ref1 external LOS signal Same description as REF0 external LOS 0x12 Ref2 external LOS signal Same description as REF0 external LOS 0x13 Ref3 external LOS signal Same description as REF0 external LOS 0x14 Ref4 external LOS signal Same description as REF0 external LOS 0x15 Ref5 external LOS signal Same description as REF0 external LOS 0x16 Ref6 external LOS signal Same description as REF0 external LOS 0x17 Ref7 external LOS signal Same description as REF0 external LOS DPLLs 0x20 DPLL0 Time Interval Error (TIE) This signal is OR-ed with the 'DPLL0 TIE clear enable' bit of the clear enable dpllX_ctrl register. The functionality of this signal is explained in the dpllX_ctrl register. 0x28 DPLL1 Time Interval Error (TIE) Same description as DPLL0 TIE clear enable clear enable 0x30 DPLL2 Time Interval Error (TIE) Same description as DPLL0 TIE clear enable clear enable 0x38 DPLL3 Time Interval Error (TIE) Same description as DPLL0 TIE clear enable clear enable Synthesizer Post Divider 0x44 Stop output clock from Synthesizer0 Post Divider C bit1 This signal is OR-ed with the 'Synthesizer0 Post Divider C stop clock' bit1 in the synth1_0_stop_clk register. 0x45 Stop output clock from Synthesizer0 Post Divider C bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 34 Microsemi Corporation ZL30165 Value Name Data Sheet Description 0x46 Stop output clock from Synthesizer0 Post Divider D bit1 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x47 Stop output clock from Synthesizer0 Post Divider D bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x4C Stop output clock from Synthesizer1 Post Divider C bit1 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x4D Stop output clock from Synthesizer1 Post Divider C bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x4E Stop output clock from Synthesizer1 Post Divider D bit1 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x4F Stop output clock from Synthesizer1 Post Divider D bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x54 Stop output clock from Synthesizer2 Post Divider C bit1 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x55 Stop output clock from Synthesizer2 Post Divider C bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x56 Stop output clock from Synthesizer2 Post Divider D bit1 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x57 Stop output clock from Synthesizer2 Post Divider D bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x5C Stop output clock from Synthesizer3 Post Divider C bit1 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x5D Stop output clock from Synthesizer3 Post Divider C bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x5E Stop output clock from Synthesizer3 Post Divider D bit1 Same description as Stop output clock Synthesizer0 Post Divider C bit1 0x5F Stop output clock from Synthesizer3 Post Divider D bit0 Same description as Stop output clock Synthesizer0 Post Divider C bit1 High Performance Differential Outputs 0x60 Enable Differential output HPDIFF0 This signal is OR-ed with the 'Enable HPDIFF0' bit in the hp_diff_en register. Functionality of this signal is explained in hp_diff_en register. 35 Microsemi Corporation ZL30165 Value Name Data Sheet Description 0x62 Enable Differential output HPDIFF1 Same description as Enable Differential output HPDIFF0 0x64 Enable Differential output HPDIFF2 Same description as Enable Differential output HPDIFF0 0x66 Enable Differential output HPDIFF3 Same description as Enable Differential output HPDIFF0 0x68 Enable Differential output HPDIFF4 Same description as Enable Differential output HPDIFF0 0x6A Enable Differential output HPDIFF5 Same description as Enable Differential output HPDIFF0 0x6C Enable Differential output HPDIFF6 Same description as Enable Differential output HPDIFF0 0x6E Enable Differential output HPDIFF7 Same description as Enable Differential output HPDIFF0 High Performance CMOS Outputs 0x70 Enable HPOUTCLK0 This signal is OR-ed with the 'Enable HPOUTCLK0' bit in the hp_cmos_en register. 0x72 Enable HPOUTCLK1 Same description as Enable HPOUTCLK0 0x74 Enable HPOUTCLK2 Same description as Enable HPOUTCLK0 0x76 Enable HPOUTCLK3 Same description as Enable HPOUTCLK0 0x78 Enable HPOUTCLK4 Same description as Enable HPOUTCLK0 0x7A Enable HPOUTCLK5 Same description as Enable HPOUTCLK0 0x7C Enable HPOUTCLK6 Same description as Enable HPOUTCLK0 0x7E Enable HPOUTCLK7 Same description as Enable HPOUTCLK0 The following table defines the function of the GPIO pin when configured as a status output pin. Configuring the value in bit 6:0 in gpio_function_pinX registers enables the stated function. Value Name Description Interrupt 0x80 Interrupt output signal This bit will be high if the interrupt has been asserted. Input Reference Status Indicators 0x88 Ref0 - Precise Frequency Measurement (PFM) failure This bit will be set if Ref0 PFM indicator is active (see pfm_limit_refX register for PFM limits). 0x89 Ref0 Single Cycle Measurement (SCM) failure This bit will be set if Ref0 SCM indicator is active (see scm_cfm_limit_refX register for SCM limits). 0x8A Ref0 Coarse Frequency Measurement (CFM) failure This bit will be set if Ref0 CFM indicator is active (see scm_cfm_limit_refX register for CFM limits). 0x8B Ref0 Guard Soak Timer (GST) Ref0 Guard Soak Timer (GST) indicator indicator 36 Microsemi Corporation ZL30165 Value Name Data Sheet Description 0x8C Ref0 failure indicator This bit will be set if either Ref0 external LOS signal is high, or Ref0 SCM, CFM or GST indicator is high, and appropriate mask bit in the 'Ref0 and Ref1 failure mask' register is set to 1 (not masked). 0x8D Ref1 - Precise Frequency Measurement (PFM) failure Same description as for Ref0 0x8E Ref1 Single Cycle Measurement (SCM) failure Same description as for Ref0 0x8F Ref1 Coarse Frequency Measurement (CFM) failure Same description as for Ref0 0x90 Ref1 Guard Soak Timer (GST) Same description as for Ref0 indicator 0x91 Ref1 failure indicator Same description as for Ref0 0x92 Ref0 - Precise Frequency Measurement (PFM) failure Same description as for Ref0 0x93 Ref2 Single Cycle Measurement (SCM) failure Same description as for Ref0 0x94 Ref2 Coarse Frequency Measurement (CFM) failure Same description as for Ref0 0x95 Ref2 Guard Soak Timer (GST) Same description as for Ref0 indicator 0x96 Ref2 failure indicator Same description as for Ref0 0x97 Ref3 - Precise Frequency Measurement (PFM) failure Same description as for Ref0 0x98 Ref3 Single Cycle Measurement (SCM) failure Same description as for Ref0 0x99 Ref3 Coarse Frequency Measurement (CFM) failure Same description as for Ref0 0x9A Ref3 Guard Soak Timer (GST) Same description as for Ref0 indicator 0x9B Ref3 failure indicator Same description as for Ref0 0x9C Ref3 - Precise Frequency Measurement (PFM) failure Same description as for Ref0 0x9D Ref4 Single Cycle Measurement (SCM) failure Same description as for Ref0 0x9E Ref4 Coarse Frequency Measurement (CFM) failure Same description as for Ref0 0x9F Ref4 Guard Soak Timer (GST) Same description as for Ref0 indicator 0xA0 Ref4 failure indicator Same description as for Ref0 37 Microsemi Corporation ZL30165 Value Name Data Sheet Description 0xA1 Ref5 - Precise Frequency Measurement (PFM) failure Same description as for Ref0 0xA2 Ref5 Single Cycle Measurement (SCM) failure Same description as for Ref0 0xA3 Ref5 Coarse Frequency Measurement (CFM) failure Same description as for Ref0 0xA4 Ref5 Guard Soak Timer (GST) Same description as for Ref0 indicator 0xA5 Ref5 failure indicator Same description as for Ref0 0xA6 Ref6 - Precise Frequency Measurement (PFM) failure Same description as for Ref0 0xA7 Ref6 Single Cycle Measurement (SCM) failure Same description as for Ref0 0xA8 Ref6 Coarse Frequency Measurement (CFM) failure Same description as for Ref0 0xA9 Ref6 Guard Soak Timer (GST) Same description as for Ref0 indicator 0xAA Ref6 failure indicator Same description as for Ref0 0xAB Ref7 - Precise Frequency Measurement (PFM) failure Same description as for Ref0 0xAC Ref7 Single Cycle Measurement (SCM) failure Same description as for Ref0 0xAD Ref7 Coarse Frequency Measurement (CFM) failure Same description as for Ref0 0xAE Ref7 Guard Soak Timer (GST) Same description as for Ref0 indicator 0xAF Ref7 failure indicator Same description as for Ref0 DPLL Status Indicators 0xC0 DPLL0 Normal mode indicator This bit will be set when DPLL0 is in normal locking mode (not holdover, not freerun) 0xC1 DPLL0 holdover mode indicator This bit will be set when DPLL0 is in holdover mode 38 Microsemi Corporation ZL30165 Value Name Data Sheet Description 0xC2 DPLL0 used reference bit3 This bit in combination with DPLL0 ref sel bit2, bit1 and bit0 represents DPLL0 selected reference. Selection: bit3 bit2 bit1 bit0 0 0 0 0 = Ref0 0 0 0 1 = Ref1 0 0 1 0 = Ref2 0 0 1 1 = Ref3 0 1 0 0 = Ref4 0 1 0 1 = Ref5 0 1 1 0 = Ref6 0 1 1 1 = Ref7 0xC3 DPLL0 used reference bit2 See bit3 description 0xC4 DPLL0 used reference bit1 See bit3 description 0xC5 DPLL0 used reference bit0 See bit3 description 0xC6 DPLL0 phase memory hit This bit will be set when DPLL0 phase is beyond selected phase memory limit (specified in the phasemem_limit_refX register). 0xC7 DPLL0 frequency range hit This bit will be set when DPLL0 frequency is beyond pull-in/hold-in range limit, specified in the dpllX_pullin_holdin register 0xC8 DPLL0 phase slope limit This bit will be set when DPLL0 frequency is beyond phase slope limit, specified in the dpllX_ctrl register 0xC9 DPLL0 Lock Indication 0 This bit will be set when DPLL0 phase error is less than 36 us during 10 s period.This bit can be selected for DPLL0 lock indicator. 0xCA DPLL0 Lock Indication 1 This bit will be set when DPLL0 phase error is less than 1us during 1s period.This bit can be selected for DPLL0 lock indicator. 0xCB DPLL0 Lock Indication 2 This bit will be set when DPLL0 phase error is less than 10us during 1s period.This bit can be selected for DPLL0 lock indicator. 0xCC DPLL0 Lock Indication 3 This bit will be set when DPLL0 phase error is less than 10us during 10s period. This bit can be selected for DPLL0 lock indicator. 0xD0 DPLL1 Normal mode indicator Same description as for DPLL0 0xD1 DPLL1 holdover mode indicator Same description as for DPLL0 0xD2 DPLL1 used reference bit3 Same description as for DPLL0 0xD3 DPLL1 used reference bit2 Same description as for DPLL0 0xD4 DPLL1 used reference bit1 Same description as for DPLL0 0xD5 DPLL1 used reference bit0 Same description as for DPLL0 0xD6 DPLL1 phase memory hit Same description as for DPLL0 0xD7 DPLL1 frequency range hit Same description as for DPLL0 0xD8 DPLL1 phase slope limit Same description as for DPLL0 39 Microsemi Corporation ZL30165 Value Name Data Sheet Description 0xD9 DPLL1 Lock Indication 0 Same description as for DPLL0 0xDA DPLL1 Lock Indication 1 Same description as for DPLL0 0xDB DPLL1 Lock Indication 2 Same description as for DPLL0 0xDC DPLL1 Lock Indication 3 Same description as for DPLL0 0xE0 DPLL2 Normal mode indicator Same description as for DPLL0 0xE1 DPLL2 holdover mode indicator Same description as for DPLL0 0xE2 DPLL2 used reference bit3 Same description as for DPLL0 0xE3 DPLL2 used reference bit2 Same description as for DPLL0 0xE4 DPLL2 used reference bit1 Same description as for DPLL0 0xE5 DPLL2 used reference bit0 Same description as for DPLL0 0xE6 DPLL2 phase memory hit Same description as for DPLL0 0xE7 DPLL2 frequency range hit Same description as for DPLL0 0xE8 DPLL2 phase slope limit Same description as for DPLL0 0xE9 DPLL2 Lock Indication 0 Same description as for DPLL0 0xEA DPLL2 Lock Indication 1 Same description as for DPLL0 0xEB DPLL2 Lock Indication 2 Same description as for DPLL0 0xEC DPLL2 Lock Indication 3 Same description as for DPLL0 0xF0 DPLL3 Normal mode indicator Same description as for DPLL0 0xF1 DPLL3 holdover mode indicator Same description as for DPLL0 0xF2 DPLL3 used reference bit3 Same description as for DPLL0 0xF3 DPLL3 used reference bit2 Same description as for DPLL0 0xF4 DPLL3 used reference bit1 Same description as for DPLL0 0xF5 DPLL3 used reference bit0 Same description as for DPLL0 0xF6 DPLL3 phase memory hit Same description as for DPLL0 0xF7 DPLL3 frequency range hit Same description as for DPLL0 0xF8 DPLL3 phase slope limit Same description as for DPLL0 0xF9 DPLL3 Lock Indication 0 Same description as for DPLL0 0xFA DPLL3 Lock Indication 1 Same description as for DPLL0 0xFB DPLL3 Lock Indication 2 Same description as for DPLL0 0xFC DPLL3 Lock Indication 3 Same description as for DPLL0 40 Microsemi Corporation ZL30165 5.3.1 Data Sheet GPIO Indication and Control Functionality The devices includes registers to control the GPIO pins directly using gpio_in_6_0, gpio_out_6_0 and gpio_out_en_6_0. These registers are used with the gpio_function_pinx registers. To read a GPIO: * Set the gpio_function_pinx to 0x00 (control, no function assigned) * Set the bit for the pin in gpio_out_en_6_0 to 0 * Read the current GPIO value in gpio_in_6_0 To set a GPIO: * Set the gpio_function_pinx to 0x00 (control, no function assigned) * Set the bit for the pin in gpio_out_en_6_0 to 1 * The value in gpio_out_6_0 for the GPIO is driven on the GPIO pin 5.4 State Control and Reference Switch Modes In un-managed mode of operation, the DPLL state (normal, freerun and holdover) and the selected reference is automatically set by the internal state machine of the device. It is based on availability of a valid reference and on the reference's selection priority. In managed mode of operation, the DPLL state (normal, freerun and holdover) and the selected reference is manually set by the user. The device allows for a smooth transition from in and out of the two modes of operation. Hence if the DPLL was in managed mode, for example locked to Ref2 reference and switched to un-managed mode of operation, then the state machine continues managing the DPLL, locked to the Ref2 and it will not force reference switching to any other reference unless a change in the Ref2 input conditions occurs that necessitate a change to an alternate input reference. Each DPLL has its own independent state control and reference selection state machine. 5.4.1 Un-managed Mode The un-managed mode combines the functionality of the normal state with automatic holdover and automatic reference switching. In this mode, transitioning from one mode to the other is controlled by the device internal state machine. The on-chip state machine monitors the DPLL status bits, and based on the status information the state machine makes a decision to force holdover or to perform reference switch. The reference switching state machine is based on the internal clock monitoring of each of the available input references and their priorities. The state machine selects a reference source based on its priority value defined in a control register and the current availability of the reference. If all the references are available, the reference with the highest priority is selected; if this reference fails, the next highest priority reference is selected, and so on. In un-managed mode, the state machine only reacts to reference failure indicators and performs reference switching anytime one of the following conditions takes place assuming they are not masked with their corresponding mask bits: * LOS detected a failure and refswitch mask LOS is at logic "1" * SCM detected a failure and refswitch mask SCM is at logic "1" * CFM detected a failure and refswitch mask CFM is at logic "1" 41 Microsemi Corporation ZL30165 * PFM detected a failure and refswitch mask PFM is at logic "1" * GST is triggered and refswitch mask GST is at logic "1" Data Sheet In un-managed mode, the device automatically selects a valid reference input. If the current reference used for synchronization fails, the state machine switches to another available reference. If all the available references fail, then the device enters the holdover mode under one of the following conditions if they are not masked with their corresponding mask bits: * LOS detected a failure and holdover mask LOS is at logic "1" * SCM detected a failure and holdover mask SCM is at logic "1" * CFM detected a failure and holdover mask CFM is at logic "1" * PFM detected a failure and holdover mask PFM is at logic "1" * GST is triggered and holdover mask GST is at logic "1" In un-managed mode of operation, the state machine automatically recovers from holdover when the conditions to enter auto-holdover are not present. The reference selection is based on reference priority. The current active reference for each DPLL can be read from DPLLx Reference Selection Status register. Reference Priority Every reference is assigned a priority value (0 to 7) to allow system designers to specify the priority of each input reference. The priorities are relative to each other, with lower value numbers being the higher priority. Value "1111" disables the ability to select the reference (i.e., don't use for synchronization). If two or more inputs are given the same priority number, the input is selected based on the reference naming convention (i.e., ref0 is higher priority than ref1). The default reference selection priority is equal to its reference number (i.e., ref0 is highest priority and ref7 is the lowest priority). When two references have the same priority they will not revert to each other (as reference availability change), but they will revert to a reference with a higher priority when it is available. 5.4.2 Managed (Manual) Mode In managed mode, the device does not auto-select between different reference inputs. The user specifies which reference to use for synchronization and if it fails the DPLL enters the auto-holdover mode without switching to another reference. The user (external uP) monitors the device status bits. Based on the status information, the user makes a decision to force holdover or to perform reference switch. In managed mode the active reference input is selected based on reference selection control bits. If the user sets the device to lock to a failed reference, the device stays in autoholdover and only locks to that reference if it becomes valid. The state machine only reacts to failure indicators and goes into auto-holdover under one of the following conditions if they are not masked with their corresponding mask bits: * LOS detected a failure and holdover mask LOS is at logic "1" * SCM detected a failure and holdover mask SCM is at logic "1" * CFM detected a failure and holdover mask CFM is at logic "1 * PFM detected a failure and holdover mask PFM is at logic "1 * GST is triggered and holdover mask GST is at logic "1 The state machine automatically recovers from auto-holdover when the conditions to enter auto-holdover are not present. 42 Microsemi Corporation ZL30165 Data Sheet Time critical transitions for entry into auto-holdover and exit from auto-holdover are managed by the internal state machine. A change of the reference select bits triggers an internal state transition into auto-holdover and then an exit into Normal state and locking to the new reference. 43 Microsemi Corporation ZL30165 6.0 Data Sheet Host Interface A host processor controls and receives status from the Microsemi device using either a SPI or an I2C interface. Microsemi Device Microsemi Device sck si so scl sda asel0 asel1 cs_b I2C Configuration SPI Configuration Figure 15 - Serial Interface Configuration The selection between I2C and SPI interfaces is performed at start-up using GPIO[3] pin, as pwr_b gets deasserted. The GPIO[3] pin needs to be held at required level for 125 ms after the de-assertion of pwr_b, after which time they can be released and used as regular GPIO. GPIO[3] Serial Interface 0 SPI 1 I2C Table 6 - Serial Interface Selection Both interfaces use seven bit address field and the device has eight bit address space. Hence, the device register space is divided in five pages of 127 register each. Page 0 has addresses 0x000 to 0x07E and Page 1 with addresses 0x080 to 0x0FF and so on until page 5 which has addresses 0x200 to 0x27E. The host selects between the pages by writing to the Page Select register (address 0x7F on each page). e.g. writing a 0x03 to the page select register makes registers 0x180 to 0x1FF available through the host interface. 6.1 Serial Peripheral Interface The serial peripheral interface (SPI) allows read/write access to the device internal registers that are used to configure, read status, and allow manual control of the device. The serial peripheral interface supports half-duplex processor mode which means that during a write cycle to the device, output data from the so_asel1 pin must be ignored. Similarly, the input data on the si_sda pin is ignored by the device during a read cycle. The SPI interface supports two modes of access: Most Significant bit (MSb) first transmission or Least Significant bit (LSb) first transmission. The mode is automatically selected based on the state of sck_scl pin when the cs_b_asel0 pin is active. If the sck_scl pin is low during cs_b_asel0 activation, then MSb first timing is selected. If the sck_scl pin is high during cs_b_asel0 activation, then LSb first timing is assumed. The SPI port expects 1-bit to differentiate between read and write operation followed by 7-bit addressing and 8-bit data transmission. During SPI access, the cs_b_asel0 pin must be held low until the operation is complete. Burst read/write mode is also supported by leaving the chip select signal cs_b_asel0 is low after a read or a write. The address will be automatically incremented after each data byte is read or written. 44 Microsemi Corporation ZL30165 Data Sheet Functional waveforms for the LSb and MSb first mode, and burst mode are shown in Figure 16, Figure 17 and Figure 18. Timing characteristics are shown in Table 8, Figure 30, and Figure 31. 6.1.1 Least Significant Bit (LSb) First Transmission Mode cs_b sck Read from the device si Rd A0 A1 A2 A3 A4 A5 A6 X so X X X X X X X D0 D1 D2 D3 D4 D5 D6 D7 Write to the device si D0 D1 D2 D3 D4 D5 D6 D7 Wr A0 A1 A2 A3 A4 A5 A6 X so X Command/Address X X X X X X Data Figure 16 - Serial Peripheral Interface Functional Waveforms - LSb First Mode 45 Microsemi Corporation ZL30165 6.1.2 Data Sheet Most Significant Bit (MSb) First Transmission Mode cs_b sck Read from the device si Rd A6 A5 A4 A3 A2 A1 A0 so X X X X X X X D7 D6 D5 D4 D3 D2 X D1 D0 Write to the device si Wr A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X Command/Address so X X X X X Data Figure 17 - Serial Peripheral Interface Functional Waveforms - MSb First Mode 6.1.3 SPI Burst Mode Operation cs_b Address +0 Address Data Address +1 Data Address +2 Address +N Data Data Figure 18 - Example of a Burst Mode Operation 6.1.4 I2C Interface The I2C controller supports version 2.1 (January 2000) of the Philips I2C bus specification. The port operates in slave mode with 7-bit addressing, and can operate in Standard (100 kbits/s) and Fast (400 kbits/s) mode. Burst mode is supported in both standard and fast modes. Data is transferred MSb first and occurs in 1 byte blocks. As shown in Figure 19, a write command consists of a 7bit device (slave) address, a R/W indicator bit, a 7-bit register address (0x00 - 0x7F), and 8-bits of data. 46 Microsemi Corporation ZL30165 Byte Byte Byte Data Write Data Sheet S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK Data[7:0] ACK P S Start (master) W Write Master Initiated P Stop (master) R Read Slave Initiated ACK Acknowledge Figure 19 - I2C Data Write Protocol A read is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. This is shown in Figure 20. Byte Byte Data Write (set read address) S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK P Data Read S Slv Addr[6:0] R ACK Data[7:0] ACK P Figure 20 - I 2C Data Read Protocol The 7-bit device (slave) address contains a 5-bit fixed address plus variable bits which are set with the asel0, and asel1 pins. This allows multiple ZL30165s to share the same I2C bus. The address configuration is shown in Figure 21. 6 5 4 3 2 1 0 0 0 1 1 0 asel0 asel1 Figure 21 - I 2C 7-bit Slave Address The device also supports burst mode which allows multiple data write or read operations with a single specified address. This is shown in Figure 22 (write) and Figure 23 (read). The first data byte is written/read to/from the specified address, and subsequent data bytes are written/read using an automatically increment address. The maximum auto increment address of a burst operation is 0x7F and operations beyond this limit will be ignored. In other words, the auto increment address does not wrap around to 0x00 after reaching 0x7F. 47 Microsemi Corporation ZL30165 Data Sheet Data Write (Burst Mode) S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK Data[7:0] ACK Data[7:0] ACK Data[7:0] ACK P Write to Reg Addr[6:0] Write to Reg Addr[6:0] +1 Figure 22 - I 2C Data Write Burst Mode Data Write (Set first read address) S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK P Data Read (Burst Mode) S Slv Addr[6:0] R ACK Data[7:0] ACK Data[7:0] ACK Data[7:0] ACK P Read from Reg Addr[6:0] Read from Reg Addr[6:0] +1 Read from Reg Addr[6:0] +2 Figure 23 - I 2C Data Read Burst Mode 48 Microsemi Corporation Write to Reg Addr[6:0] +2 ZL30165 7.0 Data Sheet Register Map The device is controlled by accessing registers through the serial interface (SPI or I2C). The device can be configured to operate in un-managed (automatic) mode which minimizes its interaction with the system's processor, or it can operate in a managed (manual) mode where the system processor controls operation of the device. A simple way to generate configuration for the device is to use the evaluation board GUI which can operate standalone (without the evaluation board). Through the GUI the user can quickly set all required parameters and save the configuration to a text file which can then be used by the system processor to load and configure the device. Multi-byte Register Values The device register map is based on 8-bit register access, so register values that require more than 8 bits are spread out over multiple registers and accessed in 8-bit segments. When accessing multi-byte register values, it is important that the registers are accessed in the proper order. The 8-bit register containing the most significant byte (MSB) must be accessed first, and the register containing the least significant byte (LSB) must be accessed last. An example of a multi-byte register is shown in Figure 24. When writing a multi-byte value, the value is latched when the LSB is written. Example: The input reference M and N 16 are bit values defining the M/N ratio is programmed using a 32-bit value which is spread over four 8-bit registers. The MSB is contained in address 0x1BC and the LSB in 0x1BF When reading or writing this multi-byte value, the MSB must be accessed first, then the middle bytes, and the LSB last. 0x1BC (MSB) 0x1BD 0x1BE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 Read or Write this byte first 2 Read or Write this byte next 3 0x1BF (LSB) 8 7 6 5 4 3 2 1 Read or Write this byte next 4 0 Read or Write this byte last Figure 24 - Accessing Multi-byte Register Values Time between two write accesses to the same register * User should wait at least 25 ms between two write accesses to the same register * The dplln_df_offset registers can be written with a minimum wait time of 300 microseconds between write accesses to the same register. * For the page selection register (at addresses 0x07F, 0x0FF, 0x17F, 0x1FF, 0x27F, 0x2FF, 0x37F and 0x3FF), there is no waiting time required between write accesses. Basic Procedure for Refreshing Latest Device Status from Sticky Read (StickyR) Registers without Interrupt Handler Access to some status registers is defined as Sticky Read (StickyR). Procedure for accessing these registers is: -write 0x01 to Sticky Lock Register at address 0x011 -clear status register(s) by writing 0x00 to it -write 0x00 to StickyR Lock Register at address 0x011 -wait for 25 ms 49 Microsemi Corporation ZL30165 Data Sheet -read the status register(s) Basic Procedure for Refreshing Latest Device Status from Sticky Read (StickyR) Registers when using an Interrupt Handler (event or polling) Access to some status registers is defined as Sticky Read (StickyR). Procedure for accessing these registers is: -host receives IRQ event or poll timer expiry -disable the CPU IRQ -write 0x01 to Sticky Lock Register at address 0x011 -read status register(s) (Sticky Status since the last IRQ) -clear status register(s) by writing 0x00 to it -write 0x00 to StickyR Lock Register at address 0x011 -exit IRQ handler or IRQ poll routine -Re-enable the CPU IRQ -next update to status will not occur for for another 25 ms -wait for IRQ event or poll timer expiry 50 Microsemi Corporation ZL30165 Data Sheet The following table provides a summary of the registers available for status and configuration of the device. Devices with a custom OTP configuration will power-up with the custom configuration values instead of the default values. Reg_Addr (Hex) Register Name Default Value (Hex) Description Type Miscellaneous Registers 0x000 ready 0x1F Ready Indicator register R 0x001 id_reg 0xA5 Chip ID Register R 0x002 chip_revision 0x05 Chip Revision register R 0x00B:0x00E central_freq_offset 0x046AAAAB Central frequency offset R/W 0x010 Spurs supression 0x00 Spurs supression R/W 0x011 sticky_lock 0x00 Sticky Lock Register R/W Input Reference Monitoring and DPLL Status 0x020 ref_fail_isr_status_7_0 0x00 Reference failure interrupt status register for Ref 7:0 StickyR/W 0x022 dpll_isr_status 0x00 DPLL interrupt status register StickyR/W 0x023 ref_fail_isr_mask_7_0 0x00 Reference failure interrupt mask register fro Ref 7:0 R/W 0x025 dpll_isr_mask 0x00 DPLL interrupt status register R/W 0x026 ref_mon_fail_0 0x00 Reference 0 Failure Indicators StickyR/W 0x027 ref_mon_fail_1 0x00 Reference 1 Failure Indicators StickyR/W 0x028 ref_mon_fail_2 0x00 Reference 2 Failure Indicators StickyR/W 0x029 ref_mon_fail_3 0x00 Reference 3 Failure Indicators StickyR/W 0x02A ref_mon_fail_4 0x00 Reference 4 Failure Indicators StickyR/W 0x02B ref_mon_fail_5 0x00 Reference 5 Failure Indicators StickyR/W 0x02C ref_mon_fail_6 0x00 Reference 6 Failure Indicators StickyR/W 0x02D ref_mon_fail_7 0x00 Reference 7 Failure Indicators StickyR/W 0x036 ref_mon_fail_mask_0 0x16 Reference 0 Failure Masks R/W Table 7 - Register Map 51 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x037 ref_mon_fail_mask_1 0x16 Reference 1 Failure Masks R/W 0x038 ref_mon_fail_mask_2 0x16 Reference 2 Failure Masks R/W 0x039 ref_mon_fail_mask_3 0x16 Reference 3 Failure Masks R/W 0x03A ref_mon_fail_mask_4 0x16 Reference 4 Failure Masks R/W 0x03B ref_mon_fail_mask_5 0x16 Reference 5 Failure Masks R/W 0x03C ref_mon_fail_mask_6 0x16 Reference 6 Failure Masks R/W 0x03D ref_mon_fail_mask_7 0x16 Reference 7 Failure Masks R/W 0x046 gst_disqualif_time_3_0 0xAA Guard soak timer (GST) disqualify time selection for Ref3:0 R/W 0x047 gst_disqualif_time_7_4 0xAA Guard soak timer (GST) disqualify time selection for Ref7:4 R/W 0x04A gst_qualif_time_3_0 0x55 Guard soak timer (GST) qualify time selection for Ref 3:0 R/W 0x04B gst_qualif_time_7_4 0x55 Guard soak timer (GST) qualify time selection for Ref 7:4 R/W 0x050 scm_cfm_limit_ref0 0x55 SCM and CFM limits for Reference 0 R/W 0x051 scm_cfm_limit_ref1 0x55 SCM and CFM limits for Reference 1 R/W 0x052 scm_cfm_limit_ref2 0x55 SCM and CFM limits for Reference 2 R/W 0x053 scm_cfm_limit_ref3 0x55 SCM and CFM limits for Reference 3 R/W 0x054 scm_cfm_limit_ref4 0x55 SCM and CFM limits for Reference 4 R/W 0x055 scm_cfm_limit_ref5 0x55 SCM and CFM limits for Reference 5 R/W 0x056 scm_cfm_limit_ref6 0x55 SCM and CFM limits for Reference 6 R/W 0x057 scm_cfm_limit_ref7 0x55 SCM and CFM limits for Reference 7 R/W 0x060 pfm_limit_ref1_0 0x33 PFM limits for References 1 and 0 R/W 0x061 pfm_limit_ref3_2 0x33 PFM limits for References 3 and 2 R/W 0x062 pfm_limit_ref5_4 0x33 PFM limits for References 5 and 4 R/W Table 7 - Register Map (continued) 52 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x063 pfm_limit_ref7_6 0x33 PFM limits for Reference 7 and 6 R/W 0x068 phase_acq_en_7_0 0xFF Phase Acquisition enable for Acq7:0 R/W 0x06A phasemem_limit_ref0 0x1B Phase memory limit for Reference 0 R/W 0x06B phasemem_limit_ref1 0x1B Phase memory limit for Reference 1 R/W 0x06C phasemem_limit_ref2 0x1B Phase memory limit for Reference 2 R/W 0x06D phasemem_limit_ref3 0x1B Phase memory limit for Reference 3 R/W 0x06E phasemem_limit_ref4 0x1B Phase memory limit for Reference 4 R/W 0x06F phasemem_limit_ref5 0x1B Phase memory limit for Reference 5 R/W 0x070 phasemem_limit_ref6 0x1B Phase memory limit for Reference 6 R/W 0x071 phasemem_limit_ref7 0x1B Phase memory limit for Reference 7 R/W 0x07A ref_config_7_0 0x00 Reference configuration register for References 7 to 0 R/W 0x07C ref_pre_divide_7_0 0x00 Reference predivider control register for Ref7:0 R/W Additional Miscellaneous Configuration 0x07F page_sel_register 0x00 SPI Page Selection Register R/W Input Frequency Configuration 0x080:0x081 ref0_base_freq 0x9C40 Ref0 base frequency Br0 R/W 0x082:0x083 ref0_freq_multiple 0x0F30 Ref0 base frequency multiple Kr0 R/W 0x084:0x087 ref0_ratio_M_N 0x00010001 Ref0 Forward Error Correction (FEC) multiplication ratio Mr0 / Nr0 (numerator Mr0 and denominator Nr0 values) R/W 0x088:0x089 ref1_base_freq 0x9C40 Ref1 base frequency Br1 R/W 0x08A:0x08B ref1_freq_multiple 0x01E6 Ref1 base frequency multiple Kr1 R/W 0x08C:0x08F ref1_ratio_M/N 0x00010001 Ref1 Forward Error Correction (FEC) multiplication ratio Mr1/ Nr1 R/W Table 7 - Register Map (continued) 53 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x090:0x091 ref2_base_freq 0x9C40 Ref2 base frequency Br2 R/W 0x092:0x093 ref2_freq_multiple 0x01E6 Ref2 base frequency multiple Kr2 R/W 0x094:0x097 ref2_ratio_M/N 0x00010001 Ref2 Forward Error Correction (FEC) multiplication ratio Mr2 / Nr2 R/W 0x098:0x099 ref3_base_freq 0x9C40 Ref3 base frequency Br3 R/W 0x09A:0x09B ref3_freq_multiple 0x01E6 Ref3 base frequency multiple Kr3 R/W 0x09C:0x09F ref3_ratio_M/N 0x00010001 Ref3 Forward Error Correction (FEC) multiplication ratio Mr3 / Nr3 R/W 0x0A0:0x0A1 ref4_base_freq 0x9C40 Ref4 base frequency Br4 R/W 0x0A2:0x0A3 ref4_freq_multiple 0x01E6 Ref4 base frequency multiple Kr4 R/W 0x0A4:0x0A7 ref4_ratio_M/N 0x00010001 Ref4 Forward Error Correction (FEC) multiplication ratio Mr4 / Nr4 R/W 0x0A8:0x0A9 ref5_base_freq 0x9C40 Ref5 base frequency Br5 R/W 0x0AA:0x0AB ref5_freq_multiple 0x01E6 Ref5 base frequency multiple Kr5 R/W 0x0AC:0x0AF ref5_ratio_M/N 0x00010001 Ref5 Forward Error Correction (FEC) multiplication ratio Mr5 / Nr5 R/W 0x0B0:0x0B1 ref6_base_freq 0x9C40 Ref6 base frequency Br6 R/W 0x0B2:0x0B3 ref6_freq_multiple 0x01E6 Ref6 base frequency multiple Kr6 R/W 0x0B4:0x0B7 ref6_ratio_M/N 0x00010001 Ref6 Forward Error Correction (FEC) multiplication ratio Mr6 / Nr6 R/W 0x0B8:0x0B9 ref7_base_freq 0x9C40 Ref7 base frequency Br7 R/W 0x0BA:0x0BB ref7_freq_multiple 0x01E6 Ref7 base frequency multiple Kr7 R/W 0x0BC:0x0BF ref7_ratio_M/N Ref7 Forward Error Correction (FEC) multiplication ratio Mr7 / Nr7 R/W 0x0FF page_sel_register SPI Page Selection register R/W 0x00010001 0x00 DPLL Configuration Registers 0x100 dpll0_ctrl 0x0C DPLL0 Control register R/W 0x102 dpll0_pull_in_hold_in 0x00 DPLL0 Pull-in Hold-in selection register R/W Table 7 - Register Map (continued) 54 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x103 dpll0_mode_refsel 0x03 DPLL0 mode and reference selection R/W 0x104 dpll0_refsel_stat 0x00 DPLL0 reference selection status R 0x105 dpll0_ref_priority1_0 0x10 DPLL0 reference 1 and 0 selection priority R/W 0x106 dpll0_ref_priority_3_2 0x32 DPLL0 reference 3 and 2 selection priority R/W 0x107 dpll0_ref_priority_5_4 0x54 DPLL0 reference 5 and 4 selection priority R/W 0x108 dpll0_ref_priority_7_6 0x76 DPLL0 reference 7 and 6 selection priority R/W 0x10D dpll0_ref_fail_mask 0x87 DPLL0 reference failure mask (used for automatic reference switching and automatic holdover) R/W 0x10E dpll0_pfm_fail_mask 0x01 DPLL0 reference failure mask based on PFM failure indicator (used for automatic reference switching and automatic holdover) R/W 0x10F dpll0_ho_edge_sel 0x0B DPLL0 Holdover Storage Delay and Reference Edge Selection register R/W 0x120 dpll1_ctrl 0x0C DPLL1 Control register R/W 0x122 dpll1_pull_in_hold_in 0x00 DPLL1 Pull-in Hold-in selection register R/W 0x123 dpll1_mode_refsel 0x03 DPLL1 mode and reference selection R/W 0x124 dpll1_refsel_stat 0x00 DPLL1 reference selection status R 0x125 dpll1_ref_priority_1_0 0x10 DPLL1 reference 1 and 0 selection priority R/W 0x126 dpll1_ref_priority_3_2 0x32 DPLL1 reference 3 and 2 selection priority R/W 0x127 dpll1_ref_priority_5_4 0x54 DPLL1 reference 5 and 4 selection priority R/W 0x128 dpll1_ref_priority_7_6 0x76 DPLL1 reference 7 and 6 selection priority R/W 0x12D dpll1_ref_fail_mask 0x87 DPLL1 reference failure mask (used for automatic reference switching and automatic holdover) R/W Table 7 - Register Map (continued) 55 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x12E dpll1_pfm_fail_mask 0x01 DPLL1 reference failure mask based on PFM failure indicator (used for automatic reference switching and automatic holdover) R/W 0x12F dpll1_ho_edge_sel 0x0B DPLL1 Holdover Storage Delay and Reference Edge Selection register R/W 0x140 dpll2_ctrl 0x0C DPLL2 Control register R/W 0x142 dpll2_pull_in_hold_in 0x00 DPLL2 Pull-in Hold-in selection register R/W 0x143 dpll2_mode_refsel 0x03 DPLL2 mode and reference selection R/W 0x144 dpll2_refsel_stat 0x00 DPLL2 reference selection status R 0x145 dpll2_ref_priority_1_0 0x10 DPLL2 reference 1 and 0 selection priority R/W 0x146 dpll2_ref_priority_3_2 0x32 DPLL2 reference 3 and 2 selection priority R/W 0x147 dpll2_ref_priority_5_4 0x54 DPLL2 reference 5 and 4 selection priority R/W 0x148 dpll2_ref_priority_7_6 0x76 DPLL2 reference 7 and 6 selection priority R/W 0x14D dpll2_ref_fail_mask 0x87 DPLL2 reference failure mask (used for automatic reference switching and automatic holdover) R/W 0x14E dpll2_pfm_fail_mask 0x01 DPLL2 reference failure mask based on PFM failure indicator (used for automatic reference switching and automatic holdover) R/W 0x14F dpll2_ho_edge_sel 0x0B DPLL2 Holdover Storage Delay and Reference Edge Selection register R/W 0x160 dpll3_ctrl 0x0C DPLL3 Control register R/W 0x162 dpll3_pull_in_hold_in 0x00 DPLL3 Pull-in Hold-in selection register R/W 0x163 dpll3_mode_refsel 0x03 DPLL3 mode and reference selection R/W 0x164 dpll3_refsel_stat 0x00 DPLL3 reference selection status R Table 7 - Register Map (continued) 56 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x165 dpll3_ref_priority_1_0 0x10 DPLL3 reference 1 and 0 selection priority R/W 0x166 dpll3_ref_priority_3_2 0x32 DPLL3 reference 3 and 2 selection priority R/W 0x167 dpll3_ref_priority_5_4 0x54 DPLL3 reference 5 and 4 selection priority R/W 0x168 dpll3_ref_priority_7_6 0x76 DPLL3 reference 7 and 6 selection priority R/W 0x16D dpll3_ref_fail_mask 0x87 DPLL3 reference failure mask (used for automatic reference switching and automatic holdover) R/W 0x16E dpll3_pfm_fail_mask 0x01 Enables phase build out for DPLL3, resets the build out occurrence counter, and resets total phase build out accumulated phase R/W 0x16F dpll3_ho_edge_sel 0x0B DPLL2 Holdover Storage Delay and Reference Edge Selection register R/W 0x17F page_sel_register 0x00 Page Selection register R/W 0x180 dpll_hold_lock_status 0x00 DPLL Lock and holdover status StickyR/W 0x182 dpll_config 0x04 DPLL configuration register R/W 0x183 dpll_lock_selection 0xAA DPLL lock selection R/W DPLL Delta Frequency Registers 0x18D:0x191 dpll0_df_offset 0x0000000000 DPLL0 Delta Frequency offset W 0x192:0x196 dpll1_df_offset 0x0000000000 DPLL1 Delta Frequency offset W 0x197:0x19B dpll2_df_offset 0x0000000000 DPLL2 Delta Frequency offset W 0x19C:0x1A0 dpll3_df_offset 0x0000000000 DPLL3 Delta Frequency offset W Output Synthesizer Configuration Registers 0x1B0 synth_drive_pll 0xE4 DPLL to Synthesizer assignment selection R/W 0x1B1 synth_enable 0x03 Synthesizer Enable register R/W 0x1B6 sync_fail_flag_status 0x00 Synthesizer APLL syncFailFlag status R Table 7 - Register Map (continued) 57 Microsemi Corporation ZL30165 Reg_Addr (Hex) 0x1B7 Register Name clear_sync_fail_flag Data Sheet Default Value (Hex) 0x00 Description Synthesizer APLL Clear syncFailFlag Type R/W Output Reference Selection and Output Driver Control 0x1B8:0x1B9 synth0_base_freq 0x9C40 Synthesizer0 base frequency Bs0 R/W 0x1BA:0x1BB synth0_freq_multiple 0x0798 Synthesizer0 base frequency multiple Ks0 R/W 0x1BC:0x1BF synth0_ratio_M_N 0x00010001 Synthesizer0 Forward Error Correction (FEC) multiplication ratio Ms0 / Ns0 (numerator Ms0 and denominator Ns0 values) R/W 0x1C0:0x1C1 synth1_base_freq 0x61A8 Synthesizer0 base frequency Bs0 R/W 0x1C2:0x1C3 synth1_freq_multiple 0x0C35 Synthesizer0 base frequency multiple Ks0 R/W 0x1C4:0x1C7 synth1_ratio_M_N 0x00010001 Synthesizer0 Forward Error Correction (FEC) multiplication ratio Ms0 / Ns0 (numerator Ms0 and denominator Ns0 values) R/W 0x1C8:0x1C9 synth2_base_freq 0x94C0 Synthesizer0 base frequency Bs0 R/W 0x1CA:0x1CB synth2_freq_multiple 0x0798 Synthesizer0 base frequency multiple Ks0 R/W 0x1CC:0x1CF synth2_ratio_M_N 0x00010001 Synthesizer0 Forward Error Correction (FEC) multiplication ratio Ms0 / Ns0 (numerator Ms0 and denominator Ns0 values) R/W 0x1D0:0x1D1 synth3_base_freq 0x9C40 Synthesizer0 base frequency Bs0 R/W 0x1D2:0x1D3 synth3_freq_multiple 0x0798 Synthesizer0 base frequency multiple Ks0 R/W 0x1D4:0x1D7 synth3_ratio_M_N 0x00010001 Synthesizer0 Forward Error Correction (FEC) multiplication ratio Ms0 / Ns0 (numerator Ms0 and denominator Ns0 values) R/W 0x1FF page_sel_register 0x00 SPI Page Selection register R/W 0x200:0x202 synth0_post_div_A 0x000002 Synthesizer0 Post Divider A R/W 0x203:0x205 synth0_post_div_B 0x000002 Synthesizer0 Post Divider B R/W 0x206:0x208 synth0_post_div_C 0x000040 Synthesizer0 Post Divider C R/W 0x209:0x20B synth0_post_div_D 0x000040 Synthesizer0 Post Divider D R/W Table 7 - Register Map (continued) 58 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x20C:0x20E synth1_post_div_A 0x000002 Synthesizer1 Post Divider A R/W 0x20F:0x211 synth1_post_div_B 0x000002 Synthesizer1 Post Divider B R/W 0x212:0x214 synth1_post_div_C 0x000032 Synthesizer1 Post Divider C R/W 0x215:0x217 synth1_post_div_D 0x000032 Synthesizer1 Post Divider D R/W 0x218:0x21A synth2_post_div_A 0x000000 Synthesizer2 Post Divider A R/W 0x21B:0x21D synth2_post_div_B 0x000000 Synthesizer2 Post Divider B R/W 0x21E:0x220 synth2_post_div_C 0x000000 Synthesizer2 Post Divider C R/W 0x221:0x223 synth2_post_div_D 0x000000 Synthesizer2 Post Divider D R/W 0x224:0x226 synth3_post_div_A 0x000000 Synthesizer3 Post Divider A R/W 0x227:0x229 synth3_post_div_B 0x000000 Synthesizer3 Post Divider B R/W 0x22A:0x22C synth3_post_div_C 0x000000 Synthesizer3 Post Divider C R/W 0x22D:0x22F synth3_post_div_D 0x000000 Synthesizer3 Post Divider D R/W 0x234:0x235 phase_shift_s0_postdiv_c 0x0000 Synthesizer0 Post Divider C phase shift R/W 0x236:0x237 phase_shift_s0_postdiv_d 0x0000 Synthesizer0 Post Divider D phase shift R/W 0x23C:0x23D phase_shift_s1_postdiv_c 0x0000 Synthesizer1 Post Divider C phase shift R/W 0x23E:0x23F phase_shift_s1_postdiv_d 0x0000 Synthesizer1 Post Divider D phase shift R/W 0x244:0x245 phase_shift_s2_postdiv_c 0x0000 Synthesizer2 Post Divider C phase shift R/W 0x246:0x247 phase_shift_s2_postdiv_d 0x0000 Synthesizer2 Post Divider D phase shift R/W 0x24C:0x24D phase_shift_s3_postdiv_c 0x0000 Synthesizer3 Post Divider C phase shift R/W 0x24E:0x24F phase_shift_s3_postdiv_d 0x0000 Synthesizer3 Post Divider D phase shift R/W 0x250 synth0_fine_phase_shift 0x00 Synth0 fine phase shift (skew) in steps of VCO period over 256 R/W 0x251 synth1_fine_phase_shift 0x00 Synth1 fine phase shift (skew) in steps of VCO period over 256 R/W 0x252 synth2_fine_phase_shift 0x00 Synth2 fine phase shift (skew) in steps of VCO period over 256 R/W Table 7 - Register Map (continued) 59 Microsemi Corporation ZL30165 Reg_Addr (Hex) Register Name Data Sheet Default Value (Hex) Description Type 0x253 synth3_fine_phase_shift 0x00 Synth3 fine phase shift (skew) in steps of VCO period over 256 R/W 0x254 synth1_0_stop_clk 0x00 Synthesizer0 and Synthesizer1 Post Dividers D and C stop clock R/W 0x255 synth3_2_stop_clk 0x00 Synthesizer3 and Synthesizer2 Post Dividers D and C stop clock R/W 0x261 hp_diff_en 0x00 High Performance Differential Output enable R/W 0x262 hp_cmos_en 0x00 High Performance CMOS Output enable R/W GPIO Related Registers 0x266 gpio_function_pin0 0x00 GPIO0 select or status R/W 0x267 gpio_function_pin1 0x00 GPIO1 select or status R/W 0x268 gpio_function_pin2 0x60 GPIO2 select or status R/W 0x269 gpio_function_pin3 0x00 GPIO3 select or status R/W 0x26A gpio_function_pin4 0x00 GPIO4 select or status R/W 0x26B gpio_function_pin5 0x00 GPIO5 select or status R/W 0x26C gpio_function_pin6 0x00 GPIO6 select or status R/W 0x276 gpio_in_7_0 0x00 GPIO7:0 Input Register R 0x278 gpio_out_7_0 0x00 GPIO7:0 Output Register R/W 0x27A gpio_out_en_7_0 0x00 GPIO7:0 Output Enable Register R/W 0x27C gpio_latch_7_0 0x00 GPIO7:0 Freeze Register R 0x27F page_sel_register 0x00 SPI Page Selection register R/W 0x2C2 dpll0_fast_lock_ctrl 0x00 Controls fast lock in DPLL0 R/W 0x2C5 dpll1_fast_lock_ctrl 0x00 Controls fast lock in DPLL1 R/W 0x2C8 dpll2_fast_lock_ctrl 0x00 Controls fast lock in DPLL2 R/W 0x2CB dpll3_fast_lock_ctrl 0x00 Controls fast lock in DPLL3 R/W 0x2D4 dpll0_holdover_filt_ctrl 0x00 Holdover Filter Value R/W 0x2D5 dpll1_holdover_filt_ctrl 0x00 Holdover Filter Value R/W 0x2D6 dpll2_holdover_filt_ctrl 0x00 Holdover Filter Value R/W 0x2D7 dpll3_holdover_filt_ctrl 0x00 Holdover Filter Value R/W 0x2FF page_sel_register 0x00 SPI Page Selection register R/W Table 7 - Register Map (continued) 60 Microsemi Corporation ZL30165 Data Sheet . 61 Microsemi Corporation ZL30165 8.0 Data Sheet Detailed Register Map Register_Address: 0x000 Register Name: ready Default Value: 0x1F Type: R Bit Field 7 Function Name Description Ready indication After reset this bit goes high when device is ready. This signals that user can start to program/configure the device. 6:5 Reserved Leave as default 4:0 Chip family identification Family Identification = 0b11111 Register_Address: 0x001 Register Name: chip_id Default Value: 0xA5 Type: R Bit Field 7:0 Function Name Chip ID register Description Chip id number: Unsigned binary value of these bits represent chip id number. Customer should not write to this register. Register_Address: 0x002 Register Name: chip_revision Default Value: 0x05 Type: R Bit Field 7:0 Function Name Description Chip Hardware Revision register Chip revision number: Unsigned binary value of these bits represent chip revision number. Customer should not write to this register. 62 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x00B:0x00E Register Name: central_freq_offset Default Value: 0x046AAAAB Type: R/W Bit Field 31:0 Function Name Central frequency offset Description 2's complement binary value of these bits represent central frequency offset for the device. This value should be used to compensate for oscillator inaccuracy. This register the controls central frequency of all 4 Synthesizers. Expressed in steps of +/- 2^-32 of nominal setting. When the oscillator inaccuracy is known: inacc_osc = (f_osc - f_nom)/f_nom (usually specified in ppm), value to be programmed in this register is calculated using the following formula: X = (1/(1 + inacc_osc) - 1)*2^32, when f_osc < f_nom X = (1/(1 + inacc_osc))*2^32, when f_osc > f_nom, where inacc_osc - represents oscillator frequency inaccuracy, f_osc - represents oscillator frequency, and f_nom - represents oscillator nominal frequency (i.e. 25MHz, 20MHz or 50MHz) Generally, when the oscillator frequency is lower than the nominal, frequency offset has to be programmed to compensate it in opposite direction, i.e. frequency offset has to be positive, and vice versa. Example 1): if oscillator inaccuracy is -2% (f_osc = 24.5 MHz; inacc_osc = (f_osc - 25 MHz)/25MHz = -0.02), X= (1/(1+(-0.02)) - 1)*2^32 = (1/0.98 - 1)*2^32 = 87652394 = 0x0539782A Example 2): if oscillator inaccuracy is +2% (f_osc = 25.5 MHz; inacc_osc = (f_osc - 25 MHz)/25MHz = 0.02), X= (1/(1+ 0.02))*2^32 = (1/1.02)*2^32 = 4210752251 = 0xFAFAFAFB Note 1: The nominal frequency for central frequency offset calculation is 25 MHz. With the master clock frequency of 24.576 MHz this register should be set to 0x046AAAAB (default value). The value of 0x046AAAAB also applies to 49.152 MHz (from a nominal of 50 MHz). Note 2: Central Frequency Offset should not exceed +/-5% off nominal. Note 3: The spurs_supression register must be programmed after changing the central_freq_offset, even if the value has not changed. 63 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x010 Register Name: Spurs_supression Default Value: 0x00 Type: R/W Bit Field 7:0 Function Name Spurs supression Description This register is used for spurs suppression. Depending on the synthesizer configuration GUI will generate recommended value. When this register is changed, the ZL30165 requires 85 msec to reconfigure itself. No reads or writes to the device are permitted during this reconfiguration period. The spurs_suppression register should only be written with values recommended by the GUI. Note: This register must be programmed after changing the central_freq_offset even if the value has not changed. Register_Address: 0x011 Register Name: sticky_lock Default Value: 0x00 Type: R/W Bit Field 7:0 Function Name Sticky Lock Register Description This register needs to be set to a non-zero value prior to clearing sticky (status) registers, to avoid race condition that can happen when the internal state machine updates the status register while the host clears it. Setting this register to a non-zero value stops the updating of any of the sticky registers, and clearing this register restarts the updating of the sticky registers. For proper sticky register monitoring, see the procedure in section 7.0, "Register Map". 64 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x020 Register Name: ref_fail_isr_status_7_0 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7 Ref7 Fail This bit will be set high when 'Ref7 fail mask' bit of the ref_fail_isr_mask_7_0 register is high and conditions for Ref7 failure have occurred. When this bit is set to high, it also sets IRQ line to high. This bit is 'sticky', so once set it will stay high until the user clears it. Conditions for Ref7 failure are satisfied when either of LOS (external Loss of Signal), SCM (Single Cycle Monitor), CFM (Coarse Frequency Monitor), GST (Guard Soak Timer) or PFM (Precise Frequency Monitor) indicators are active and the appropriate mask bit (specified in the ref_mon_fail_mask_X register) is high. The failure indicators can be checked in the ref_mon_fail_X register. 6 Ref6 Fail See Ref7 above 5 Ref5 Fail See Ref7 above 4 Ref4 Fail See Ref7 above 3 Ref3 Fail See Ref7 above 2 Ref2 Fail See Ref7 above 1 Ref1 Fail See Ref7 above 0 Ref0 Fail See Ref7 above Register_Address: 0x022 Register Name: dpll_isr_status Default Value: 0x00 Type: StickyR/W Bit Field 7 Function Name DPLL3 Lost Lock Description The device will set this bit to high when 'DPLL3 Lost Lock Mask' bit of the dpll_isr_mask register is high and DPLL3 has lost lock. When this bit is set to high, it also sets IRQ line to high. This bit is 'sticky', so it will stay high until the user clears it. The lost lock indicator can be checked in the dpll_hold_lock_status register. 65 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x022 Register Name: dpll_isr_status Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 6 DPLL3 Holdover The device will set this bit to high when 'DPLL3 Holdover Mask' bit of the dpll_isr_mask register is high and DPLL3 went into holdover mode. When this bit is set to high, it also sets IRQ line to high. This bit is 'sticky', so it will stay high until the user clears it. The holdover indicator can be checked in the dpll_hold_lock_status register. 5 DPLL2 Lost Lock See description for DPLL3 Lost Lock above 4 DPLL2 Holdover See description for DPLL3 Holdover above 3 DPLL1 Lost Lock See description for DPLL3 Lost Lock above 2 DPLL1 Holdover See description for DPLL3 Holdover above 1 DPLL0 Lost Lock See description for DPLL3 Lost Lock above 0 DPLL0 Holdover See description for DPLL3 Holdover above Register_Address: 0x023 Register Name: ref_fail_isr_mask_7_0 Default Value: 0x00 Type: R/W Bit Field Function Name Description 7 Ref7 Fail Mask When set to high, this bit allows Ref7 fail indicator to appear in the ref_fail_isr_status_7_0 register and on the IRQ line. When low, the Ref7 failure indicator is masked. 6 Ref6 Fail Mask See description for Ref7 above 5 Ref5 Fail Mask See description for Ref7 above 4 Ref4 Fail Mask See description for Ref7 above 3 Ref3 Fail Mask See description for Ref7 above 2 Ref2 Fail Mask See description for Ref7 above 1 Ref1 Fail Mask See description for Ref7 above 0 Ref0 Fail Mask See description for Ref7 above 66 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x025 Register Name: dpll_isr_mask Default Value: 0x00 Type: R/W Bit Field Function Name Description 7 DPLL3 Lost Lock Mask When set to high, this bit allows DPLL3 lost lock indicator to appear in the dpll_isr_status register and on the IRQ line. When low, the DPLL3 lost lock indicator is masked. 6 DPLL3 Holdover Mask When set to high, this bit allows DPLL3 holdover indicator to appear in the dpll_isr_status register and on the IRQ line. When low, the DPLL3 holdover indicator is masked. 5 DPLL2 Lost Lock See description for DPLL3 Lost Lock Mask above 4 DPLL2 Holdover See description for DPLL3 Holdover Mask above 3 DPLL1 Lost Lock See description for DPLL3 Lost Lock Mask above 2 DPLL1 Holdover See description for DPLL3 Holdover Mask above 1 DPLL0 Lost Lock See description for DPLL3 Lost Lock Mask above 0 DPLL0 Holdover See description for DPLL3 Holdover Mask above Register_Address: 0x026 Register Name: ref_mon_fail_0 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref0 Fail PFM Ref0 Precise Frequency Monitor (PFM) failure: This bit is set high when Ref0 fails to meet the Precise Frequency Monitor (PFM) failure criteria specified by the 'PFM limit' bits of the pfm_limit_ref1_0 register. The PFM failure criteria is typically referred to as reference frequency drift. This bit is 'sticky', so it will remain high until the user clears it. Note: This bit is not maskable, i.e. whenever conditions for it to be set are met, it will be set, regardless of any mask bits 67 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x026 Register Name: ref_mon_fail_0 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 3 Ref0 Fail GST Guard Soak Timer failure (GST): This bit is set when Ref0 fails to meet Guard Soak Timer (GST) failure criteria specified by the 'GST disqualify Ref0' bits of the gst_disqualif_time_3_0 register. The GST timer is triggered by either CFM or SCM failure and this bit will be set if either of the two failures still exists upon expiration of the GST time. This bit is 'sticky', so it will stay high until customer clears it. Note: This bit is not maskable, i.e. whenever conditions for it to be set are met, it will be set, regardless of any mask bits 2 Ref0 Fail CFM Ref0 Coarse Frequency Monitor (CFM) failure: This bit is set this when Ref0 fails to meet Coarse Frequency Monitor (CFM) failure criteria specified by the 'Ref0 CFM Limit' bits of the scm_cfm_limit_ref0 register. The CFM failure criteria is usually referred to as reference phase hit. This bit is 'sticky', so it will stay high until customer clears it. Note: this bit is not maskable, i.e. whenever conditions for it to be set are met, it will be set, regardless of any mask bits 1 Ref0 Fail SCM Ref0 Single Cycle Monitor (SCM) failure: This bit is set when Ref0 fails to meet Single Cycle Monitor (SCM) failure criteria specified by the 'Ref0 SCM limit' bits of the scm_cfm_limit_ref0 register. The SCM failure criteria is usually referred to as reference phase irregularity. This bit is 'sticky', so it will stay high until the user clears it. Note: this bit is not maskable, i.e. whenever conditions for it to be set are met, it will be set, regardless of any mask bits 0 Ref0 Fail LOS External Ref0 Loss Of Signal (LOS) indicator: This bit is set when the external Ref0 LOS signal, applied to a selected GPIO, goes high. This bit is 'sticky', so it will stay high until the user clears it. The Ref0 LOS signal can be selected to appear on any of available GPIOs through the gpio_function_pin[0:6] registers. Note: this bit is not maskable, i.e. whenever conditions for it to be set are met, it will be set, regardless of any mask bits Register_Address: 0x027 Register Name: ref_mon_fail_1 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:0 Ref1 Fail Leave as default 4 Ref1 Fail PFM Ref1 Precise Frequency Monitoring (PFM) failure. See description for register at address 0x026 bit 4 3 Ref1 Fail GST Ref1 Guard Soak Timer (GST) failure. See description for register at address 0x026 bit 3 68 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x027 Register Name: ref_mon_fail_1 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 2 Ref1 Fail CFM Ref1 Coarse Frequency Monitor (CFM) failure. See description for register at address 0x026 bit 2 1 Ref1 Fail SCM Ref1 Single Cycle Monitor (SCM) failure. See description for register at address 0x026 bit 1 0 Ref1 Fail LOS Ref1 Loss of Signal (LOS). See description for register at address 0x026 bit 0 Register_Address: 0x028 Register Name: ref_mon_fail_2 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref2 Fail PFM Ref2 Precise Frequency Monitoring (PFM) failure. See description for register at address 0x026 bit 4 3 Ref2 Fail GST Ref2 Guard Soak Timer (GST) failure. See description for register at address 0x026 bit 3 2 Ref2 Fail CFM Ref2 Coarse Frequency Monitor (CFM) failure. See description for register at address 0x026 bit 2 1 Ref2 Fail SCM Ref2 Single Cycle Monitor (SCM) failure. See description for register at address 0x026 bit 1 0 Ref2 Fail LOS Ref2 Loss of Signal (LOS). See description for register at address 0x026 bit 0 Register_Address: 0x029 Register Name: ref_mon_fail_3 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref3 Fail PFM Ref3 Precise Frequency Monitoring (PFM) failure. See description for register at address 0x026 bit 4 3 Ref3 Fail GST Ref3 Guard Soak Timer (GST) failure. See description for register at address 0x026 bit 3 69 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x029 Register Name: ref_mon_fail_3 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 2 Ref3 Fail CFM Ref3 Coarse Frequency Monitor (CFM) failure. See description for register at address 0x026 bit 2 1 Ref3 Fail SCM Ref3 Single Cycle Monitor (SCM) failure. See description for register at address 0x026 bit 1 0 Ref3 Fail LOS Ref3 Loss of Signal (LOS). See description for register at address 0x026 bit 0 Register_Address: 0x02A Register Name: ref_mon_fail_4 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref4 Fail PFM Ref4 Precise Frequency Monitoring (PFM) failure. See description for register at address 0x026 bit 4 3 Ref4 Fail GST Ref4 Guard Soak Timer (GST) failure. See description for register at address 0x026 bit 3 2 Ref4 Fail CFM Ref4 Coarse Frequency Monitor (CFM) failure. See description for register at address 0x026 bit 2 1 Ref4 Fail SCM Ref4 Single Cycle Monitor (SCM) failure. See description for register at address 0x026 bit 1 0 Ref4 Fail LOS Ref4 Loss of Signal (LOS). See description for register at address 0x026 bit 0 Register_Address: 0x02B Register Name: ref_mon_fail_5 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref5 Fail PFM Ref5 Precise Frequency Monitoring (PFM) failure. See description for register at address 0x026 bit 4 70 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x02B Register Name: ref_mon_fail_5 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 3 Ref5 Fail GST Ref5 Guard Soak Timer (GST) failure. See description for register at address 0x026 bit 3 2 Ref5 Fail CFM Ref5 Coarse Frequency Monitor (CFM) failure. See description for register at address 0x026 bit 2 1 Ref5 Fail SCM Ref5 Single Cycle Monitor (SCM) failure. See description for register at address 0x026 bit 1 0 Ref5 Fail LOS Ref5 Loss of Signal (LOS). See description for register at address 0x026 bit 0 Register_Address: 0x02C Register Name: ref_mon_fail_6 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref6 Fail PFM Ref6 Precise Frequency Monitoring (PFM) failure. See description for register at address 0x026 bit 4 3 Ref6 Fail GST Ref6 Guard Soak Timer (GST) failure. See description for register at address 0x026 bit 3 2 Ref6 Fail CFM Ref6 Coarse Frequency Monitor (CFM) failure. See description for register at address 0x026 bit 2 1 Ref6 Fail SCM Ref6 Single Cycle Monitor (SCM) failure. See description for register at address 0x026 bit 1 0 Ref6 Fail LOS Ref6 Loss of Signal (LOS). See description for register at address 0x026 bit 0 Register_Address: 0x02D Register Name: ref_mon_fail_7 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref7 Fail PFM Ref7 Precise Frequency Monitoring (PFM) failure. See description for register at address 0x026 bit 4 71 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x02D Register Name: ref_mon_fail_7 Default Value: 0x00 Type: StickyR/W Bit Field Function Name Description 3 Ref7 Fail GST Ref7 Guard Soak Timer (GST) failure. See description for register at address 0x026 bit 3 2 Ref7 Fail CFM Ref7 Coarse Frequency Monitor (CFM) failure. See description for register at address 0x026 bit 2 1 Ref7 Fail SCM Ref7 Single Cycle Monitor (SCM) failure. See description for register at address 0x026 bit 1 0 Ref7 Fail LOS Ref7 Loss of Signal (LOS). See description for register at address 0x026 bit 0 Register_Address: 0x036 Register Name: ref_mon_fail_mask_0 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref0 Fail PFM Mask When set to high, this bit will allow Ref0 Fail PFM to appear in ref_fail_isr_status_7_0 register and on IRQ line if not masked by 'Ref0 Fail Mask' bit in the ref_fail_isr_mask_7_0 register. When low, Ref0 Fail PFM will be masked from appearing in the ref_fail_isr_status_7_0 register and on IRQ line. Note: This bit will not affect 'Ref0 Fail PFM' bit in the ref_mon_fail_0 register since the ref_mon_fail_0 register values are not maskable. 3 Ref0 Fail GST Mask When set to high, this bit will allow Ref0 Fail GST to appear in ref_fail_isr_status_7_0 register and on IRQ line if not masked by 'Ref0 Fail Mask' bit in the ref_fail_isr_mask_7_0 register. When low, Ref0 Fail GST will be masked from appearing in the ref_fail_isr_status_7_0 register and on IRQ line. Note: This bit will not affect 'Ref0 Fail GST' bit in the ref_mon_fail_0 register since the ref_mon_fail_0 register values are not maskable. 72 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x036 Register Name: ref_mon_fail_mask_0 Default Value: 0x16 Type: R/W Bit Field 2 Function Name Ref0 Fail CFM Mask Description When set to high, this bit will allow Ref0 Fail CFM to appear in ref_fail_isr_status_7_0 register and on IRQ line if not masked by 'Ref0 Fail Mask' bit in the ref_fail_isr_mask_7_0 register. When low, Ref0 CFM failure will be masked from appearing, as part of Ref0 failure indicator, in the ref_fail_isr_mask_7_0 register and on IRQ line. Note: This bit will not affect 'Ref0 Fail CFM' bit in the ref_mon_fail_0 register since the ref_mon_fail_0 register values are not maskable. 1 Ref0 Fail SCM Mask When set to high, this bit will allow Ref0 Fail SCM to appear in ref_fail_isr_status_7_0 register and on IRQ line if not masked by 'Ref0 Fail Mask' bit in the ref_fail_isr_mask_7_0 register. When low, Ref0 SCM failure will be masked from appearing, as part of Ref0 failure indicator, in the 'Reference status interrupt failure' register and on IRQ line. Note: This bit will not affect 'Ref0 Fail SCM' bit in the ref_mon_fail_0 register since the ref_mon_fail_0 register values are not maskable. 0 Ref0 Fail LOS Mask When set to high, this bit will allow Ref0 Fail LOS to appear in ref_fail_isr_status_7_0 register and on IRQ line if not masked by 'Ref0 Fail Mask' bit in the ref_fail_isr_mask_7_0 register. When low, Ref0 external LOS failure will be masked from appearing, as part of Ref0 failure indicator, in the 'Reference status interrupt failure' register and on IRQ line. Note: This bit will not affect 'Ref0 Fail LOS' bit in the ref_mon_fail_0 register since the ref_mon_fail_0 register values are not maskable. Register_Address: 0x037 Register Name: ref_mon_fail_mask_1 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref1 Fail PFM Mask See description for register at address 0x036 bit 4 3 Ref1 Fail GST Mask See description for register at address 0x036 bit 3 2 Ref1 Fail CFM Mask See description for register at address 0x036 bit 2 1 Ref1 Fail SCM Mask See description for register at address 0x036 bit 1 73 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x037 Register Name: ref_mon_fail_mask_1 Default Value: 0x16 Type: R/W Bit Field 0 Function Name Ref1 Fail LOS Mask Description See description for register at address 0x036 bit 0 Register_Address: 0x038 Register Name: ref_mon_fail_mask_2 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref2 Fail PFM Mask See description for register at address 0x036 bit 4 3 Ref2 Fail GST Mask See description for register at address 0x036 bit 3 2 Ref2 Fail CFM Mask See description for register at address 0x036 bit 2 1 Ref2 Fail SCM Mask See description for register at address 0x036 bit 1 0 Ref2 Fail LOS Mask See description for register at address 0x036 bit 0 Register_Address: 0x039 Register Name: ref_mon_fail_mask_3 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref3 Fail PFM Mask See description for register at address 0x036 bit 4 3 Ref3 Fail GST Mask See description for register at address 0x036 bit 3 2 Ref3 Fail CFM Mask See description for register at address 0x036 bit 2 1 Ref3 Fail SCM Mask See description for register at address 0x036 bit 1 0 Ref3 Fail LOS Mask See description for register at address 0x036 bit 0 74 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x03A Register Name: ref_mon_fail_mask_4 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref4 Fail PFM Mask See description for register at address 0x036 bit 4 3 Ref4 Fail GST Mask See description for register at address 0x036 bit 3 2 Ref4 Fail CFM Mask See description for register at address 0x036 bit 2 1 Ref4 Fail SCM Mask See description for register at address 0x036 bit 1 0 Ref4 Fail LOS Mask See description for register at address 0x036 bit 0 Register_Address: 0x03B Register Name: ref_mon_fail_mask_5 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref5 Fail PFM Mask See description for register at address 0x036 bit 4 3 Ref5 Fail GST Mask See description for register at address 0x036 bit 3 2 Ref5 Fail CFM Mask See description for register at address 0x036 bit 2 1 Ref5 Fail SCM Mask See description for register at address 0x036 bit 1 0 Ref5 Fail LOS Mask See description for register at address 0x036 bit 0 Register_Address: 0x03C Register Name: ref_mon_fail_mask_6 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref6 Fail PFM Mask See description for register at address 0x036 bit 4 3 Ref6 Fail GST Mask See description for register at address 0x036 bit 3 75 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x03C Register Name: ref_mon_fail_mask_6 Default Value: 0x16 Type: R/W Bit Field Function Name Description 2 Ref6 Fail CFM Mask See description for register at address 0x036 bit 2 1 Ref6 Fail SCM Mask See description for register at address 0x036 bit 1 0 Ref6 Fail LOS Mask See description for register at address 0x036 bit 0 Register_Address: 0x03D Register Name: ref_mon_fail_mask_7 Default Value: 0x16 Type: R/W Bit Field Function Name Description 7:5 Reserved Leave as default 4 Ref7 Fail PFM Mask See description for register at address 0x036 bit 4 3 Ref7 Fail GST Mask See description for register at address 0x036 bit 3 2 Ref7 Fail CFM Mask See description for register at address 0x036 bit 2 1 Ref7 Fail SCM Mask See description for register at address 0x036 bit 1 0 Ref7 Fail LOS Mask See description for register at address 0x036 bit 0 76 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x046 Register Name: gst_disqualif_time_3_0 Default Value: 0xAA Type: R/W Bit Field Function Name Description 7:6 Ref3 GST disqualification time Guard soak timer disqualify time: Time to disqualify Ref3 input clock after detection of either a Ref3 CFM or Ref3 SCM failure indications. The expiration of the GST disqualify time after starting of the Ref3 GST disqualify timer will cause the Ref3 GST indicator to go high if the source of the timer triggering is still present. Selection: 00 = minimum delay possible 01 = 10 ms 10 = 50 ms (default) 11 = 2.5 s 5:4 Ref2 GST disqualification time See bits 7:6 (Ref3) for details 3:2 Ref1 GST disqualification time See bits 7:6 (Ref3) for details 1:0 Ref0 GST disqualification time See bits 7:6 (Ref3) for details Register_Address: 0x047 Register Name: gst_disqualif_time_7_4 Default Value: 0xAA Type: R/W Bit Field Function Name Description 7:6 Ref7 GST disqualification time See description for register at address 0x046 bits 7:6 5:4 Ref6 GST disqualification time See description for register at address 0x046 bits 7:6 3:2 Ref5 GST disqualification time See description for register at address 0x046 bits 7:6 1:0 Ref4 GST disqualification time See description for register at address 0x046 bits 7:6 77 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x04A Register Name: gst_qualif_time_3_0 Default Value: 0x55 Type: R/W Bit Field 7:6 Function Name Ref3 GST qualification time Description Guard soak timer qualify time selection: Time to qualify Ref3 input clock after disappearance of both the Ref3 CFM and the Ref3 SCM failure indications. The expiration of the GST qualify time after starting of the Ref3 GST qualify timer will cause Ref3 GST failure indicator to go low if neither the Ref3 CFM nor the Ref3 SCM indicator is present. Selection: 00 = 2 x selected Ref3 GST disqualify time 01 = 4 x selected Ref3 GST disqualify time (default) 10 = 8 x selected Ref3 GST disqualify time 11 = 16 x selected Ref3 GST disqualify time 5:4 Ref2 GST qualification time See bits 7:6 (Ref3) for details 3:2 Ref1 GST qualification time See bits 7:6 (Ref3) for details 1:0 Ref0 GST qualification time See bits 7:6 (Ref3) for details Register_Address: 0x04B Register Name: gst_qualif_time_7_4 Default Value: 0x55 Type: R/W Bit Field Function Name Description 7:6 Ref7 GST qualification time See description for register at address 0x04A bits 7:6 5:4 Ref6 GST qualification time See description for register at address 0x04A bits 7:6 3:2 Ref5 GST qualification time See description for register at address 0x04A bits 7:6 1:0 Ref4 GST qualification time See description for register at address 0x04A bits 7:6 78 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x050 Register Name: scm_cfm_limit_ref0 Default Value: 0x55 Type: R/W Bit Field 7 6:4 Function Name Description Reserved Leave as default Ref0 SCM limit These bits represent Ref0 Single Cycle Monitor (SCM) limit selection. When Ref0 fails the criteria specified by these bits, the SCM failure indicator will go high (can be read in the ref_mon_fail_0 register) Selection: 000 = +/- 0.1% (in Ref0 frequency units) 001 = +/- 0.5% 010 = +/- 1% 011 = +/- 2% 100 = +/- 5% 101 = +/- 10% 110 = +/- 20% 111 = +/- 50% Note that Ref0 clock is sampled by a 800 MHz clock, so the measurement granularity is 1.25 ns. This imposes a limitation to SCM limits that can be programmed depending on Ref0 clock frequencies: +/- 0.1% can be programmed for frequencies below 800 kHz +/- 0.5%: below 4 MHz +/- 1% : below 8 MHz +/- 2% : below 16 MHz +/- 5% : below 40 MHz +/- 10% : below 80 MHz +/- 20% : below 160 MHz +/- 50% : below 400 MHz Note 1: The SCM indicator should not be used (it should be masked) for reference frequencies above 400MHz. Note 2: For frequencies below 16 kHz, the CFM and SCM limits should be be set to the same value for proper operation. 3 Reserved Leave as default 79 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x050 Register Name: scm_cfm_limit_ref0 Default Value: 0x55 Type: R/W Bit Field 2:0 Function Name Ref0 CFM Limit Description These bits represent the Ref0 Coarse Frequency Monitor (CFM) limit selection. When Ref0 fails the criteria specified by these bits, the CFM failure indicator will go high (can be read in the ref_mon_fail_0 register). Selection: 000 = +/- 0.1% (in Ref0 frequency units) 001 = +/- 0.5% 010 = +/- 1% 011 = +/- 2% 100 = +/- 5% 101 = +/- 10% 110 = +/- 20% 111 = +/- 50% Note: For frequencies below 16 kHz, the CFM and SCM limits should be be set to the same value for proper operation. 80 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x051 Register Name: scm_cfm_limit_ref1 Default Value: 0x55 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref1 SCM limit See description for register at address 0x050 bits 6:4 Reserved Leave as default Ref1 CFM Limit See description for register at address 0x050 bits 2:0 Register_Address: 0x052 Register Name: scm_cfm_limit_ref2 Default Value: 0x55 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref2 SCM limit See description for register at address 0x050 bits 6:4 Reserved Leave as default Ref2 CFM Limit See description for register at address 0x050 bits 2:0 Register_Address: 0x053 Register Name: scm_cfm_limit_ref3 Default Value: 0x55 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref3 SCM limit See description for register at address 0x050 bits 6:4 Reserved Leave as default Ref3 CFM Limit See description for register at address 0x050 bits 2:0 81 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x054 Register Name: scm_cfm_limit_ref4 Default Value: 0x55 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref4 SCM limit See description for register at address 0x050 bits 6:4 Reserved Leave as default Ref4 CFM Limit See description for register at address 0x050 bits 2:0 Register_Address: 0x055 Register Name: scm_cfm_limit_ref5 Default Value: 0x55 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref5 SCM limit See description for register at address 0x050 bits 6:4 Reserved Leave as default Ref5 CFM Limit See description for register at address 0x050 bits 2:0 Register_Address: 0x056 Register Name: scm_cfm_limit_ref6 Default Value: 0x55 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref6 SCM limit See description for register at address 0x050 bits 6:4 Reserved Leave as default Ref6 CFM Limit See description for register at address 0x050 bits 2:0 82 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x057 Register Name: scm_cfm_limit_ref7 Default Value: 0x55 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref7 SCM limit See description for register at address 0x050 bits 6:4 Reserved Leave as default Ref7 CFM Limit See description for register at address 0x050 bits 2:0 Register_Address: 0x060 Register Name: pfm_limit_ref1_0 Default Value: 0x33 Type: R/W Bit Field 7 6:4 Function Name Description Reserved Leave as default Ref1 PFM Limit These bits represent the Ref1 Precise Frequency Monitor (PFM) limit selection. When Ref1 fails this criteria, the PFM failure indicator will go high that can be read in the ref_mon_fail_1 register. Selection: 000 = 9.2 --- 12 ppm (in Ref1 frequency units) 001 = 40 --- 52 ppm 010 = 64 --- 83 ppm 011 = 100 --- 130 ppm 100 = 13.8 --- 18 ppm 101 = 24.6 --- 32 ppm 110 = 36.6 --- 47.5 ppm 111 = 52 --- 67.5 ppm Example: For Ref1 PFM Limit = 000, the input reference will be accepted if its frequency accuracy is lower than +/- 9.2 ppm. If the input reference frequency accuracy exceeds +/- 12 ppm, than the reference will be rejected. If the input reference frequency accuracy is in between +/-9.2 ppm and +/-12 ppm the state remains unchanged (hysteresis). Note : PFM supports any reference (input) frequency from 1 Hz to 750 MHz except for non integer (in Hz) frequencies below 5,000,000 Hz. For example 1 Hz, 8 kHz, 2.048 MHz, 156.25*66/64 MHz are supported frequencies but 0.5 Hz and 1.5 Hz are not supported. 3 2:0 Reserved Leave as default Ref0 PFM Limit See bits 6:4 (Ref1) 83 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x061 Register Name: pfm_limit_ref3_2 Default Value: 0x33 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref3 PFM Limit See description for register at address 0x060 bits 6:4 Reserved Leave as default Ref2 PFM Limit See description for register at address 0x060 bits 2:0 Register_Address: 0x062 Register Name: pfm_limit_ref5_4 Default Value: 0x33 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref5 PFM Limit See description for register at address 0x060 bits 6:4 Reserved Leave as default Ref4 PFM Limit See description for register at address 0x060 bits 2:0 Register_Address: 0x063 Register Name: pfm_limit_ref7_6 Default Value: 0x33 Type: R/W Bit Field 7 6:4 3 2:0 Function Name Description Reserved Leave as default Ref7 PFM Limit See description for register at address 0x060 bits 6:4 Reserved Leave as default Ref6 PFM Limit See description for register at address 0x060 bits 2:0 84 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x068 Register Name: phase_acq_en_7_0 Default Value: 0xFF Type: R/W Bit Field Function Name Description 7 Phase Acquisition 7 enable When this bit is set to high, it will enable Phase Acquisition module for Ref7 input. When low, Phase Acquisition 7 is disabled (i.e. powered down). 6 Phase Acquisition 6 enable See bit 7 for details 5 Phase Acquisition 5 enable See bit 7 for details 4 Phase Acquisition 4 enable See bit 7 for details 3 Phase Acquisition 3 enable See bit 7 for details 2 Phase Acquisition 2 enable See bit 7 for details 1 Phase Acquisition 1 enable See bit 7 for details 0 Phase Acquisition 0 enable See bit 7 for details Register_Address: 0x06A Register Name: phasemem_limit_ref0 Default Value: 0x1B Type:R/W Bit Field 7:0 Function Name Phase memory limit for Ref0 Description These bits specify the Ref0 phase memory limit as per the following formula, using E32 series style: Value = round(32 * log(PhaseMemLimit/10) ), where PhaseMemLimit is given in us units Example, if the desired delay is 10us, the value to be written to this register is 0x00, for 1 ms the value is 0x40, while for 930 seconds the value is 0xFF. Note: This register should be programmed to have a value that represents at least one reference period. 85 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x06B Register Name: phasemem_limit_ref1 Default Value: 0x1B Type:R/W Bit Field Function Name 7:0 Phase memory limit for Ref1 Description See description for register at address 0x06A Register_Address: 0x06C Register Name: phasemem_limit_ref2 Default Value: 0x1B Type:R/W Bit Field Function Name 7:0 Phase memory limit for Ref2 Description See description for register at address 0x06A Register_Address: 0x06D Register Name: phasemem_limit_ref3 Default Value: 0x1B Type:R/W Bit Field Function Name 7:0 Phase memory limit for Ref3 Description See description for register at address 0x06A Register_Address: 0x06E Register Name: phasemem_limit_ref4 Default Value: 0x1B Type:R/W Bit Field Function Name 7:0 Phase memory limit for Ref4 Description See description for register at address 0x06A 86 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x06F Register Name: phasemem_limit_ref5 Default Value: 0x1B Type:R/W Bit Field Function Name 7:0 Phase memory limit for Ref5 Description See description for register at address 0x06A Register_Address: 0x070 Register Name: phasemem_limit_ref6 Default Value: 0x1B Type:R/W Bit Field Function Name 7:0 Phase memory limit for Ref6 Description See description for register at address 0x06A Register_Address: 0x071 Register Name: phasemem_limit_ref7 Default Value: 0x1B Type:R/W Bit Field Function Name 7:0 Phase memory limit for Ref7 Description See description for register at address 0x06A Register_Address: 0x07A Register Name: ref_config_7_0 Default Value: 0x00 Type:R/W Bit Field Function Name 7 Ref7 differential input enable When this bit is set high, the device expects differential signal on its Ref7 pins (REF7_P and REF7_N). When low, the device expects single-ended signal on the REF7_P input, and the REF7_N input should be tied to GND. 6 Ref6 differential input enable See bit 7 for details Description 87 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x07A Register Name: ref_config_7_0 Default Value: 0x00 Type:R/W Bit Field Function Name 5 Ref5 differential input enable See bit 7 for details 4 Ref4 differential input enable See bit 7 for details 3 Ref3 differential input enable See bit 7 for details 2 Ref2 differential input enable See bit 7 for details 1 Ref1 differential input enable See bit 7 for details 0 Ref0 differential input enable See bit 7 for details Description Register_Address: 0x07C Register Name: ref_pre_divide_7_0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 Ref7 pre-divider enable When this bit is set to high, the Ref7 input clock will be divided by 2 prior being processed by the DPLLs. All registers requiring Ref7 frequency information are programmed as if the divider output frequency is actual Ref7 frequency. When low, the Ref7 input clock is not divided prior being processed by the DPLLs. 6 Ref6 pre-divider enable See bit 7 for details 5 Ref5 pre-divider enable See bit 7 for details 4 Ref4 pre-divider enable See bit 7 for details 3 Ref3 pre-divider enable See bit 7 for details 2 Ref2 pre-divider enable See bit 7 for details 1 Ref1 pre-divider enable See bit 7 for details 0 Ref0 pre-divider enable See bit 7 for details 88 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x07F Register Name: page_sel_register Default Value: 0x00 Type:R/W Bit Field 7:0 Function Name Page selection register Description The unsigned binary value written to this register selects the 128 byte page of registers that the host can write to. 0x00: page 0 (register addresses 0x00 to 0x7F) 0x01: page 1 (register addresses 0x80 to 0xFF) 0x02: page 2 (register addresses 0x100 to 0x17F) 0x03: page 3 (register addresses 0x180 to 0x1FF) 0x04: page 4 (register addresses 0x200 to 0x27F) 0x05: page 5 (register addresses 0x280 to 0x2FF) 0x06-0xFF: reserved Register_Address: 0x080:0x081 Register Name: ref0_base_freq Default Value: 0x9C40 Type:R/W Bit Field Function Name Description 15:0 Ref0 base frequency Br0 Unsigned binary value of these bits represents Ref0 base frequency Br in Hz. Examples of values fro Br that can be programmed: 0x0001 for 1Hz, 0x000A for 10Hz, 0x0064 for 100Hz 0x03E8 for 1kHz, 0x07D0 for 2kHz, 0x1F40 for 8kHz, 0x61A8 for 25kHz, 0x9C40 for 40kHz. Note 1: Br has to be directly divisible from 1600000000, i.e. mod (1600000000, Br) has to be 0. The evaluation board GUI can generate recommended Br, Kr, Mr and Nr values for required input frequency. Note 2: in order to write e.g. 0x9C40 to this register (and any other register whose value is larger than 8 bits), 0x9C has to be written to the lower address and 0x40 to the upper address (big endian) with the 0x40 (LSBs) written last. 89 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x082:0x083 Register Name: ref0_freq_multiple Default Value: 0x0F30 Type:R/W Bit Field 15:0 Function Name Ref0 base frequency multiple Kr0 Description Unsigned binary value represents the Ref0 base frequency multiplication number. For a regular (non-FEC) reference frequency, the 'Base frequency' number Br multiplied by the 'Base frequency multiple' number Kr has to equal the reference frequency in Hz. Examples of some references frequencies and appropriate values that can be programmed for Br and Kr to match that reference frequency: Ref0 frequency Base frequency Br 2.048 MHz 1.544 MHz 19.44 MHz 177.5.MHz 125 MHz 156.25.MHz 155.52 MHz 1234 Hz 8 kHz Base frequency multiple Kr 8 kHz (0x1F40) 8 kHz (0x1F40) 40 kHz (0x9C40) 25 kHz (0x61A8) 40 kHz (0x9C40) 25 kHz (0x61A8) 40 kHz (0x9C40) 1 Hz (0x0001) 1 kHz (0x03E8) 256 (0x0100) 193 (0x00C1) 486 (0x01E6) 7100 (0x1BBC) 18752 (0x4940) 6250 (0x186A) 3888 (0x0F30) 1234 (0x04D2) 8 (0x0008) Register_Address: 0x084:0x087 Register Name: ref0_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Description Function Name 31:16 Ref0 FEC ratio numerator Mr 15:0 Ref0 FEC ratio denominator Nr Unsigned binary value of Mr bits, in combination with unsigned binary value of Nr bits represents Ref0 FEC multiplication ratio. For FEC reference frequencies, the 'Base frequency' number Br multiplied by the 'Base frequency multiple' number Kr, multiplied by Mr and divided by Nr has to equal the reference frequency in Hz; Ref_freq [Hz] = Br x Kr x Mr / Nr For regular (non-FEC) reference frequencies, Mr and Nr should be programmed to 0x0001 (default values). 90 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x088:0x089 Register Name: ref1_base_freq Default Value: 0x9C40 Type:R/W Bit Field Function Name 15:0 Ref1 base frequency Br1 Description See description for registers at address 0x080:0x081 Register_Address: 0x08A:0x08B Register Name: ref1_freq_multiple Default Value: 0x01E6 Type:R/W Bit Field Function Name 15:0 Ref1 base frequency multiple Kr1 Description See description for registers at address 0x082:0x083 Register_Address: 0x08C:0x08F Register Name: ref1_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Ref1 FEC ratio numerator Mr1 15:0 Ref1 FEC ratio denominator Nr1 Description See description for registers at address 0x084:0x087 Register_Address: 0x090:0x091 Register Name: ref2_base_freq Default Value: 0x9C40 Type:R/W Bit Field 15:0 Function Name Ref2 base frequency Br2 Description See description for registers at address 0x080:0x081 91 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x092:0x093 Register Name: ref2_freq_multiple Default Value: 0x01E6 Type:R/W Bit Field Function Name 15:0 Ref2 base frequency multiple Kr2 Description See description for registers at address 0x082:0x083 Register_Address: 0x094:0x097 Register Name: ref2_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Ref2 FEC ratio numerator Mr2 15:0 Ref2 FEC ratio denominator Nr2 Description See description for registers at address 0x084:0x087 Register_Address: 0x098:0x099 Register Name: ref3_base_freq Default Value: 0x9C40 Type:R/W Bit Field Function Name 15:0 Ref3 base frequency Br3 Description See description for registers at address 0x080:0x081 Register_Address: 0x09A:0x09B Register Name: ref3_freq_multiple Default Value: 0x01E6 Type:R/W Bit Field Function Name 15:0 Ref3 base frequency multiple Kr3 Description See description for registers at address 0x082:0x083 92 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x09C:0x09F Register Name: ref3_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Ref3 FEC ratio numerator Mr3 15:0 Ref3 FEC ratio denominator Nr3 Description See description for registers at address 0x084:0x087 Register_Address: 0x0A0:0x0A1 Register Name: ref4_base_freq Default Value: 0x9C40 Type:R/W Bit Field Function Name 15:0 Ref4 base frequency Br4 Description See description for registers at address 0x080:0x081 Register_Address: 0x0A2:0x0A3 Register Name: ref4_freq_multiple Default Value: 0x01E6 Type:R/W Bit Field Function Name 15:0 Ref4 base frequency multiple Kr4 Description See description for registers at address 0x082:0x083 93 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x0A4:0x0A7 Register Name: ref4_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Ref4 FEC ratio numerator Mr4 15:0 Ref4 FEC ratio denominator Nr4 Description See description for registers at address 0x084:0x087 Register_Address: 0x0A8:0x0A9 Register Name: ref5_base_freq Default Value: 0x9C40 Type:R/W Bit Field Function Name 15:0 Ref5 base frequency Br5 Description See description for registers at address 0x080:0x081 Register_Address: 0x0AA:0x0AB Register Name: ref5_freq_multiple Default Value: 0x01E6 Type:R/W Bit Field Function Name 15:0 Ref5 base frequency multiple Kr5 Description See description for registers at address 0x082:0x083 94 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x0AC:0x0AF Register Name: ref5_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Ref5 FEC ratio numerator Mr5 15:0 Ref5 FEC ratio denominator Nr5 Description See description for registers at address 0x084:0x087 Register_Address: 0x0B0:0x0B1 Register Name: ref6_base_freq Default Value: 0x9C40 Type:R/W Bit Field Function Name 15:0 Ref6 base frequency Br6 Description See description for registers at address 0x080:0x081 Register_Address: 0x0B2:0x0B3 Register Name: ref6_freq_multiple Default Value: 0x01E6 Type:R/W Bit Field 15:0 Function Name Ref6 base frequency multiple Kr6 Description See description for registers at address 0x082:0x083 95 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x0B4:0x0B7 Register Name: ref6_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Ref6 FEC ratio numerator Mr6 15:0 Ref6 FEC ratio denominator Nr6 Description See description for registers at address 0x084:0x087 Register_Address: 0x0B8:0x0B9 Register Name: ref7_base_freq Default Value: 0x9C40 Type:R/W Bit Field Function Name 15:0 Ref7 base frequency Br7 Description See description for registers at address 0x080:0x081. Register_Address: 0x0BA:0x0BB Register Name: ref7_freq_multiple Default Value: 0x01E6 Type:R/W Bit Field Function Name 15:0 Ref7 base frequency multiple Kr7 Description See description for registers at address 0x082:0x083 96 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x0BC:0x0BF Register Name: ref7_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name Description 31:16 Ref7 FEC ratio numerator Mr7 15:0 Ref7 FEC ratio denominator Nr7 See description for registers at address 0x084:0x087 Register_Address: 0x0FF Register Name: page_sel_register Default Value: 0x00 Type:R/W Bit Field 7:0 Function Name Page Selection register Description Unsigned binary value of these bits represents selected page for SPI access. See register at address 0x07F for details Register_Address: 0x100 Register Name: dpll0_ctrl Default Value: 0x0C Type:R/W Bit Field 7:5 Function Name DPLL loop filter corner frequency selection Description These bits control DPLL0 loop filter corner frequency. Bit selection: 000 = 14 Hz 001 = 28 Hz 010 = 56 Hz 011 = 112 Hz 100 = 224 Hz 101 = 448 Hz 110 = 896 Hz 111 = 5.2 Hz 97 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x100 Register Name: dpll0_ctrl Default Value: 0x0C Type:R/W Bit Field 4 3:2 Function Name Description Time Interval Error (TIE) clear enable This bit controls the DPLL0 output to input alignment. When this bit is set to high, the DPLL0 will align its outputs to the reset position (specified by appropriate phase shift selection). This bit should be set when initial output to input alignment is desired after numerous reference rearrangement. To achieve 'hitless' reference switch, this bit has to be kept low. DPLL0 Phase Slope Limiter These bits control DPLL0 phase slope limiter. Bit selection: 00 = 61 usec/sec 01 = 7.5 usec/sec 10 = 0.885 usec/sec 11 = unlimited (1/256) Note: Under certain configurations, the output of the DPLL may exceed these phase slope limit values. This depends on the input transient (phase or frequency) and the bandwidth of the DPLL. 1:0 Reserved Leave as default Register_Address: 0x102 Register Name: dpll0_pull_in_hold_in Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:3 Reserved Leave as default 2:0 DPLL0 Pull-in Hold-in selection register These bits control DPLL0 pull-in / hold-in range selection. Bit selection: 000 = +/- 12 ppm 001 = +/- 52 ppm 010 = +/- 83 ppm 011 = +/- 130 ppm 100 = +/- 400 ppm 101 = reserved 110 = reserved 111 = unlimited (1/256) 98 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x103 Register Name: dpll0_mode_refsel Default Value: 0x03 Type:R/W Bit Field 7:4 3 2:0 Function Name Description Reference selection When the 'DPLL0 mode' bits of this register (bits 2:0) are set to '10' (forced reference mode), these bits specify which reference the DPLL0 is forced to select. When the forced reference fails, the DPLL0 will go into holdover mode When the 'DPLL0 mode' bits of this register are set to are set to anything other than forced reference mode, these bits are ignored. Reserved Leave as default DPLL0 Mode These bits determine DPLL0 mode of operation. Selection: 000 = freerun mode 001 = forced holdover mode 010 = forced reference lock mode 011 = automatic mode 100 = NCO mode 101,110, 111 = reserved For more information on these modes of operation, please see Section 4.3.2, "DPLL States" on page 20. Register_Address: 0x104 Register Name: dpll0_refsel_stat Default Value: 0x00 Type:R Bit Field Function Name Description 7:4 Reserved Leave as default 3:0 Selected reference status When the 'DPLL0 mode' bits of the dpll0_mode_refsel register are set to '11' (automatic mode), these bits represent the selected reference status, i.e. '0000' = Ref0, '0001' = Ref1 and so on. 99 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x105 Register Name: dpll0_ref_priority1_0 Default Value: 0x10 Type:R/W Bit Field 7:4 Function Name priority selection Ref1 Description When the DPLL0 is in automatic mode of operation programmed in the DPLL0 Mode field in dpll_mode_refsel , these bits are used to select priority of Ref1 for DPLL. 0000 is highest priority and 1110 is lowest priority. Setting these bits to 1111 will disable Ref1 reference (that will prevent DPLL0 from locking to Ref1). When references are programmed to have different priority number, the DPLL0 will perform 'REVERTIVE' switching between them. This means that the DPLL0 will always switch to the highest priority reference available with lowest priority number) when that reference becomes available (input is valid). When two or more input references are programmed to have same priority number, the DPLL0 will perform 'NON-REVERTIVE' switching between them. This means that the DPLL0 will not perform a switch to another reference with the same priority when that reference becomes available. Combinations of the same and different priority numbers can be used, such that the DPLL0 performs revertive switching between different priority references, but non-revertive switching among references with the same priority. Example: if Ref0 has priority 0 (highest), Ref1, Ref2 and Ref3 have priority 1. Whenever Ref0 becomes available, DPLL0 will switch to it. But, if Ref0 is not available, DPLL0 will remain locking to currently selected reference (e.g. Ref3) even when Ref1 or Ref2 become available. 3:0 priority selection Ref0 See description for bits 7:4 above Register_Address: 0x106 Register Name: dpll0_ref_priority3_2 Default Value: 0x32 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref3 See description for register at address 0x105 3:0 priority selection Ref2 See description for register at address 0x105 100 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x107 Register Name: dpll0_ref_priority5_4 Default Value: 0x54 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref5 See description for register at address 0x105 3:0 priority selection Ref4 See description for register at address 0x105 Register_Address: 0x108 Register Name: dpll0_ref_priority7_6 Default Value: 0x76 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref7 See description for register at address 0x105 3:0 priority selection Ref6 See description for register at address 0x105 Register_Address: 0x10D Register Name: dpll0_ref_fail_mask Default Value: 0x87 Type:R/W Bit Field 7 Function Name refswitch mask GST Description When set high, this bit allows the selected reference GST failure to cause the DPLL0 to perform a reference switch. When set low, the selected reference GST failure will be masked and DPLL0 will not perform a reference switch due to a GST failure. 0 = mask 1 = enable (activate) 101 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x10D Register Name: dpll0_ref_fail_mask Default Value: 0x87 Type:R/W Bit Field Function Name Description 6 refswitch mask CFM When set high, this bit allows the selected reference CFM failure to cause DPLL0 to perform a reference switch. When low, the selected reference CFM failure will be masked and DPLL0 will not perform a reference switch due to a CFM failure. 0 = mask 1 = enable (activate) 5 refswitch mask SCM When set high, this bit allows the selected reference SCM failure to cause DPLL0 to perform a reference switch. When low, the selected reference SCM failure will be masked and DPLL0 will not perform a reference switch due to a SCM failure. 0 = mask 1 = enable (activate) 4 refswitch mask LOS When set high, this bit allows the selected reference LOS failure to cause DPLL0 to perform reference switch. When low, the selected reference LOS failure will be masked and DPLL0 will not perform a reference switch due to a LOS failure. 0 = mask 1 = enable (activate) 3 holdover mask GST When set high, this bit allows the selected reference GST failure to cause DPLL0 to go into holdover. When low, the selected reference GST failure will be masked and DPLL0 will not go into holdover due to a GST failure. 0 = mask 1 = enable (activate) Note: This bit should never be programmed to 1 if neither 'holdover mask CFM' nor 'holdover mask SCM' bit is programmed to 1 (e.g. bits 3:1 should never be programmed to '100'). 2 holdover mask CFM When set high, this bit allows the selected reference CFM failure to cause DPLL0 to go into holdover. When low, the selected reference CFM failure will be masked and DPLL0 will not go into holdover due to a CFM failure. 0 = mask 1 = enable (activate) 1 holdover mask SCM When set high, this bit allows the selected reference SCM failure to cause DPLL0 to go into holdover. When low, the selected reference SCM failure will be masked and DPLL0 will not go into holdover due to a SCM failure. 0 = mask 1 = enable (activate) 102 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x10D Register Name: dpll0_ref_fail_mask Default Value: 0x87 Type:R/W Bit Field 0 Function Name holdover mask LOS Description When set high, this bit allows the selected reference external LOS signal to cause DPLL0 to go into holdover. When low, selected reference external LOS signal will be masked and DPLL0 will not go to holdover when the LOS signal is active high. 0 = mask 1 = enable (activate) Register_Address: 0x10E Register Name: dpll0_pfm_fail_mask Default Value: 0x01 Type:R/W Bit Field 7:5 4 3:1 0 Function Name Description Reserved Leave as default refswitch mask PFM When set high, this bit allows selected reference PFM failure to cause DPLL to perform a reference switch. When low, selected reference PFM failure will be masked and DPLL will not perform reference switch due to a PFM failure. Reserved Leave as default holdover mask PFM When set high, this bit allows selected reference PFM failure to cause DPLL to go into holdover. When low, selected reference PFM failure will be masked and DPLL will not go into holdover due to the PFM failure. 103 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x10F Register Name: dpll0_ho_edge_sel Default Value: 0x0B Type:R/W Bit Field 7:6 Function Name DPLL0 reference edge selection Description These bits define the selected reference edge sensitivity 00 = positive (rising) edge 01 = negative (falling) edge 10 = low pulse 11 = high pulse The low pulse and the high pulse options select a middle sample point halfway between the clock edges. 5 4:0 Reserved Leave as default DPLL0 holdover storage delay These bits specify the DPLL0 holdover storage delay as per the following formula, using E8 series style: Value = round( 8 * log(StorageDelay/10) ), where StorageDelay is given in ms Example, if desired delay is 10ms, value to be written to this register is 0x00, for 1 second the value is 0x10, while for 75 seconds the value is 0x1F. The default value of 0x0B corresponds to 237ms. Register_Address: 0x120 Register Name: dpll1_ctrl Default Value: 0x0C Type:R/W Bit Field Function Name Description 7:5 DPLL1 loop filter corner frequency selection See description for register at address 0x100 4 Time Interval Error (TIE) clear enable See description for register at address 0x100 3:2 DPLL1 Phase Slope Limiter See description for register at address 0x100 1:0 Reserved Leave as default 104 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x122 Register Name: dpll1_pull_in_hold_in Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:3 Reserved Leave as default 2:0 DPLL1 Pull-in Hold-in selection register See description for register at address 0x102 Register_Address: 0x123 Register Name: dpll1_mode_refsel Default Value: 0x03 Type:R/W Bit Field 7:4 3 2:0 Function Name Description Reference selection See description for register at address 0x103 Reserved Leave as default DPLL1 Mode See description for register at address 0x103 Register_Address: 0x124 Register Name: dpll1_refsel_stat Default Value: 0x00 Type:R Bit Field Function Name Description 7:4 Reserved Leave as default 3:0 Selected reference status See description for register at address 0x104 105 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x125 Register Name: dpll1_ref_priority1_0 Default Value: 0x10 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref1 See description for register at address 0x105 3:0 priority selection Ref0 See description for register at address 0x105 Register_Address: 0x126 Register Name: dpll1_ref_priority3_2 Default Value: 0x32 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref3 See description for register at address 0x105 3:0 priority selection Ref2 See description for register at address 0x105 Register_Address: 0x127 Register Name: dpll1_ref_priority5_4 Default Value: 0x54 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref5 See description for register at address 0x105 3:0 priority selection Ref4 See description for register at address 0x105 106 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x128 Register Name: dpll1_ref_priority7_6 Default Value: 0x76 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref7 See description for register at address 0x105 3:0 priority selection Ref6 See description for register at address 0x105 Register_Address: 0x12D Register Name: dpll1_ref_fail_mask Default Value: 0x87 Type:R/W Bit Field Function Name Description 7 refswitch mask GST See description for register at address 0x10D 6 refswitch mask CFM See description for register at address 0x10D 5 refswitch mask SCM See description for register at address 0x10D 4 refswitch mask LOS See description for register at address 0x10D 3 holdover mask GST See description for register at address 0x10D 2 holdover mask CFM See description for register at address 0x10D 1 holdover mask SCM See description for register at address 0x10D 0 holdover mask LOS See description for register at address 0x10D Register_Address: 0x12E Register Name: dpll1_pfm_fail_mask Default Value: 0x01 Type:R/W Bit Field 7:5 Function Name Reserved Description Leave as default 107 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x12E Register Name: dpll1_pfm_fail_mask Default Value: 0x01 Type:R/W Bit Field 4 3:1 0 Function Name Description refswitch mask PFM See description for register at address 0x10E Reserved Leave as default holdover mask PFM See description for register at address 0x10E Register_Address: 0x12F Register Name: dpll1_ho_edge_sel Default Value: 0x0B Type:R/W Bit Field 7:6 5 4:0 Function Name Description DPLL1 reference edge selection See description for register at address 0x10F Reserved Leave as default DPLL1 holdover storage delay See description for register at address 0x10F Register_Address: 0x140 Register Name: dpll2_ctrl Default Value: 0x0C Type:R/W Bit Field Function Name Description 7:5 DPLL2 loop filter corner frequency selection See description for register at address 0x100 4 Time Interval Error (TIE) clear enable See description for register at address 0x100 3:2 DPLL2 Phase Slope Limiter See description for register at address 0x100 1:0 Reserved Leave as default 108 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x142 Register Name: dpll2_pull_in_hold_in Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:3 Reserved Leave as default 2:0 DPLL2 Pull-in Hold-in selection register See description for register at address 0x102 Register_Address: 0x143 Register Name: dpll2_mode_refsel Default Value: 0x03 Type:R/W Bit Field 7:4 3 2:0 Function Name Description Reference selection See description for register at address 0x103 Reserved Leave as default DPLL2 Mode See description for register at address 0x103 Register_Address: 0x144 Register Name: dpll2_refsel_stat Default Value: 0x00 Type:R Bit Field Function Name Description 7:4 Reserved Leave as default 3:0 Selected reference status See description for register at address 0x104 109 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x145 Register Name: dpll2_ref_priority1_0 Default Value: 0x10 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref1 See description for register at address 0x105 3:0 priority selection Ref0 See description for register at address 0x105 Register_Address: 0x146 Register Name: dpll2_ref_priority3_2 Default Value: 0x32 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref3 See description for register at address 0x105 3:0 priority selection Ref2 See description for register at address 0x105 Register_Address: 0x147 Register Name: dpll2_ref_priority5_4 Default Value: 0x54 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref5 See description for register at address 0x105 3:0 priority selection Ref4 See description for register at address 0x105 110 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x148 Register Name: dpll2_ref_priority7_6 Default Value: 0x76 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref7 See description for register at address 0x105 3:0 priority selection Ref6 See description for register at address 0x105 Register_Address: 0x14D Register Name: dpll2_ref_fail_mask Default Value: 0x87 Type:R/W Bit Field Function Name Description 7 refswitch mask GST See description for register at address 0x10D 6 refswitch mask CFM See description for register at address 0x10D 5 refswitch mask SCM See description for register at address 0x10D 4 refswitch mask LOS See description for register at address 0x10D 3 holdover mask GST See description for register at address 0x10D 2 holdover mask CFM See description for register at address 0x10D 1 holdover mask SCM See description for register at address 0x10D 0 holdover mask LOS See description for register at address 0x10D Register_Address: 0x14E Register Name: dpll2_pfm_fail_mask Default Value: 0x01 Type:R/W Bit Field 7:5 4 3:1 Function Name Description Reserved Leave as default refswitch mask PFM See description for register at address 0x10E Reserved Leave as default 111 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x14E Register Name: dpll2_pfm_fail_mask Default Value: 0x01 Type:R/W Bit Field 0 Function Name holdover mask PFM Description See description for register at address 0x10E Register_Address: 0x14F Register Name: dpll2_ho_edge_sel Default Value: 0x0B Type:R/W Bit Field 7:6 5 4:0 Function Name Description DPLL2 reference edge selection See description for register at address 0x10F Reserved Leave as default DPLL2 holdover storage delay See description for register at address 0x10F Register_Address: 0x160 Register Name: dpll3_ctrl Default Value: 0x0C Type:R/W Bit Field Function Name Description 7:5 DPLL3 loop filter corner frequency selection See description for register at address 0x100 4 Time Interval Error (TIE) clear enable See description for register at address 0x100 3:2 DPLL3 Phase Slope Limiter See description for register at address 0x100 1:0 Reserved Leave as default 112 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x162 Register Name: dpll3_pull_in_hold_in Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:3 Reserved Leave as default 2:0 DPLL3 Pull-in Hold-in selection register See description for register at address 0x102 Register_Address: 0x163 Register Name: dpll3_mode_refsel Default Value: 0x03 Type:R/W Bit Field 7:4 3 2:0 Function Name Description Reference selection See description for register at address 0x103 Reserved Leave as default DPLL3 Mode See description for register at address 0x103 Register_Address: 0x164 Register Name: dpll3_refsel_stat Default Value: 0x00 Type:R Bit Field Function Name Description 7:4 Reserved Leave as default 3:0 Selected reference status See description for register at address 0x104 113 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x165 Register Name: dpll3_ref_priority1_0 Default Value: 0x10 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref1 See description for register at address 0x105 3:0 priority selection Ref0 See description for register at address 0x105 Register_Address: 0x166 Register Name: dpll3_ref_priority3_2 Default Value: 0x32 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref3 See description for register at address 0x105 3:0 priority selection Ref2 See description for register at address 0x105 Register_Address: 0x167 Register Name: dpll3_ref_priority5_4 Default Value: 0x54 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref5 See description for register at address 0x105 3:0 priority selection Ref4 See description for register at address 0x105 114 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x168 Register Name: dpll3_ref_priority7_6 Default Value: 0x76 Type:R/W Bit Field Function Name Description 7:4 priority selection Ref7 See description for register at address 0x105 3:0 priority selection Ref6 See description for register at address 0x105 Register_Address: 0x16D Register Name: dpll3_ref_fail_mask Default Value: 0x87 Type:R/W Bit Field Function Name Description 7 refswitch mask GST See description for register at address 0x10D 6 refswitch mask CFM See description for register at address 0x10D 5 refswitch mask SCM See description for register at address 0x10D 4 refswitch mask LOS See description for register at address 0x10D 3 holdover mask GST See description for register at address 0x10D 2 holdover mask CFM See description for register at address 0x10D 1 holdover mask SCM See description for register at address 0x10D 0 holdover mask LOS See description for register at address 0x10D Register_Address: 0x16E Register Name: dpll3_pfm_fail_mask Default Value: 0x01 Type:R/W Bit Field 7:5 4 Function Name Description Reserved Leave as default refswitch mask PFM See description for register at address 0x10E 115 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x16E Register Name: dpll3_pfm_fail_mask Default Value: 0x01 Type:R/W Bit Field 3:1 0 Function Name Description Reserved Leave as default holdover mask PFM See description for register at address 0x10E Register_Address: 0x16F Register Name: dpll3_ho_edge_sel Default Value: 0x0B Type:R/W Bit Field 7:6 5 4:0 Function Name Description DPLL3 reference edge selection See description for register at address 0x10F Reserved Leave as default DPLL3 holdover storage delay See description for register at address 0x10F Register_Address: 0x17F Register Name: page_sel_register Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:0 Page Selection register See description for register at address 0x7F 116 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x180 Register Name: dpll_hold_lock_status Default Value: 0x00 Type::Sticky R/W Bit Field 7 Function Name DPLL3 lock status Description When DPLL3 is locked to a reference, the device will set this bit high. This bit is 'sticky', so it will stay high until the user clears it. Note: This bit is not maskable, i.e. whenever DPLL3 is locked, it will be set regardless of any mask bits. 6 DPLL3 holdover status This bit is set high when DPLL3 is in holdover mode. This bit is 'sticky', so it will stay high until the user clears it. Note: This bit is not maskable, i.e. whenever DPLL3 is in holdover, it will be set regardless of any mask bits. 5 DPLL2 lock status See description for bit 7 4 DPLL2 holdover status See description for bit 7 3 DPLL1 lock status See description for bit 7 2 DPLL1 holdover status See description for bit 7 1 DPLL0 lock status See description for bit 7 0 DPLL0 holdover status See description for bit 7 Register_Address: 0x182 Register Name: dpll_config Default Value: 0x04 Type: R/W Bit Field Function Name Description 7:3 Reserved Leave as default 2:0 DPLL Configuration Selects which DPLLs are enabled Selection: 000 = none 001 = DPLL0 010 = DPLL0 and DPLL1 011 = DPLL0, DPLL1 and DPLL2 100 = all four DPLLs are enabled 101-111 = reserved 117 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x183 Register Name: dpll_lock_selection Default Value: 0xAA Type: R/W Bit Field Function Name Description 7:6 DPLL3 lock selection These bits select DPLL3 lock indicator condition (appearing in the dpll_hold_lock_status register). Selection: 00 = phase error is smaller than 36us per 10s 01 = phase error is smaller than 1 us during 1 s 10 = phase error is smaller than 10 us during 1 s 11 = phase error is smaller than 10 us during 10 s 5:4 DPLL2 lock selection See description for bits 7:6 3:2 DPLL1 lock selection See description for bits 7:6 1:0 DPLL0 lock selection See description for bits 7:6 Register_Address: 0x18D:0x191 Register Name: dpll0_df_offset Default Value: 0x0000000000 Type: W Bit Field 39:0 Function Name NCO0 Delta Frequency offset Description When DPLL0 is programmed into NCO0 mode (dpll0_mode_refsel register), this register contains a 2's complement binary value of delta frequency offset. This register controls delta frequency of Synthesizers that are associated with the DPLL0/NCO0. Delta frequency is expressed in steps of +/- 2^-40 of nominal setting. The output frequency should be calculated as per formula: f_out = (1 - X/2^40)*f_nom where, X is 2's complement number specified in this register, f_nom is the nominal frequency set by Bs, Ks, Ms, Ns and postdivider number for particular Synthesizer and f_out is the desired output frequency Note 1: Delta frequency offset combined with the Synthesizer Frequency should be between 1.0 GHz and 1.5 GHz. Note 2: The delta frequency offset should not exceed +/-5000 ppm of the nominal value. Note 3: The delta frequency offset should not be changed by more than 7 ppm in a single update. 118 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x192:0x196 Register Name: dpll1_df_offset Default Value: 0x0000000000 Type: W Bit Field 39:0 Function Name NCO1 Delta Frequency offset Description See description of the register at address 0x18D:0x191 Register_Address: 0x197:0x19B Register Name: dpll2_df_offset Default Value: 0x0000000000 Type: W Bit Field 39:0 Function Name NCO2 Delta Frequency offset Description See description of the register at address 0x18D:0x191 Register_Address: 0x19C:0x1A0 Register Name: dpll3_df_offset Default Value: 0x0000000000 Type: W Bit Field 39:0 Function Name NCO3 Delta Frequency offset Description See description of the register at address 0x18D:0x191 Register_Address: 0x1B0 Register Name: synth_drive_pll Default Value: 0xE4 Type:R/W Bit Field 7:6 Function Name DPLL for Synth 3 Description Selects DPLL that drives Synthesizer 3 Selection: 00 = DPLL0 01 = DPLL1 10 = DPLL2 11 = DPLL3 119 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1B0 Register Name: synth_drive_pll Default Value: 0xE4 Type:R/W Bit Field Function Name Description 5:4 DPLL for Synth 2 See description for bits 7:6 3:2 DPLL for Synth 1 See description for bits 7:6 1:0 DPLL for Synth 0 See description for bits 7:6 Register_Address: 0x1B1 Register Name: synth_enable Default Value: 0x03 Type:R/W Bit Field 7:4 Function Name Description Reserved Leave as default 3 Synth3 Enable When this bit is set high, Synthesizer 3 is enabled. When low, Synthesizer 3 is disabled. 2 Synth2 Enable See description for bit 3 1 Synth1 Enable See description for bit 3 0 Synth0 Enable See description for bit 3 Register_Address: 0x1B6 Register Name: sync_fail_flag_status Default Value: 0x00 Type:R/W Bit Field 7:4 Function Name Description Reserved Leave as default 3 Synth3 APLL syncfailFlag status When high, this bit indicates that Synth3 APLL has lost lock, therefore generating wrong output frequency. This sticky bit is cleared by the clear_sync_fail_flag register bit. To check the status, first clear the bit using clear_sync_fail_flag register bit 3 for Synth3, then check the bit from this register. Note: This bit will be set upon power up or device reset 2 Synth2 APLLsyncfailFlag status See description for bit 3 1 Synth1 APLL syncfailFlag status See description for bit 3 120 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1B6 Register Name: sync_fail_flag_status Default Value: 0x00 Type:R/W Bit Field 0 Function Name Synth0 APLL syncfailFlag status Description See description for bit 3 Register_Address: 0x1B7 Register Name: clear_sync_fail_flag Default Value: 0x00 Type:R/W Bit Field 7:4 Function Name Description Reserved Leave as default 3 Synth3 APLL clear syncfailFlag When high, this bit clears the syncFailFlag for Synth3 APLL. Note: after clearing the syncFailFlag, this bit MUST be set to low for normal device operation 2 Synth2 APLL clear syncfailFlag See description for bit 3 1 Synth1 APLL clear syncfailFlag See description for bit 3 0 Synth0 APLL clear syncfailFlag See description for bit 3 121 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1B8:0x1B9 Register Name: synth0_base_freq Default Value: 0x9C40 Type:R/W Bit Field 15:0 Function Name Synth0 base frequency Bs0 Description Unsigned binary value of these bits represents Synthesizer 0 base frequency Bs in Hz. Examples of values for Bs that can be programmed: 0x1F40 for 8kHz, 0x61A8 for 25kHz, 0x9C40 for 40kHz. Note 1: Br has to be directly divisible from 1600000000, i.e. mod (1600000000, Br) has to be 0. The evaluation board GUI can generate recommended Br, Kr, Mr and Nr values for required input frequency. Note 2: in order to write e.g. 0x9C40 to this register (and any other register whose value is larger than 8 bits), 0x9C has to be written to the lower address and 0x40 to the upper address (big endian) with the 0x40 (LSBs) written last. 122 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1BA:0x1BB Register Name: synth0_freq_multiple Default Value: 0x0798 Type:R/W Bit Field 15:0 Function Name Synth0 base frequency multiple Ks0 Description Unsigned binary value that represents Synthesizer 0 base frequency multiplication number. For a regular (non-FEC) synthesizer frequency, the 'Base frequency' number Bs is multiplied by the 'Base frequency multiple' number Ks, and multiplied by 16 is equal the synthesizer frequency in Hz. The synthesizer frequency must be programmed to be between 1 GHz and 1.5 GHz, so: Bs x Ks x 16 x Ms / Ns has to be between 1 000 000 000 and 1 500 000 000 Hz. Examples of appropriate values that can be programmed for Bs and Ks to get desired synthesizer frequency: Synthesizer frequency Base frequency Bs Base frequency multiple Ks 1.048576 GHz 8 kHz (0x1F40) 8192 (0x2000) 1.24416 GHz 40 kHz (0x9C40) 1944 (0x0798) 1.25 GHz 25 kHz (0x61A8) 3125 (0x0C35) Note 1: Br has to be directly divisible from 1600000000, i.e. mod (1600000000, Br) has to be 0. The evaluation board GUI can generate recommended Br, Kr, Mr and Nr values for required input frequency. Note 2: For proper operation of the synthesizer, Bs x Ks x Ms / Ns must not be a multiple any of the following frequencies: 65,536,000; 69,632,000; 73,728,000; 77,824,000; 81,920,000; 86,016,000 or 90,112,000. 123 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1BC:0x1BF Register Name: synth0_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field 31:16 Function Name Synth0 FEC ratio numerator Ms0 Description The unsigned binary value of Ms bits, in combination with unsigned binary value of Ns bits represents Synthesizer 0 FEC multiplication ratio. Synthesizer 0 FEC frequencies are calculated using the following formula: Synth_freq [Hz] = Bs x Ks x 16 x Ms / Ns For regular (non-FEC) synthesizer frequencies, Ms and Ns should be programmed to be 0x0001 Examples of some synthesizer FEC frequencies and appropriate values for Bs, Ks, Ms and Ns registers to get those FEC frequencies are: 15:0 Synth0 FEC ratio denominator Ns0 a) OC-192 mode, standard EFEC for long reach: Desired frequency - 155.52MHz x 255/237 Synth frequency - 1.24416 GHz x 255/237 Base freq. Bs - 40 kHz (0x9C40) Base freq. mul. Ks - 1944 (0x0798) FEC ratio num. Ms - 255 (0x00FF) FEC ratio den. - 237 (0x00ED) Post div PA - 8 b) Long reach 10GE mode, double rate conversion (synth freq : 1250MHz x 66/64 x 255/238): Desired frequency - 156.25MHz x 66/64 x 255/238 Base frequency Bsr - 25 kHz (0x061A8 Base freq mul. Ks - 3125 (0x0C35) FEC ratio num. Ms - 66x255 (0x41BE) FEC ratio den. Ns - 64x238 (0x3B80) Post div PA - 8 Register_Address: 0x1C0:0x1C1 Register Name: synth1_base_freq Default Value: 0x61A8 Type:R/W Bit Field 15:0 Function Name Synth1 base frequency Bs1 Description See description for register at address 0x1B8:0x1B9 124 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1C2:0x1C3 Register Name: synth1_freq_multiple Default Value: 0x0C35 Type:R/W Bit Field 15:0 Function Name Synth1 base frequency multiple Ks1 Description See description for register at address 0x1BA:0x1BB Register_Address: 0x1C4:0x1C7 Register Name: synth1_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Synth1 FEC ratio numerator Ms1 15:0 Synth1 FEC ratio denominator Nr1 Description See description for register at address 0x1BC:0x1BF Register_Address: 0x1C8:0x1C9 Register Name: synth2_base_freq Default Value: 0x9C40 Type:R/W Bit Field 15:0 Function Name Synth2 base frequency Bs2 Description See description for register at address 0x1B8:0x1B9 125 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1CA:0x1CB Register Name: synth2_freq_multiple Default Value: 0x0798 Type:R/W Bit Field 15:0 Function Name Synth2 base frequency multiple Ks2 Description See description for register at address 0x1BA:0x1BB Register_Address: 0x1CC:0x1CF Register Name: synth2_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Synth2 FEC ratio numerator Ms2 15:0 Synth2 FEC ratio denominator Nr2 Description See description for register at address 0x1BC:0x1BF Register_Address: 0x1D0:0x1D1 Register Name: synth3_base_freq Default Value: 0x9C40 Type:R/W Bit Field 15:0 Function Name Synth3 base frequency Bs3 Description See description for register at address 0x1B8:0x1B9 126 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x1D2:0x1D3 Register Name: synth3_freq_multiple Default Value: 0x0798 Type:R/W Bit Field 15:0 Function Name Synth3 base frequency multiple Ks3 Description See description for register at address 0x1BA:0x1BB Register_Address: 0x1D4:0x1D7 Register Name: synth3_ratio_M_N Default Value: 0x00010001 Type:R/W Bit Field Function Name 31:16 Synth3 FEC ratio numerator Ms3 15:0 Synth3 FEC ratio denominator Nr3 Description See description for register at address 0x1BC:0x1BF Register_Address: 0x1FF Register Name: page_sel_register Default Value: 0x00 Type:R/W Bit Field 7:0 Function Name Page Selection register Description See description for register at address 0x07F 127 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x200:0x202 Register Name: synth0_post_div_A Default Value: 0x000002 Type:R/W Bit Field 23:20 Function Name Frame pulse or clock selection Description When these bits are programmed '1111' the output clock will be a frame pulse or a low frequency clock (below 1 KHz). Selection between frame pulse and low frequency clock depends on the value of bits 17:16. '1111' and bits[17:16] == '00' : The output is low frequency clock with 50% duty cycle with frequency equal to 2 x Synthesizer 0 base frequency Bs0 (synth0_base_freq register) divided by the value in bits[15:0] of this register. '1111' and bits[17:16] != '00' : output is frame pulse whose width is equal to period of the clock driven from the output selected by bits[17:16] If these bits are different from '1111' than the output is a clock with 50% duty cycle and frequency equal to the Synthesizer0 frequency (1 GHz to 1.5 GHz) divided by the value in bits [23:0] of this register. 19 Frame pulse type Whenever bits[23:20] == '1111' and bits[17:16] != '00' ,this bit is used to select between ST-Bus and GCI frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: ST-Bus frame pulse (frame boundary in the middle of the frame pulse) 1: GCI frame pulse (frame boundary defined by first edge of the frame pulse 18 Frame pulse polarity Whenever bits[23:20] == '1111' and bits[17:16] != '00' this bit is used to select between positive and negative frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: positive frame pulse 1: negative frame pulse Frame pulse reference clock Whenever bits[23:20] == '1111' these bits select between the low frequency clock and a the frame pulse related output clock (The Frame pulse width will be equal to the period of the related output clock). Otherwise it is used as part of divider ratio (bits[23:0]) 17:16 Selection: 00: low frequency clock 01: clock 1 (Synth 0 postdivider B) 10: clock 2 (Synth 0 postdivider C) 11: clock 3 (Synth 0 postdivider D) 128 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x200:0x202 Register Name: synth0_post_div_A Default Value: 0x000002 Type:R/W Bit Field 15:0 Function Name Division or frame pulse rate Description Function of these bits depends on the value in bits[23:20]. Whenever bits[23:20] =='1111' and bits[17:16] != '00' these bits represent the number of periods of the selected clock (bits[17:16]) in between two frame pulses. Whenever bits[23:20] =='1111' and bits[17:16] == '00' these bits represent the division factor for the low frequency output clock. The output is low frequency is equal to 2 x Synthesizer 0 base frequency (synth0_base_freq register) divided by the value stored in these bits. Whenever bits[23:20] !='1111' the value is these bits is part of the output divider (bits[23:0]). The output frequency is then equal to Synthesizer 0 output frequency divided by the value stored in bits[23:0]. Register_Address: 0x203:0x205 Register Name: synth0_post_div_B Default Value: 0x000002 Type:R/W Bit Field 23:20 Function Name Frame pulse or clock selection Description When these bits are programmed '1111' the output clock will be a frame pulse or a low frequency clock (below 1 KHz). Selection between frame pulse and low frequency clock depends on the value of bits 17:16. '1111' and bits[17:16] == '01' : The output is low frequency clock with 50% duty cycle with frequency equal to 2 x Synthesizer 0 base frequency Bs0 (synth0_base_freq register) divided by the value in bits[15:0] of this register. '1111' and bits[17:16] != '01' : output is frame pulse whose width is equal to period of the clock driven from the output selected by bits[17:16] If these bits are different from '1111' than the output is a clock with 50% duty cycle and frequency equal to the Synthesizer0 frequency (1 GHz to 1.5 GHz) divided by the value in bits [23:0] of this register. 19 Frame pulse type Whenever bits[23:20] == '1111' and bits[17:16] != '01' ,this bit is used to select between ST-Bus and GCI frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: ST-Bus frame pulse (frame boundary in the middle of the frame pulse) 1: GCI frame pulse (frame boundary defined by first edge of the frame pulse 129 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x203:0x205 Register Name: synth0_post_div_B Default Value: 0x000002 Type:R/W Bit Field 18 17:16 Function Name Description Frame pulse polarity Whenever bits[23:20] == '1111' and bits[17:16] != '01' this bit is used to select between positive and negative frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: positive frame pulse 1: negative frame pulse Frame pulse reference clock Whenever bits[23:20] == '1111' these bits select between the low frequency clock and a the frame pulse related output clock (The Frame pulse width will be equal to the period of the related output clock). Otherwise it is used as part of divider ratio (bits[23:0]) Selection: 00: clock 0 (Synth 0 postdivider A) 01: low frequency clock 10: clock 2 (Synth 0 postdivider C) 11: clock 3 (Synth 0 postdivider D) 15:0 Division or frame pulse rate Function of these bits depends on the value in bits[23:20]. Whenever bits[23:20] =='1111' and bits[17:16] != '01' these bits represent the number of periods of the selected clock (bits[17:16]) in between two frame pulses. Whenever bits[23:20] =='1111' and bits[17:16] == '01' these bits represent the division factor for the low frequency output clock. The output is low frequency is equal to 2 x Synthesizer 0 base frequency (synth0_base_freq register) divided by the value stored in these bits. Whenever bits[23:20] !='1111' the value is these bits is part of the output divider (bits[23:0]). The output frequency is then equal to Synthesizer 0 output frequency divided by the value stored in bits[23:0]. 130 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x206:0x208 Register Name: synth0_post_div_C Default Value: 0x000040 Type:R/W Bit Field 23:20 Function Name Frame pulse or clock selection Description When these bits are programmed '1111' the output clock will be a frame pulse or a low frequency clock (below 1 KHz). Selection between frame pulse and low frequency clock depends on the value of bits 17:16. '1111' and bits[17:16] == '10' : The output is low frequency clock with 50% duty cycle with frequency equal to 2 x Synthesizer 0 base frequency Bs0 (synth0_base_freq register) divided by the value in bits[15:0] of this register. '1111' and bits[17:16] != '10' : output is frame pulse whose width is equal to period of the clock driven from the output selected by bits[17:16] If these bits are different from '1111' than the output is a clock with 50% duty cycle and frequency equal to the Synthesizer0 frequency (1 GHz to 1.5 GHz) divided by the value in bits [23:0] of this register. 19 Frame pulse type Whenever bits[23:20] == '1111' and bits[17:16] != '10' ,this bit is used to select between ST-Bus and GCI frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: ST-Bus frame pulse (frame boundary in the middle of the frame pulse) 1: GCI frame pulse (frame boundary defined by first edge of the frame pulse 18 Frame pulse polarity Whenever bits[23:20] == '1111' and bits[17:16] != '10' this bit is used to select between positive and negative frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: positive frame pulse 1: negative frame pulse Frame pulse reference clock Whenever bits[23:20] == '1111' these bits select between the low frequency clock and a the frame pulse related output clock (The Frame pulse width will be equal to the period of the related output clock). Otherwise it is used as part of divider ratio (bits[23:0]) 17:16 Selection: 00: clock 0 (Synth 0 postdivider A) 01: clock 1 (Synth 0 postdivider B) 10: low frequency clock 11: clock 3 (Synth 0 postdivider D) 131 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x206:0x208 Register Name: synth0_post_div_C Default Value: 0x000040 Type:R/W Bit Field 15:0 Function Name Division or frame pulse rate Description Function of these bits depends on the value in bits[23:20]. Whenever bits[23:20] =='1111' and bits[17:16] != '10' these bits represent the number of periods of the selected clock (bits[17:16]) in between two frame pulses. Whenever bits[23:20] =='1111' and bits[17:16] == '10' these bits represent the division factor for the low frequency output clock. The output is low frequency is equal to 2 x Synthesizer 0 base frequency (synth0_base_freq register) divided by the value stored in these bits. Whenever bits[23:20] !='1111' the value is these bits is part of the output divider (bits[23:0]). The output frequency is then equal to Synthesizer 0 output frequency divided by the value stored in bits[23:0]. Register_Address: 0x209:0x20B Register Name: synth0_post_div_D Default Value: 0x000040 Type:R/W Bit Field 23:20 Function Name Frame pulse or clock selection Description When these bits are programmed '1111' the output clock will be a frame pulse or a low frequency clock (below 1 KHz). Selection between frame pulse and low frequency clock depends on the value of bits 17:16. '1111' and bits[17:16] == '11' : The output is low frequency clock with 50% duty cycle with frequency equal to 2 x Synthesizer 0 base frequency Bs0 (synth0_base_freq register) divided by the value in bits[15:0] of this register. '1111' and bits[17:16] != '11' : output is frame pulse whose width is equal to period of the clock driven from the output selected by bits[17:16] If these bits are different from '1111' than the output is a clock with 50% duty cycle and frequency equal to the Synthesizer0 frequency (1 GHz to 1.5 GHz) divided by the value in bits [23:0] of this register. 19 Frame pulse type Whenever bits[23:20] == '1111' and bits[17:16] != '11' ,this bit is used to select between ST-Bus and GCI frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: ST-Bus frame pulse (frame boundary in the middle of the frame pulse) 1: GCI frame pulse (frame boundary defined by first edge of the frame pulse 132 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x209:0x20B Register Name: synth0_post_div_D Default Value: 0x000040 Type:R/W Bit Field 18 17:16 Function Name Description Frame pulse polarity Whenever bits[23:20] == '1111' and bits[17:16] != '11' this bit is used to select between positive and negative frame pulse. Otherwise it is used as part of divider ratio (bits[23:0]) 0: positive frame pulse 1: negative frame pulse Frame pulse reference clock Whenever bits[23:20] == '1111' these bits select between the low frequency clock and a the frame pulse related output clock (The Frame pulse width will be equal to the period of the related output clock). Otherwise it is used as part of divider ratio (bits[23:0]) Selection: 00: clock 0 (Synth 0 postdivider A) 01: clock 1 (Synth 0 postdivider B) 10: clock 2 (Synth 0 postdivider C) 11: low frequency clock 15:0 Division or frame pulse rate Function of these bits depends on the value in bits[23:20]. Whenever bits[23:20] =='1111' and bits[17:16] != '11' these bits represent the number of periods of the selected clock (bits[17:16]) in between two frame pulses. Whenever bits[23:20] =='1111' and bits[17:16] == '11' these bits represent the division factor for the low frequency output clock. The output is low frequency is equal to 2 x Synthesizer 0 base frequency (synth0_base_freq register) divided by the value stored in these bits. Whenever bits[23:20] !='1111' the value is these bits is part of the output divider (bits[23:0]). The output frequency is then equal to Synthesizer 0 output frequency divided by the value stored in bits[23:0]. Register_Address: 0x20C:0x20E Register Name: synth1_post_div_A Default Value: 0x000002 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x200:0x202 19 Frame pulse type See description for the register at address 0x200:0x202 18 Frame pulse polarity See description for the register at address 0x200:0x202 17:16 Frame pulse related clock selection See description for the register at address 0x200:0x202 15:0 Frame pulse or divider See description for the register at address 0x200:0x202 133 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x20F:0x211 Register Name: synth1_post_div_B Default Value: 0x000002 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x203:0x205 19 Frame pulse type See description for the register at address 0x203:0x205 18 Frame pulse polarity See description for the register at address 0x203:0x205 17:16 Frame pulse related clock selection See description for the register at address 0x203:0x205 15:0 Frame pulse or divider See description for the register at address 0x203:0x205 Register_Address: 0x212:0x214 Register Name: synth1_post_div_C Default Value: 0x000032 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x206:0x208 19 Frame pulse type See description for the register at address 0x206:0x208 18 Frame pulse polarity See description for the register at address 0x206:0x208 17:16 Frame pulse related clock selection See description for the register at address 0x206:0x208 15:0 Frame pulse or divider See description for the register at address 0x206:0x208 Register_Address: 0x215:0x217 Register Name: synth1_post_div_D Default Value: 0x000032 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x209:0x20B 19 Frame pulse type See description for the register at address 0x209:0x20B 18 Frame pulse polarity See description for the register at address 0x209:0x20B 17:16 Frame pulse related clock selection See description for the register at address 0x209:0x20B 15:0 Frame pulse or divider See description for the register at address 0x209:0x20B 134 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x218:0x21A Register Name: synth2_post_div_A Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x200:0x202 19 Frame pulse type See description for the register at address 0x200:0x202 18 Frame pulse polarity See description for the register at address 0x200:0x202 17:16 Frame pulse related clock selection See description for the register at address 0x200:0x202 15:0 Frame pulse or divider See description for the register at address 0x200:0x202 Register_Address: 0x21B:0x21D Register Name: synth2_post_div_B Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x203:0x205 19 Frame pulse type See description for the register at address 0x203:0x205 18 Frame pulse polarity See description for the register at address 0x203:0x205 17:16 Frame pulse related clock selection See description for the register at address 0x203:0x205 15:0 Frame pulse or divider See description for the register at address 0x203:0x205 Register_Address: 0x21E:0x220 Register Name: synth2_post_div_C Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x206:0x208 19 Frame pulse type See description for the register at address 0x206:0x208 18 Frame pulse polarity See description for the register at address 0x206:0x208 17:16 Frame pulse related clock selection See description for the register at address 0x206:0x208 15:0 Frame pulse or divider See description for the register at address 0x206:0x208 135 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x221:0x223 Register Name: synth2_post_div_D Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x209:0x20B 19 Frame pulse type See description for the register at address 0x209:0x20B 18 Frame pulse polarity See description for the register at address 0x209:0x20B 17:16 Frame pulse related clock selection See description for the register at address 0x209:0x20B 15:0 Frame pulse or divider See description for the register at address 0x209:0x20B Register_Address: 0x224:0x226 Register Name: synth3_post_div_A Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x200:0x202 19 Frame pulse type See description for the register at address 0x200:0x202 18 Frame pulse polarity See description for the register at address 0x200:0x202 17:16 Frame pulse related clock selection See description for the register at address 0x200:0x202 15:0 Frame pulse or divider See description for the register at address 0x200:0x202 Register_Address: 0x227:0x229 Register Name: synth3_post_div_B Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x203:0x205 19 Frame pulse type See description for the register at address 0x203:0x205 18 Frame pulse polarity See description for the register at address 0x203:0x205 17:16 Frame pulse related clock selection See description for the register at address 0x203:0x205 15:0 Frame pulse or divider See description for the register at address 0x203:0x205 136 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x22A:0x22C Register Name: synth3_post_div_C Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x206:0x208 19 Frame pulse type See description for the register at address 0x206:0x208 18 Frame pulse polarity See description for the register at address 0x206:0x208 17:16 Frame pulse related clock selection See description for the register at address 0x206:0x208 15:0 Frame pulse or divider See description for the register at address 0x206:0x208 Register_Address: 0x22D:0x22F Register Name: synth3_post_div_D Default Value: 0x000000 Type:R/W Bit Field Function Name Description 23:20 Frame pulse selection See description for the register at address 0x209:0x20B 19 Frame pulse type See description for the register at address 0x209:0x20B 18 Frame pulse polarity See description for the register at address 0x209:0x20B 17:16 Frame pulse related clock selection See description for the register at address 0x209:0x20B 15:0 Frame pulse or divider See description for the register at address 0x209:0x20B 137 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x234:0x235 Register Name: phase_shift_s0_postdiv_c Default Value: 0x0000 Type:R/W Bit Field 15:13 Function Name Synth0 Divider C quadrature phase shift Description These bits select the quadrature phase shift (in 45 degrees step, from 135 to +135 degrees) for all clocks coming from Synthesizer0 Post Divider C. Selection: 000 = 0 degrees (no shift) 001 = -45 degrees 010 = -90 degrees 011 = -135 degrees 100 = -180 (or 180) degrees 101 = 135 degrees 110 = 90 degrees 111 = 45 degrees Note: Only use the 0b000 selection with 1 Hz output signals 12:0 Synth0 Divider C coarse phase shift 2's complement binary value of these bits represent phase shift in steps of one period of Synthesizer0 frequency for all clocks coming from Synthesizer0 Post Divider C (0=no shift, -1= delay output clock for 1 period, 1 = advance output for 1 period, and so on). Register_Address: 0x236:0x237 Register Name: phase_shift_s0_postdiv_d Default Value: 0x0000 Type:R/W Bit Field Function Name Description 15:13 Synth 0 Divider D quadrature phase shift See description for the register at address 0x234:235 12:0 Synth0 Divider D course phase shift See description for the register at address 0x234:235 Register_Address: 0x23C:0x23D Register Name: phase_shift_s1_postdiv_c Default Value: 0x0000 Type:R/W Bit Field 15:13 Function Name Synth 1 Divider C quadrature phase shift Description See description for the register at address 0x234:235 138 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x23C:0x23D Register Name: phase_shift_s1_postdiv_c Default Value: 0x0000 Type:R/W Bit Field 12:0 Function Name Synth1 Divider C coarse phase shift Description See description for the register at address 0x234:235 Register_Address: 0x23E:0x23F Register Name: phase_shift_s1_postdiv_d Default Value: 0x0000 Type:R/W Bit Field Function Name Description 15:13 Synth1 Divider D quadrature phase shift See description for the register at address 0x234:235 12:0 Synth1 Divider D coarse phase shift See description for the register at address 0x234:235 Register_Address: 0x244:0x245 Register Name: phase_shift_s2_postdiv_c Default Value: 0x0000 Type:R/W Bit Field Function Name Description 15:13 Synth2 Divider C quadrature phase shift See description for the register at address 0x234:235 12:0 Synth2 Divider C coarse phase shift See description for the register at address 0x234:235 Register_Address: 0x246:0x247 Register Name: phase_shift_s2_postdiv_d Default Value: 0x0000 Type:R/W Bit Field Function Name Description 15:13 Synth2 Divider D quadrature phase shift See description for the register at address 0x234:235 12:0 Synth2 Divider D coarse phase shift See description for the register at address 0x234:235 139 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x24C:0x24D Register Name: phase_shift_s3_postdiv_c Default Value: 0x0000 Type:R/W Bit Field Function Name Description 15:13 Synth3 Divider C quadrature phase shift See description for the register at address 0x234:235 12:0 Synth3 Divider C coarse phase shift See description for the register at address 0x234:235 Register_Address: 0x24E:0x24F Register Name: phase_shift_s3_postdiv_d Default Value: 0x0000 Type:R/W Bit Field Function Name Description 15:13 Synth3 Divider D quadrature phase shift See description for the register at address 0x234:235 12:0 Synth3 Divider D course phase shift See description for the register at address 0x234:235 Register_Address: 0x254 Register Name: synth1_0_stop_clk Default Value: 0x00 Type:R/W Bit Field 7:6 Function Name Synth1 Post Divider D stop clock Description Setting of these bits will cause Synthesizer 1 Post Divider D to stop clock on either the rising or falling edge. Selection: 00 - 01 = continuous run (stop clock function is disabled) 10 = stop HPOUTCLK3 on the falling edge (stays low) 11 = stop HPOUTCLK3 on the rising edge (stays high) 5:4 Synth1 Post Divider C stop clock See description for bits 7:6 3:2 Synth0 Post Divider D stop clock See description for bits 7:6 1:0 Synth0 Post Divider C stop clock See description for bits 7:6 140 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x255 Register Name: synth3_2_stop_clk Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:6 Synth3 Post Divider D stop clock See description for register at address 0x254 5:4 Synth3 Post Divider C stop clock See description for register at address 0x254 3:2 Synth2 Post Divider D stop clock See description for register at address 0x254 1:0 Synth2 Post Divider C stop clock See description for register at address 0x254 Register_Address: 0x261 Register Name: hp_diff_en Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 enable HPDIFF7 When this bit is set to high, it will enable HPDIFF7_P and HPDIFF7_N outputs. When low, the outputs are tristated. 6 enable HPDIFF6 See description for bit 7 5 enable HPDIFF5 See description for bit 7 4 enable HPDIFF4 See description for bit 7 3 enable HPDIFF3 See description for bit 7 2 enable HPDIFF2 See description for bit 7 1 enable HPDIFF1 See description for bit 7 0 enable HPDIFF0 See description for bit 7 Register_Address: 0x262 Register Name: hp_cmos_en Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 enable HPOUTCLOCK7 When this bit is set to high, it will enable HPOUTCLK7 output. When low, the output is tristated. 6 enable HPOUTCLOCK6 See description for bit 7 5 enableHPOUTCLOCK5 See description for bit 7 4 enable HPOUTCLOCK4 See description for bit 7 3 enable HPOUTCLOCK3 See description for bit 7 141 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x262 Register Name: hp_cmos_en Default Value: 0x00 Type:R/W Bit Field Function Name Description 2 enable HPOUTCLOCK2 See description for bit 7 1 enable HPOUTCLOCK1 See description for bit 7 0 enable HPOUTCLOCK0 See description for bit 7 Register_Address: 0x266 Register Name: gpio_function_pin0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 GPIO0 control or status select This bit determines whether GPIO0 is input (control) pin or output (status) pin. Selection: 0 = control 1 = status 6:0 GPIO0 table bit address Unsigned binary value of these bits represent the address in the control or status table, depending on 'GPIO0 control or status select' bit. The GPIO control and status tables are specified in 5.3, "GPIO Configuration" Default: No function assigned Register_Address: 0x267 Register Name: gpio_function_pin1 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 GPIO1 control or status select See description for register at address 0x266 bit 7 6:0 GPIO1 table bit address See description for register at address 0x266 bits 6:0 142 Microsemi Corporation ZL30165 Register_Address: 0x268 Register Name: gpio_function_pin2 Default Value: 0x60 Type:R/W Bit Field Function Name Description 7 GPIO2 control or status select See description for register at address 0x266 bit 7 6:0 GPIO2 table bit address See description for register at address 0x266 bits 6:0 Register_Address: 0x269 Register Name: gpio_function_pin3 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 GPIO3 control or status select See description for register at address 0x266 bit 7 6:0 GPIO3 table bit address See description for register at address 0x266 bits 6:0 Register_Address: 0x26A Register Name: gpio_function_pin4 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 GPIO4 control or status select See description for register at address 0x266 bit 7 6:0 GPIO4 table bit address See description for register at address 0x266 bits 6:0 Register_Address: 0x26B Register Name: gpio_function_pin5 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 GPIO5 control or status select See description for register at address 0x266 bit 7 6:0 GPIO5 table bit address See description for register at address 0x266 bits 6:0 143 Microsemi Corporation Data Sheet ZL30165 Data Sheet Register_Address: 0x26C Register Name: gpio_function_pin6 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 GPIO6 control or status select See description for register at address 0x266 bit 7 6:0 GPIO6 table bit address See description for register at address 0x266 bits 6:0 Register_Address: 0x276 Register Name: gpio_in_6_0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 Reserved Leave as default 6 Input value for GPIO6 5 Input value for GPIO5 Logic values seen on pins GPIO6 when gpio_function_pin6 == 0x00 (control mode and function 0) and the bit for GPIO6 is '0' in gpio_out_en_6_0 See description for bit 6 4 Input value for GPIO4 See description for bit 6 3 Input value for GPIO3 See description for bit 6 2 Input value for GPIO2 See description for bit 6 1 Input value for GPIO1 See description for bit 6 0 Input value for GPIO0 See description for bit 6 Register_Address: 0x278 Register Name: gpio_out_6_0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 Reserved Leave as default 6 Set GPIO6 output 5 Set GPIO5 output Sets the output value of GPIO6 when gpio_function_pin6 == 0x00 (status mode and function 0) and the bit for GPIO6 is '1' in gpio_out_en_6_0 See description for bit 6 4 Set GPIO4 output See description for bit 6 3 Set GPIO3 output See description for bit 6 2 Set GPIO2 output See description for bit 6 144 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x278 Register Name: gpio_out_6_0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 1 Set GPIO1 output See description for bit 6 0 Set GPIO0 output See description for bit 6 Register_Address: 0x27A Register Name: gpio_out_en_6_0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 Reserved Leave as default 6 Enable GPIO6 output 5 Enable GPIO5 output If bit is a '0' and gpio_function_pin6 is a 0x00, then GPIO6 is an input and data sensed on GPIO6 is reflected in the gpio_in_6_0 register (bit 6). If bit is a '1' and gpio_function_pin6 is 0x00, then GPIO6 is an output and the value in gpio_out_6_0 (bit 6) driven out on GPIO6. See description for bit 6 4 Enable GPIO4 output See description for bit 6 3 Enable GPIO3 output See description for bit 6 2 Enable GPIO2 output See description for bit 6 1 Enable GPIO1 output See description for bit 6 0 Enable GPIO0 output See description for bit 6 Register_Address: 0x27C Register Name: gpio_latch_6_0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 7 Reserved Leave as default 6 Latch GPIO6 input Set to latch the current value on GPIO6 pin. If this bit is zero, the value in bit 6 of gpio_in_6_0 will change as the logic level on GPIO6 changes. 5 Latch GPIO5 input See description for bit 6 4 Latch GPIO4 input See description for bit 6 3 Latch GPIO3 input See description for bit 6 2 Latch GPIO2 input See description for bit 6 1 Latch GPIO1 input See description for bit 6 145 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x27C Register Name: gpio_latch_6_0 Default Value: 0x00 Type:R/W Bit Field Function Name Description 0 Latch GPIO0 input See description for bit 6 Register_Address: 0x27F Register Name: page_sel_register Default Value: 0x00 Type:R/W Bit Field 7:0 Function Name Page Selection register Description See description for register at address 0x07F Register_Address: 0x2C2 Register Name: dpll0_fast_lock_ctrl Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:1 Reserved Leave as default 0 fast_lock_master_enable This bit is the master-enable control for the fast-lock feature for DPLL0. 0 - Feature disabled 1 - Feature enabled Register_Address: 0x2C5 Register Name: dpll1_fast_lock_ctrl Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:1 Reserved Leave as default 0 fast_lock_master_enable This bit is the master-enable control for the fast-lock feature for DPLL1. 146 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x2C8 Register Name: dpll2_fast_lock_ctrl Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:1 Reserved Leave as default 0 fast_lock_master_enable This bit is the master-enable control for the fast-lock feature for DPLL2. Register_Address: 0x2CB Register Name: dpll3_fast_lock_ctrl Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:1 Reserved Leave as default 0 fast_lock_master_enable This bit is the master-enable control for the fast-lock feature for DPLL3. Register_Address: 0x2D4 Register Name: dpll0_holdover_filt_ctrl Default Value: 0x00 Type:R/W Bit Field 7:4 Function Name Reserved Description Leave as default 147 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x2D4 Register Name: dpll0_holdover_filt_ctrl Default Value: 0x00 Type:R/W Bit Field 3:0 Function Name Holdover Filter Value Description This register specifies the holdover filter bandwidth. The default value of 0x00 means that the filter is bypassed. These are the possible settings (BW = 343/(2^n*2*pi) Hz): Setting 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F BW Bypass (default) 27.3 Hz 13.6 Hz 6.8 Hz 3.4 Hz 1.7 Hz 883 mHz 426 mHz 213 mHz 107 mHz 53.3 mHz 26.6 mHz 13.3 mHz 6.7 mHz 3.3 mHz 1.7 mHz Register_Address: 0x2D5 Register Name: dpll1_holdover_filt_ctrl Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:4 Reserved Leave as default 3:0 Holdover Filter Value See description for register at address 0x2D4 Register_Address: 0x2D6 Register Name: dpll2_holdover_filt_ctrl Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:4 Reserved Leave as default 3:0 Holdover Filter Value See description for register at address 0x2D4 148 Microsemi Corporation ZL30165 Data Sheet Register_Address: 0x2D7 Register Name: dpll3_holdover_filt_ctrl Default Value: 0x00 Type:R/W Bit Field Function Name Description 7:4 Reserved Leave as default 3:0 Holdover Filter Value See description for register at address 0x2D4 Register_Address: 0x2FF Register Name: page_sel_register Default Value: 0x00 Type:R/W Bit Field 7:0 Function Name Page Selection register Description See description for register at address 0x07F 149 Microsemi Corporation ZL30165 9.0 Data Sheet AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter Symbol Min. Max. Units VDD_R -0.5 4.6 V VCORE_R -0.5 2.5 V 1 Supply voltage 2 Core supply voltage 3 Voltage on any digital pin VPIN -0.5 6 V 4 Voltage on osci and osco pin VOSC -0.3 VDD + 0.3 V 5 Storage temperature TST -55 125 C * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated Recommended Operating Conditions* Characteristics 1 Supply voltage 2 Core supply voltage 3 Operating temperature 4 Input voltage Sym Min. Typ. Max. Units VDD 3.135 3.30 3.465 V VCORE 1.71 1.80 1.89 V TA -40 25 85 C VDD-IN 2.97 3.30 3.63 V * Voltages are with respect to ground (GND) unless otherwise stated DC Electrical Characteristics - Power - Core Characteristics 1 2 Core supply current (Vcore) Current for each HP Synthesis Engine Sym Typ. Units ICORE (VDD 3.3V) 75 mA ICORE (VCORE 1.8V) 242 mA ISYN (VDD 3.3V) 54 mA ISYN (VCORE 1.8V) 8 mA 150 Microsemi Corporation Notes ZL30165 Data Sheet DC Electrical Characteristics - Power - Clock Outputs Characteristics 1 Power for each hpdiff clock driver 2 Power for each hpdiff clock driver minus power dissipated in the biasing and load resistors. 3 Power for each hpoutclk clock driver Sym. Typ. Units Notes Phpdiff(VDD 3.3V) 89 mW Including power to biasing and load resistors Phpdiff(VDD 3.3V) 49 mW Without power to biasing and load resistors Phpout(VDD 3.3V) 23 mW CL = 5 pF fout = 20 MHz Typ. Max. DC Electrical Characteristics - Inputs Characteristics Sym. Min. 0.7*VDD 1 CMOS high-level input voltage VCIH 2 CMOS low-level input voltage VCIL 3 CMOS Input leakage current IIL -10 4 Schmitt high-level input voltage for tck, pwr_b, sck_scl, trst_b VSIH 2.0 5 Schmitt low-level input voltage for tck, pwr_b, sck_scl, trst_b VSIL 6 Differential input common mode voltage VCM 7 Differential input voltage difference VID Units Notes V Excluding pins below 0.3*VDD V Excluding pins below 10 A VI = VDD or 0 V V 0.7 V 1.1 2.0 V 0.25 1.0 V Max. Units AC/DC Electrical Characteristics - Master Clock Inputs Characteristics Sym. Min. 0.7*VDD 1 CMOS high-level input voltage (OSCi_3V3) VCIH 2 CMOS low-level input voltage (OSCi_3V3) VCIL 3 Input leakage current (OSCi_3V3) 4 IIL -10 CMOS high-level input voltage (OSCi_1V8) VCIH 1.37 5 CMOS low-level input voltage (OSCi_1V8) VCIL 6 Input leakage current (OSCi_1V8) 7 CMOS high-level input voltage (XOin) IIL -10 VCIH 2.0 151 Microsemi Corporation Typ. Notes V 0.3*VDD V 10 A VI = VDD or 0 V V 0.59 V 10 A V VI = VDD or 0 V ZL30165 Data Sheet AC/DC Electrical Characteristics - Master Clock Inputs Characteristics Sym. 8 CMOS low-level input voltage (XOin) VCIL 9 Input leakage current (XOin) 10 Duty Cycle Min. IIL Typ. Max. Units 0.8 V -10 10 A 40 60 % Notes VI = VDD or 0 V DC Electrical Characteristics - High Performance Outputs Characteristics Sym. Min. 1 HPCMOS High-level output voltage VOH 0.8*VDD 2 HPCMOS Low-level output voltage VOL 3 LVPECL: High-level output voltage VOH_LV 5 LVPECL: Low-level output voltage LVPECL: Differential output voltage* Max. Units Notes V 22 Ohms series CL = 10pF 0.2*VDD V 22 Ohms series CL = 10pF VDD 1.16 VDD 0.88 V RL = 50to VDD - 2V, CL = 1pF VDD 1.55 V ECL VDD 1.81 RL = 50to VDD - 2V, CL = 1pF VOD_LV 0.38 0.94 V RL = 50to VDD - 2V, CL = 1pF PECL 4 Typ. VOL_LVP PECL * IBIS model should be used to estimate differential output voltage for different trace lengths and different output frequencies. VOD 2*VOD Figure 25 - Timing Parameter - Output Differential 152 Microsemi Corporation ZL30165 Data Sheet AC Electrical Characteristics* -Output Timing Parameters Measurement Voltage Levels (see Figure 26) Characteristics Sym. CMOS LVPECL Units 1 Threshold Voltage VT-CMOS VT-LVPECL 0.5*VDD VDD-1.35 V 2 Rise and Fall Threshold Voltage High VHM 0.8*VDD 0.8*VOD_LVPECL V 3 Rise and Fall Threshold Voltage Low VLM 0.2*VDD 0.2*VOD_LVPECL V * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated Timing Reference Points V HM VT VLM ALL SIGNALS tIRF, tORF tIRF, tORF Figure 26 - Timing Parameter Measurement Voltage Levels 153 Microsemi Corporation ZL30165 Data Sheet AC Electrical Characteristics* - Inputs (see Figure 27) Characteristics Symbol Min. Typ. Max. Units 1 Input reference Frequency (CMOS Inputs) 1/tREFP 177.5 MHz 2 Input reference Frequency (LVPECL Inputs) 1/tREFP 750 MHz 3 Input reference pulse width high or low tREFW 0.55 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions AC Electrical Characteristics* - Input To Output Timing (see Figure 27 and Figure 28) Characteristics 1 Input reference to hpoutclk0 (single-ended) output clock (with same frequency) delay 2 Input reference to hpdiff0 (differential) output clock (with same frequency) delay Symbol Min. Typ. Max. Units tHP_REFD -2 0 2 ns tHP_DIFF_REFD -1.2 0 1.6 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. tREFP tREFW tREFW REF<7:0> Output clock with the same frequency as REF tHP_REFD Figure 27 - Input To Output Timing for hpoutclk0 tREFP tREFW tREFW REF<7:0>_P/N Output clock with the same frequency as REF tHP_DIFF_REFD Figure 28 - Input To Output Timing To hpdiff0_P/N 154 Microsemi Corporation ZL30165 Data Sheet AC Electrical Characteristics* - Outputs (see Figure 29). Characteristics Sym. Min. Typ. Max. Units 1 Clock skew between high performance outputs tOUT2OUTD -2 0 2 ns 2 Output clock Duty Cycle - hpdiff tPWH, tPWL 45 50 55 Duty Cycle RL = 50 ohm to VDD - 2V CL = 1pF 3 Output clock Duty Cycle - hpoutclk tPWH, tPWL 40 50 60 Duty Cycle 22 ohm in series CL = 10pF 4 hpdiff (LVPECL) Output clock rise or fall time tr / tf 265 515 ps 5 hpoutclk (LVCMOS) clock rise and fall time tr / tf 620 1490 ps 6 Output Clock Frequency (hpdiff) Fhpdiff 750 MHz 7 Output Clock Frequency (hpoutclk) Fhpout 177.5 MHz * Supply voltage and operating temperature are as per Recommended Operating Conditions tPWH hpclkout0/ clkout0 tPWL tOUT2OUTD hpclkout(n)/ clkout(n) Figure 29 - Output Timing Referenced To hpclkout0/clkout0 155 Microsemi Corporation Notes 10pF load ZL30165 Data Sheet Functional waveforms and timing characteristics for the LSB first mode are shown in Figure 30, and Figure 31 describe the MSB first mode. Table 8 shows the timing specifications. Specification Name Min. Max. Units 1 sck period tcyc 124 ns 2 sck pulse width low tclkl 62 ns 3 sck pulse width high tclkh 62 ns 4 si setup (write) from sck rising trxs 10 ns 5 si hold (write) from sck rising trxh 10 ns 6 so delay (read) from sck falling txd 7 cs_b setup from sck falling (LSB first) tcssi 20 ns 8 cs_b setup from sck rising (MSB first) tcssm 20 ns 9 cs_b hold from sck falling (MSB first) tcshm 10 ns 10 cs_b hold from sck rising (LSB first) tcshi 10 ns 11 cs_b to output high impedance tohz 25 ns 60 ns Table 8 - Serial Peripheral Interface Timing si tclkh trxh trxs sck tcssi tcshi tcyc tclkl cs_b txd so Figure 30 - Serial Peripheral Interface Timing - LSB First Mode 156 Microsemi Corporation tohz ZL30165 Data Sheet si tclkh trxh trxs sck tclkl tcyc tcssm txd tcshi cs_b tohz so Figure 31 - Serial Peripheral Interface Timing - MSB First Mode 157 Microsemi Corporation ZL30165 Data Sheet The timing specification for the I2C interface is shown in Figure 32 and Table 9. Specification Name Min. Typ. Max. 400 Units 1 SCL clock frequency fSCL 0 2 Hold time START condition tHD:STA 0.6 us 3 Low period SCL tLOW 1.3 us 4 Hi period SCL tHIGH 0.6 us 5 Setup time START condition tSU:STA 0.6 us 6 Data hold time tHD:DAT 0 7 Data setup time tSU:DAT 100 8 Rise time tr 9 Fall time tf 20 + 0.1Cb 10 Setup time STOP condition tSU:STO 0.6 us 11 Bus free time between STOP/START tBUF 1.3 us 12 Pulse width of spikes which must be suppressed by the input filter tSP 0 13 Max capacitance for each I/O pin 0.9 Note kHz us ns ns 250 Determined by choice of pull-up resistor ns 50 ns 10 pF Table 9 - I2C Serial Microport Timing SDA tSU:DAT tf tLOW tf tHD:STA tr tSP tBUF SCL tHD:STA S tHD:DAT tHIGH tSU:STA tSU:STO Sr Figure 32 - I2C Serial Microport Timing 158 Microsemi Corporation P S ZL30165 10.0 Performance Characterization 10.1 Output Clocks Jitter Generation Output Frequency 622.08 MHz Data Sheet Jitter Measurement Filter Max. Units 12 kHz - 20 MHz 0.67 psrms Notes 50 kHz - 80 MHz 0.63 psrms Table 10 - Jitter Generation Specifications - LVPECL Differential (HPDIFF) Outputs Jitter Measurement Filter Max. Units 25 MHz 12 kHz - 5 MHz 0.74 psrms 77.76 MHz 12 kHz - 20 MHz 0.97 psrms 125 MHz 12 kHz - 20 MHz 1.10 psrms Output Frequency Notes 156.25 MHz 12 kHz - 20 MHz 0.97 psrms Table 11 - Jitter Generation Specifications - LVCMOS Single-ended (HPOUT) Outputs 159 Microsemi Corporation ZL30165 10.2 Data Sheet DPLL Performance Characteristics Characteristics Min. Typ. +/-12 Max. Units Notes +/-2100 ppm user selectable For bandwidths of 5.2 Hz and above 1 Pull-in/Hold-in Range 2 Lock Time * 2 sec 3 Reference Switching MTIE 5 nsec 4 Entry into Holdover MTIE 5 nsec 5 Exit from Holdover MTIE 5 nsec 6 Holdover Accuracy - jitter free input 10 ppb 7 Holdover Accuracy - jittered input 50 ppb Table 12 - DPLL Characteristics * Lock time of 2 sec is achieved when pulling a 9.2 ppm reference for any selected bandwidth and when phase slope limit is larger than 7.5 usec. 11.0 Thermal Characteristics Parameter Symbol Test Condition Value Unit Junction to Ambient Thermal Resistance JA Still Air 1 m/s 2 m/s 21.3 19.0 17.8 oC/W Junction to Case Thermal Resistance JC 4.2 oC/W Junction to Board Thermal Resistance JB 10.1 oC/W Maximum Junction Temperature* Tjmax 125 oC Maximum Ambient Temperature TA 85 oC Table 13 - Thermal Care * Proper thermal management must be practiced to ensure that Tjmax is not exceeded. 160 Microsemi Corporation ZL30165 12.0 Mechanical Drawing 161 Microsemi Corporation Data Sheet ZL30165 13.0 Package Markings 13.1 144-pin BGA. Package Top Mark Format Data Sheet Figure 33 - Non-customized Device Top Mark Figure 34 - Custom Factory Programmed Device Top Mark Line Characters Description 1 ZL30165 Part Number 2 F Fab Code 2 R Product Revision Code 2 e1 Denotes Pb-Free Package 3 YY Last Two Digits of the Year of Encapsulation 3 WW Work Week of Assembly 3 A Assembly Location Code 3 ZZ Assembly Lot Sequence 4 CCID Custom Programming Identification Code 4 WP Work Week of Programming Table 14 - Package Marking Legend 162 Microsemi Corporation Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,400 employees globally. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: sales.support@microsemi.com (c) 2015 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. ZL30165