TL/F/9497
54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks
November 1994
54F/74F193 Up/Down Binary Counter
with Separate Up/Down Clocks
General Description
The ’F193 is an up/down modulo-16 binary counter. Sepa-
rate Count Up and Count Down Clocks are used, and in
either counting mode the circuits operate synchronously.
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs. Separate Terminal
Count Up and Terminal Count Down outputs are provided
that are used as the clocks for subsequent stages without
extra logic, thus simplifying multi-stage counter designs.
Individual preset inputs allow the circuit to be used as a
programmable counter. Both the Parallel Load (PL) and the
Master Reset (MR) inputs asynchronously override the
clocks.
Features
YGuaranteed 4000V minimum ESD protection
Commercial Military Package Package Description
Number
74F193PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F193DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F193SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
74F193SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F193FM (Note 2) W16A 16-Lead Cerpack
54F193LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffix eSCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix eDMQB, FMQB and LMQB.
Logic Symbols Connection Diagrams
TL/F/9497–1
IEEE/IEC
TL/F/9497–4
Pin Assignment
for DIP, SOIC and Flatpak
TL/F/9497–2
Pin Assignment
for LCC
TL/F/9497–3
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
CPUCount Up Clock Input (Active Rising Edge) 1.0/3.0 20 mA/b1.8 mA
CPDCount Down Clock Input (Active Rising Edge) 1.0/3.0 20 mA/b1.8 mA
MR Asynchronous Master Reset Input (Active HIGH) 1.0/1.0 20 mA/b0.6 mA
PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
P0–P3Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA
Q0–Q3Flip-Flop Outputs 50/33.3 b1 mA/20 mA
TCDTerminal Count Down (Borrow) Output (Active LOW) 50/33.3 b1 mA/20 mA
TCUTerminal Count Up (Carry) Output (Active LOW) 50/33.3 b1 mA/20 mA
Functional Description
The ’F193 is a 4-bit binary synchronous up/down (revers-
ible) counter. It contains four edge-triggered flip-flops, with
internal gating and steering logic to provide master reset,
individual preset, count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state. Synchronous switching,
as opposed to ripple counting, is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line, thereby causing all state
changes to be initiated simultaneously. A LOW-to-HIGH
transition on the Count Up input will advance the count by
one; a similar transition on the Count Down input will de-
crease the count by one. While counting with one clock in-
put, the other should be held HIGH, as indicated in the
Function Table.
The Terminal Count Up (TCU) and Terminal Count Down
(TCD) outputs are normally HIGH. When the circuit has
reached the maximum count state 15, the next HIGH-to-
LOW transition of the Count Up Clock will cause TCUto go
LOW. TCUwill stay LOW until CPUgoes HIGH again, thus
effectively repeating the Count Up Clock, but delayed by
two gate delays. Similarly, the TCDoutput will go LOW when
the circuit is in the zero state and the Count Down Clock
goes LOW. Since the TC outputs repeat the clock wave-
forms, they can be used as the clock input signals to the
next higher order circuit in a multistage counter.
TCUeQ0#Q1#Q2#Q3#CPU
TCDeQ0#Q1#Q2#Q3#CPD
The ’F193 has an asynchronous parallel load capability per-
mitting the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW, informa-
tion present on the Parallel Data input (P0–P3) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs. A HIGH signal on the
Master Reset input will disable the preset gates, override
both clock inputs, and latch each Q output in the LOW state.
If one of the clock inputs is LOW during and after a reset or
load operation, the next LOW-to-HIGH transition of that
clock will be interpreted as a legitimate signal and will be
counted.
Function Table
MR PL CPUCPDMode
H X X X Reset (Asyn.)
L L X X Preset (Asyn.)
L H H H No Change
LHLH Count Up
LH HLCount Down
HeHIGH Voltage Level
LeLOW Voltage Level
XeImmaterial
LeLOW-to-HIGH Clock Transition
State Diagram
TL/F/9497–5
2
Logic Diagram
TL/F/9497–6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature b65§Ctoa
150§C
Ambient Temperature under Bias b55§Ctoa
125§C
Junction Temperature under Bias b55§Ctoa
175§C
Plastic b55§Ctoa
150§C
VCC Pin Potential to
Ground Pin b0.5V to a7.0V
Input Voltage (Note 2) b0.5V to a7.0V
Input Current (Note 2) b30 mA to a5.0 mA
Voltage Applied to Output
in HIGH State (with VCC e0V)
Standard Output b0.5V to VCC
TRI-STATEÉOutput b0.5V to a5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
ESD Last Passing Voltage (Min) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military b55§Ctoa
125§C
Commercial 0§Ctoa
70§C
Supply Voltage
Military a4.5V to a5.5V
Commercial a4.5V to a5.5V
DC Electrical Characteristics
Symbol Parameter 54F/74F Units VCC Conditions
Min Typ Max
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage b1.2 V Min IIN eb
18 mA
VOH Output HIGH 54F 10% VCC 2.5 IOH eb
1mA
Voltage 74F 10% VCC 2.5 V Min IOH eb
1mA
74F 5% VCC 2.7 IOH eb
1mA
V
OL Output LOW 54F 10% VCC 0.5 V Min IOL e20 mA
Voltage 74F 10% VCC 0.5 IOL e20 mA
IIH Input HIGH 54F 20.0
mA Max VIN e2.7V
Current 74F 5.0
IBVI Input HIGH Current 54F 100
mA Max VIN e7.0V
Breakdown Test 74F 7.0
ICEX Output HIGH 54F 250
mA Max VOUT eVCC
Leakage Current 74F 50
VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA
Test All Other Pins Grounded
IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current b0.6 mA Max VIN e0.5V (MR, PL,P
n
)
b
1.8 VIN e0.5V (CPu,CP
D
)
I
OS Output Short-Circuit Current b60 b150 mA Max VOUT e0V
ICC Power Supply Current 38 55 mA Max
4
AC Electrical Characteristics
74F 54F 74F
TAea
25§CTA,V
CC eMil TA,V
CC eCom
Symbol Parameter VCC ea
5.0V CLe50 pF CLe50 pF Units
CLe50 pF
Min Typ Max Min Max Min Max
fmax Maximum Count Frequency 100 125 75 90 MHz
tPLH Propagation Delay 4.0 7.0 9.0 4.0 10.5 4.0 10.0
tPHL CPUor CPDto 3.5 6.0 8.0 3.5 9.5 3.5 9.0 ns
TCUor TCD
tPLH Propagation Delay 4.0 6.5 8.5 3.5 10.0 4.0 9.5 ns
tPHL CPUor CPDto Qn5.5 9.5 12.5 5.5 14.0 5.5 13.5
tPLH Propagation Delay 3.0 4.5 7.0 3.0 8.5 3.0 8.0 ns
tPHL Pnto Qn6.0 11.0 14.5 6.0 16.5 6.0 15.5
tPLH Propagation Delay 5.0 8.5 11.0 5.0 13.5 5.0 12.0 ns
tPHL PL to Qn5.5 10.0 13.0 5.5 15.0 5.5 14.0
tPHL Propagation Delay 5.5 11.0 14.5 5.0 16.0 5.5 15.5
MR to Qn
tPLH Propagation Delay 6.0 10.5 13.5 5.0 15.0 6.0 14.5 ns
MR to TCU
tPHL Propagation Delay 6.0 11.5 14.5 6.0 16.0 6.0 15.5
MR to TCD
tPLH Propagation Delay 7.0 12.0 15.5 7.0 18.5 7.0 16.5 ns
tPHL PL to TCUor TCD7.0 11.5 14.5 6.0 17.5 7.0 15.5
tPLH Propagation Delay 7.0 11.5 14.5 6.0 16.5 7.0 15.5 ns
tPHL Pnto TCUor TCD6.5 11.0 14.0 5.0 16.5 6.5 15.0
AC Operating Requirements
74F 54F 74F
Symbol Parameter TAea
25§CTA,V
CC eMil TA,V
CC eCom Units
VCC ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 4.5 6.0 5.0
ts(L) Pnto PL 4.5 6.0 5.0
th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0
ns
th(L) Pnto PL 2.0 2.0 2.0
tw(L) PL Pulse Width, LOW 6.0 7.5 6.0 ns
tw(L) CPUor CPD5.0 7.0 5.0 ns
Pulse Width, LOW
tw(L) CPUor CPD
Pulse Width, LOW 10.0 12.0 10.0 ns
(Change of Direction)
tw(H) MR Pulse Width, HIGH 6.0 6.0 6.0 ns
trec Recovery Time 6.0 8.0 6.0 ns
PL to CPUor CPD
trec Recovery Time 4.0 4.5 4.0 ns
MR to CPUor CPD
5
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 193 S C X
Temperature Range Family Special Variations
74FeCommercial QB eMilitary grade device with
54FeMilitary environmental and burn-in
processing
Device Type XeDevices shipped in 13×reel
Package Code Temperature Range
PePlastic DIP CeCommercial (0§Ctoa
70§C)
DeCeramic DIP MeMilitary (b55§Ctoa
125§C)
FeFlatpak
LeLeadless Chip Carrier (LCC)
SeSmall Outline SOIC JEDEC
SJ eSmall Outline SOIC EIAJ
6
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.150×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M16A
16-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M16D
8
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N16E
9
54F/74F193 Up/Down Binary Counter with Separate Up/Down Clocks
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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