MC74HC00ADR2G - ON Semiconductor

June, 2012 − Rev. 13

1Publication Order Number:

MC74HC00A/D

MC74HC00A

Quad 2-Input NAND Gate

High−Performance Silicon−Gate CMOS

The MC74HC00A is identical in pinout to the LS00. The device

inputs are compatible with Standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With the JEDEC Standard No. 7 A Requirements

•Chip Complexity: 32 FETs or 8 Equivalent Gates

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free and are RoHS Compliant

3Y1

1

A1

PIN 14 = VCC

PIN 7 = GND

LOGIC DIAGRAM

2

B1

6Y2

4

A2

5

B2

8Y3

9

A3

10

B3

11 Y4

12

A4

13

B4

Y = AB

Pinout: 14−Lead Packages (Top View)

1314 12 11 10 9 8

21 34567

VCC B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GND

L

H

L

H

L

H

FUNCTION TABLE

Inputs Output

AB

H

L

Y

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

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MARKING

DIAGRAMS

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

TSSOP−14

DT SUFFIX

CASE 948G

14

1

SOIC−14

D SUFFIX

CASE 751A

14

1

HC

00A

ALYWG

G

1

14

1

PDIP−14

N SUFFIX

CASE 646

MC74HC00AN

AWLYYWWG

1

14

(Note: Microdot may be in either location)

HC00AG

AWLYWW

1

14

MC74HC00A

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2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

750

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

ÎÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎÎÎ

260

ÎÎÎ

_C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎ

6.0

ÎÎÎ

V

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

0

ÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎ

+ 125

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

0

ÎÎ

1000

500

400

ÎÎÎ

ns

ORDERING INFORMATION

Device Package Shipping†

MC74HC00ANG PDIP−14

(Pb−Free) 25 Units / Rail

MC74HC00ADG SOIC−14

(Pb−Free) 55 Units / Rail

MC74HC00ADR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

MC74HC00ADTR2G TSSOP−14

(Pb−Free) 2500 / Tape & Reel

NLV74HC00ADG* SOIC−14

(Pb−Free)

55 Units / Rail

NLV74HC00ADR2G* SOIC−14

(Pb−Free)

2500 / Tape & Reel

NLV74HC00ADTR2G* TSSOP−14

(Pb−Free)

2500 / Tape & Reel

NLV74HC00ANG* PDIP−14

(Pb−Free)

25 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC00A

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3

DC CHARACTERISTICS (Voltages Referenced to GND)

VCC

V

Guaranteed Limit

Symbol Parameter Condition −55 to 25°C≤85°C≤125°C Unit

VIH Minimum High−Level Input

Voltage

Vout = 0.1V or VCC −0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

V

VIL Maximum Low−Level Input

Voltage

Vout = 0.1V or VCC − 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

V

VOH Minimum High−Level Output

Voltage

Vin = VIH or VIL

|Iout| ≤ 20mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin =VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low−Level Output

Voltage

Vin = VIH or VIL

|Iout| ≤ 20mA

2.0

4.5

6.0

0.1

V

Vin = VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage

Current

Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

ICC Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0mA

6.0 1.0 10 40 mA

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

VCC

V

Guaranteed Limit

Symbol Parameter −55 to 25°C≤85°C≤125°C Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A or B to Output Y

(Figures 1 and 2)

2.0

3.0

4.5

6.0

75

30

15

13

95

40

19

16

110

55

22

19

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

16

110

36

22

19

ns

Cin Maximum Input Capacitance 10 10 10 pF

CPD Power Dissipation Capacitance (Per Buffer)*

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

pF

22

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

MC74HC00A

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4

Figure 1. Switching Waveforms

GND

VCC

OUTPUT Y

INPUT

A OR B

CL*

*Includes all probe and jig capacitance

TEST

POINT

90%

50%

10%

tTLH

DEVICE

UNDER

TEST

OUTPUT

Figure 2. Test Circuit

Y

A

B

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

tTHL

90%

50%

10%

tPLH tPHL

tftr

MC74HC00A

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5

PACKAGE DIMENSIONS

PDIP−14

N SUFFIX

CASE 646−06

ISSUE P

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG D

K

C

SEATING

PLANE

N

−T−

14 PL

M

0.13 (0.005)

L

M

J0.290 0.310 7.37 7.87

MC74HC00A

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6

PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

H

14 8

71

M

0.25 B M

C

h

X 45

SEATING

PLANE

A1

A

M

_

S

A

M

0.25 B S

C

b

13X

B

A

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

__ __

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC00A

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7

PACKAGE DIMENSIONS

TSSOP−14

DT SUFFIX

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

K

K1

ÉÉÉ

DETAIL E

F

M

−W−

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

−V−

14X REFK

N

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC00A

http://onsemi.com

8

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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Phone: 81−3−5817−1050

MC74HC00A/D

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