HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Features * Ultra Low Power Dissipation * Normal Mode, 42 / 70 / 103 / 123 / 157 mW @ 20 / 40 / 65 / 80 / 105 MSPS * Low Power Mode, 31 / 49 / 71 / 85 / 107 mW @ 20 / 40 / 65 / 80 / 105 MSPS * Programmable Power Dissipation A / D Converters - SMT 0 * Coarse and fine gain control * Internal offset correction * 1.8 V supply voltage * 1.7 - 3.6 V CMOS logic on control interface pins * Serial LVDS 14, 16 and dual 8-bit output modes available * -10% to -40% ADC core current reduction in 4 steps * 7mm x 7mm 48 QFN Package * 75.4 dB SNR at 70 MHz FIN, Normal Mode Typical Applications * 72.6 dB SNR at 70 MHz FIN, Low Power Mode * 85 dB SFDR at 70 MHz FIN, Normal Mode * Diversity receivers * 83 dB SFDR at 70 MHz FIN, Low Power Mode * Software Defined Radio * 82 dB SFDR at 140 MHz FIN, Normal Mode * High End Ultrasound * 0.5 s start-up time from Sleep, 15 s from Power Down * Communication Testing * Non Destructive Testing * Internal ultra low jitter clock divider * Internal reference circuitry with no external components required Functional Diagram General Description HMCAD1060 is a versatile high performance low power 14-bit quad analog-to-digital converter (ADC) with optional power saving modes. The different Reduced Power Dissipation Modes can be selected during operation to trade off power dissipation and accuracy. Low switching times between the Modes enables the system to continuously keep power dissipation and performance at the optimum level. HMCAD1060 is based on a proprietary structure, and employs internal reference circuitry, a serial control interface and serial LVDS output data. Data and frame synchronization output clocks are supplied for data capture at the receiver. Figure 1. Functional Block Diagram In Dual 8-bit LVDS mode, each ADC is connected to two LVDS pairs, one for the 8 MSBs and one pair for the LSBs. Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. Register settings determine the exact function of this pin. HMCAD1060 is designed to easily interface with Field Programmable Gate Arrays (FPGAs). 0-1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Electrical Specifications AVDD= 1.8V, DVDD= 1.8V, OVDD= 1.8V, FS = 80 MSPS, 4 channel 14-bit Normal Mode, -1 dBFS 8 MHz input signal, 1x/0 dB digital gain (fine and coarse), unless otherwise noted Parameter Description Min Typ Max Unit 6 %FS DC Accuracy No missing codes Guaranteed Offset error after internal digital offset correction Gabs Gain error 1 LSB Grel Gain matching between channels. 3sigma value at worst case conditions 0.5 %FS DNL Differential non linearity 0.5 LSB INL Integral non linearity 1 LSB VCM,out Common mode voltage output VAVDD/2 Analog Input VCM,in Analog input common mode voltage FSR Differential input voltage range VCM -0.05 VCM +0.05 V Cin Differential input capacitance 6 pF BW Input Bandwidth 750 MHz Vpp 2 Clock Input FCLK Applied input clock frequency: FS*Clock Divide Factor 840 (105*8) 15 (15*1) MHz Power Supply VAVDD Analog Supply Voltage 1.7 1.8 2 V VDVDD Digital and output driver supply voltage 1.7 1.8 2 V VOVDD Digital CMOS Input Supply Voltage 1.7 1.8 3.6 V Operating free-air temperature -40 85 C Temperature TA For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 A / D Converters - SMT Offset 0-2 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Electrical Specifications - 20 MSPS AVDD= 1.8V, DVDD= 1.8V, OVDD= 1.8V, 20 MSPS clock, -1 dBFS 8 MHz input signal, 14-bit output, Input Signal common mode voltage=VAVDD/2, LVDS Mode 14-bit, unless otherwise noted Parameter Description Min Typ Max Unit Performance SNR SINAD A / D Converters - SMT 0 SFDR HD2 HD3 ENOB Xtlk Signal to Noise Ratio FIN = 8 MHz 75.5 dBFS FIN = 70 MHz 75.4 dBFS FIN = 140 MHz 74 dBFS Signal to Noise and Distortion Ratio FIN = 8 MHz 75 dBFS FIN = 70 MHz 74.5 dBFS FIN = 140 MHz 73 dBFS Spurious Free Dynamic Range FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc dBc Second order Harmonic Distortion FIN = 8 MHz 90 FIN = 70 MHz 90 dBc FIN = 140 MHz 85 dBc Third order Harmonic Distortion FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc bits Effective number of Bits FIN = 8 MHz 12.2 FIN = 70 MHz 12.1 bits FIN = 140 MHz 11.8 bits Crosstalk. Signal applied to 3 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1=8MHz, FIN0 =9.9MHz 95 dBc mA Power Supply IAVDD Analog Supply Current 48 IDVDD Digital and output driver Supply Current 45 mA PAVDD Analog Power 86 mW PDVDD Digital Power 80 mW PTOT Total Power Dissipation 167 mW PPD Power Down Mode dissipation 10 W PSLP Deep sleep Mode power dissipation 29 mW PSLPCH2 Total Power dissipation with all channels in sleep channel mode (Light sleep) 47 mW PSLPCH1 Power dissipation savings per channel off 29 mW Clock Inputs 0-3 FSmax Max. Conversion Rate FSmin Min. Conversion Rate 20 MSPS 15 MSPS For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Electrical Specifications - 40 MSPS AVDD= 1.8V, DVDD= 1.8V, OVDD= 1.8V, 40 MSPS clock, -1 dBFS 8 MHz input signal, 14-bit output, Input Signal common mode voltage=VAVDD/2, LVDS Mode 14-bit, unless otherwise noted Parameter Description Min Typ Max Unit Performance SINAD SFDR HD2 HD3 ENOB Xtlk Signal to Noise Ratio FIN = 8 MHz 75.5 FIN = 70 MHz 75.4 dBFS dBFS FIN = 140 MHz 74 dBFS Signal to Noise and Distortion Ratio FIN = 8 MHz 75 dBFS FIN = 70 MHz 74.5 dBFS FIN = 140 MHz 73 dBFS Spurious Free Dynamic Range FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc dBc Second order Harmonic Distortion FIN = 8 MHz 90 FIN = 70 MHz 90 dBc FIN = 140 MHz 85 dBc Third order Harmonic Distortion FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc bits Effective number of Bits FIN = 8 MHz 12.2 FIN = 70 MHz 12.1 bits FIN = 140 MHz 11.8 bits Crosstalk. Signal applied to 3 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1=8MHz, FIN0 =9.9MHz 95 dBc mA Power Supply IAVDD Analog Supply Current 91 IDVDD Digital and output driver Supply Current 63 mA PAVDD Analog Power 165 mW PDVDD Digital Power 113 mW PTOT Total Power Dissipation 278 mW PPD Power Down Mode dissipation 10 W PSLP Deep sleep Mode power dissipation 37 mW PSLPCH2 Total Power dissipation with all channels in sleep channel mode (Light sleep) 73 mW PSLPCH1 Power dissipation savings per channel off 50 mW 0 A / D Converters - SMT SNR Clock Inputs FSmax Max. Conversion Rate FSmin Min. Conversion Rate 40 MSPS 15 MSPS For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0-4 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Electrical Specifications - 65 MSPS AVDD= 1.8V, DVDD= 1.8V, OVDD= 1.8V, 65 MSPS clock, -1 dBFS 8 MHz input signal, 14-bit output, Input Signal common mode voltage=VAVDD/2, LVDS Mode 14-bit, unless otherwise noted Parameter Description Min Typ Max Unit Performance SNR SINAD A / D Converters - SMT 0 SFDR HD2 HD3 ENOB Xtlk Signal to Noise Ratio FIN = 8 MHz 75.5 FIN = 70 MHz 75.4 dBFS dBFS FIN = 140 MHz 74 dBFS dBFS Signal to Noise and Distortion Ratio FIN = 8 MHz 75 FIN = 70 MHz 74.5 dBFS FIN = 140 MHz 73 dBFS Spurious Free Dynamic Range FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc Second order Harmonic Distortion FIN = 8 MHz 90 dBc FIN = 70 MHz 90 dBc FIN = 140 MHz 85 dBc Third order Harmonic Distortion FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc Effective number of Bits FIN = 8 MHz 12.2 bits FIN = 70 MHz 12.1 bits FIN = 140 MHz 11.8 bits Crosstalk. Signal applied to 3 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1=8MHz, FIN0 =9.9MHz 95 dBc mA Power Supply IAVDD Analog Supply Current 144 IDVDD Digital and output driver Supply Current 85 mA PAVDD Analog Power 259 mW PDVDD Digital Power 152 mW PTOT Total Power Dissipation 411 mW PPD Power Down Mode dissipation 10 W PSLP Deep sleep Mode power dissipation 46 mW PSLPCH2 Total Power dissipation with all channels in sleep channel mode (Light sleep) 105 mW PSLPCH1 Power dissipation savings per channel off 76 mW Clock Inputs 0-5 FSmax Max. Conversion Rate FSmin Min. Conversion Rate 65 MSPS 15 MSPS For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Electrical Specifications - 80 MSPS AVDD= 1.8V, DVDD= 1.8V, OVDD= 1.8V, 80 MSPS clock, -1 dBFS 8 MHz input signal, 14-bit output, Input Signal common mode voltage=VAVDD/2, LVDS Mode dual 8-bit, unless otherwise noted Parameter Description Min Typ Max Unit Performance SINAD SFDR HD2 HD3 ENOB Xtlk Signal to Noise Ratio FIN = 8 MHz 75.5 FIN = 70 MHz 75.4 dBFS dBFS FIN = 140 MHz 74 dBFS dBFS Signal to Noise and Distortion Ratio FIN = 8 MHz 75 FIN = 70 MHz 74.5 dBFS FIN = 140 MHz 73 dBFS Spurious Free Dynamic Range FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc Second order Harmonic Distortion FIN = 8 MHz 90 dBc FIN = 70 MHz 90 dBc FIN = 140 MHz 85 dBc Third order Harmonic Distortion FIN = 8 MHz 89 dBc FIN = 70 MHz 85 dBc FIN = 140 MHz 82 dBc Effective number of Bits FIN = 8 MHz 12.2 bits FIN = 70 MHz 12.1 bits FIN = 140 MHz 11.8 bits Crosstalk. Signal applied to 3 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1=8MHz, FIN0 =9.9MHz 95 dBc mA Power Supply IAVDD Analog Supply Current 175 IDVDD Digital and output driver Supply Current 99 mA PAVDD Analog Power 314 mW PDVDD Digital Power 179 mW PTOT Total Power Dissipation 493 mW PPD Power Down Mode dissipation 10 W PSLP Deep sleep Mode power dissipation 52 mW PSLPCH2 Total Power dissipation with all channels in sleep channel mode (Light sleep) 105 mW PSLPCH1 Power dissipation savings per channel off 97 mW 0 A / D Converters - SMT SNR Clock Inputs FSmax Max. Conversion Rate FSmin Min. Conversion Rate 80 MSPS 15 MSPS For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0-6 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Electrical Specifications - 105 MSPS AVDD= 1.8V, DVDD= 1.8V, OVDD= 1.8V, 105 MSPS clock, -1 dBFS 8 MHz input signal, 14-bit output, Input Signal common mode voltage=VAVDD/2, LVDS Mode dual 8-bit, unless otherwise noted Parameter Description Min Typ Max Unit Performance SNR SINAD A / D Converters - SMT 0 SFDR HD2 HD3 ENOB Xtlk Signal to Noise Ratio FIN = 8 MHz 75 dBFS FIN = 70 MHz 74.3 dBFS FIN = 140 MHz 71.5 dBFS Signal to Noise and Distortion Ratio FIN = 8 MHz 73 dBFS FIN = 70 MHz 72.5 dBFS FIN = 140 MHz 71 dBFS Spurious Free Dynamic Range FIN = 8 MHz 83 dBc FIN = 70 MHz 80 dBc FIN = 140 MHz 78 dBc dBc Second order Harmonic Distortion FIN = 8 MHz 85 FIN = 70 MHz 85 dBc FIN = 140 MHz 85 dBc Third order Harmonic Distortion FIN = 8 MHz 83 dBc FIN = 70 MHz 80 dBc FIN = 140 MHz 78 dBc bits Effective number of Bits FIN = 8 MHz 11.8 FIN = 70 MHz 11.8 bits FIN = 140 MHz 11.5 bits Crosstalk. Signal applied to 3 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1=8MHz, FIN0 =9.9MHz 95 dBc mA Power Supply IAVDD Analog Supply Current 225 IDVDD Digital and output driver Supply Current 123 mA PAVDD Analog Power 405 mW PDVDD Digital Power 221 mW PTOT Total Power Dissipation 626 mW PPD Power Down Mode dissipation 10 W PSLP Deep sleep Mode power dissipation 61 mW PSLPCH2 Total Power dissipation with all channels in sleep channel mode (Light sleep) 130 mW PSLPCH1 Power dissipation savings per channel off 120 mW Clock Inputs 0-7 FSmax Max. Conversion Rate FSmin Min. Conversion Rate 105 MSPS 15 MSPS For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Digital and Switching Specifications AVDD= 1.8V, DVDD= 1.8V, OVDD= 1.8V, unless otherwise noted Parameter Description Min Duty Cycle 30 Typ Max Unit 70 % high Clock Inputs DC Sine, CMOS, LVDS, LVPECL VCK,diff Differential input voltage swing +/-200 VCK,sine Differential input voltage swing, sine wave clock input +/-800 VCK,CMOS Voltage input range CMOS (CLKN connected to ground) VCM,CK Input common mode voltage. Keep voltages within ground and voltage of OVDD CCK Differential Input capacitance mVpp mVpp VOVDD VOVDD -0.3 0.3 3 V pF Logic Inputs (CMOS) VHI High Level Input Voltage. VOVDD 3.0V 2 VHI High Level Input Voltage. VOVDD = 1.7V - 3.0V 0.8*VOVDD V VLI Low Level Input Voltage. VOVDD 3.0V 0 0.8 VLI Low Level Input Voltage. VOVDD = 1.7V - 3.0V 0 0.2*VOVDD V IHI High Level Input leakage Current +/-10 A ILI Low Level Input leakage Current +/-10 A CI Input Capacitance V 3 V pF Data Outputs (LVDS) Compliance LVDS VOUT Differential output voltage 350 mV VCM Output common mode voltage 1.2 V Output coding Default/optional Offset Binary/ 2's complement Timing Characteristics Aperture delay Aperture jitter TSU Start up time from Power Down Mode and Deep Sleep Mode to Active Mode. References have reached 99% of final value. See section "Clock Frequency" 0.8 ns 80 fsrms 260 992 clock cycles Start up time from Power Down Mode and Deep Sleep Mode to Active Mode in s. 15 TSLPCH Start up time from Sleep Channel Mode to Active Mode 0.5 s TOVR Out of range recovery time 1 clock cycles TLAT Pipeline delay 15 clock cycles ps s 0 A / D Converters - SMT Compliance LVDS Output Timing Characteristics tdata LCLK to data delay time (excluding programmable phase shift) 250 TPROP Clock propagation delay. 7 * TLVDS + 3 LVDS bit-clock duty-cycle 45 Frame clock cycle-to-cycle jitter ns 55 % LCLK cycle 2.5 % LCLK cycle TEDGE Data rise and fall time 20% to 80% 0.4 ns TCLKEDGE Clock rise and fall time 20% to 80% 0.4 ns For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0-8 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Absolute Maximum Ratings Table 2. Maximum Temperature Ratings Applying voltages to the pins beyond those specified in Table 1 could cause permanent damage to the circuit. Operating Temperature -40 to +85 C Storage Temperature -60 to +150 C Soldering Profile Qualification J-STD-020 Table 1. Maximum Voltage Ratings Pin A / D Converters - SMT 0 Reference Pin Rating -0.3V to +2.3V AVDD AVSS DVDD DVSS -0.3V to +2.3V OVDD AVSS -0.3V to +3.9V -0.3V to +0.3V AVSS / DVSS DVSS / AVSS Analog inputs and outputs AVSS -0.3V to +2.3V CLKx AVSS -0.3V to +3.9V LVDS outputs DVSS -0.3V to +2.3V Digital inputs DVSS -0.3V to +3.9V ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS This device can be damaged by ESD. Even though this product is protected with state-of-the-art ESD protection circuitry, damage may occur if the device is not handled with appropriate precautions. ESD damage may range from device failure to performance degradation. Analog circuitry may be more susceptible to damage as very small parametric changes can result in specification incompliance. Pin Configuration and Description Figure 2. Package diagram 0-9 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Table 3. Pin Descriptions Description Pin Number AVDD Analog power supply, 1.8V 1, 36 # of Pins 2 CSN Chip select enable. Active low 2 1 SDATA Serial data input 3 1 SCLK Serial clock input 4 1 RESETN Reset SPI interface. Active low 5 1 PD Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the SPI power down feature 6 1 DVDD Digital and I/O power supply, 1.8V 7, 30 2 DVSS Digital ground 8, 29 2 DP1A LVDS channel 1A, positive output 9 1 DN1A LVDS channel 1A, negative output 10 1 DP1B LVDS channel 1B, positive output 11 1 DN1B LVDS channel 1B, negative output 12 1 DP2A LVDS channel 2A, positive output 13 1 DN2A LVDS channel 2A, negative output 14 1 DP2B LVDS channel 2B, positive output 15 1 DN2B LVDS channel 2B, negative output 16 1 LCKP LVDS bit clock, positive output 17 1 LCKN LVDS bit clock, negative output 18 1 FCLKP LVDS frame clock (1X), positive output 19 1 FCLKN LVDS frame clock (1X), negative output 20 1 DP3A LVDS channel 3A, positive output 21 1 DN3A LVDS channel 3A, negative output 22 1 1 DP3B LVDS channel 3B, positive output 23 DN3B LVDS channel 3B, negative output 24 1 DP4A LVDS channel 4A, positive output 25 1 DN4A LVDS channel 4A, negative output 26 1 DP4B LVDS channel 4B, positive output 27 1 DN4B LVDS channel 4B, negative output 28 1 AVSS2 Analog ground domain 2 31 1 AVDD2 Analog power supply domain 2, 1.8V 32 1 OVDD Digital CMOS Inputs supply voltage 33 1 CLKN Negative differential input clock. 34 1 CLKP Positive differential input clock 35 1 IN4 Negative differential input signal, channel 4 37 1 1 IP4 Positive differential input signal, channel 4 38 AVSS Analog ground 39, 42, 45 3 IN3 Negative differential input signal, channel 3 40 1 IP3 Positive differential input signal, channel 3 41 1 IN2 Negative differential input signal, channel 2 43 1 IP2 Positive differential input signal, channel 2 44 1 IN1 Negative differential input signal, channel 1 46 1 IP1 Positive differential input signal, channel 1 47 1 VCM Common mode output pin, 0.5*AVDD 48 1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 A / D Converters - SMT Pin Name 0 - 10 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Start up Initialization As part of the HMCAD1060 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. Make sure that the supply voltages are properly settled before the start up initialization is being performed. Reset can be done in one of two ways: 1. By applying a low-going pulse (minimum 20 ns) on the RESETN pin (asynchronous). 2. By using the serial interface to set the `rst' bit high. Internal registers are reset to default values when this bit is set. The `rst' bit is self-reset to zero. When using this method, do not apply any low-going pulse on the RESETN pin. Power down cycling can be done in one of two ways: 1. By applying a high-going pulse (minimum 20 ns) on the PD pin (asynchronous). A / D Converters - SMT 0 2. By cycling the `pd' bit in register 0Fhex to high (reg value `0200'hex) and then low (reg value `0000'hex). Serial Interface The HMCAD1060 configuration registers can be accessed through a serial interface formed by the pins SDATA (serial interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs when CSN is set low: * Serial data are shifted into the chip * At every rising edge of SCLK, the value present at SDATA is latched * SDATA is loaded into the register every 24th rising edge of SCLK Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is divided into two parts: * The first eight bits form the register address * The remaining 16 bits form the register data Acceptable SCLK frequencies are from 20 MHz down to a few hertz. Duty-cycle does not have to be tightly controlled. Timing Diagram Figure 3 shows the timing of the serial port interface. Table 4 explains the timing variables used in figure 3. Figure 3. Serial Port Interface timing Table 4. Serial Port Interface Timing Definitions 0 - 11 Parameter Description Minimum Value Unit tcs Setup time between CSN and SCLK 8 ns tch Hold time between CSN and SCLK 8 ns thi SCLK high time 20 ns tlo SCLK low time 20 ns tck SCLK period 50 ns ts Data setup time 5 ns th Data hold time 5 ns For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Timing Diagrams Figure 4. LVDS timing 14-bit output Figure 5. LVDS timing 16-bit output For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com A / D Converters - SMT 0 0 - 12 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter A / D Converters - SMT 0 0 - 13 Figure 6. LVDS timing dual 8-bit output Figure 7. LVDS data timing Register Map Summary Table 5. Register Map Name Description Default rst * Self-clearing software reset. Inactive sleep_ch <4:1> Channel-specific sleep mode. Inactive sleep Go to sleep-mode. Inactive pd Go to power-down. Inactive pd_pin_cfg <1:0> Configures the PD pin function. PD pin configured for power-down mode low_power_ en Enable low power mode Inactive low_power_ cfg Configure low power mode behavior Low power mode configured as sleep D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X Hex Address 0x00 X X X X X 0x0F X X For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Table 5. Register Map D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address Name Description Default ilvds_lclk <2:0> LVDS current drive programmability for LCLKP and LCLKN pins. 3.5 mA drive ilvds_frame <2:0> LVDS current drive programmability for FCLKP and FCLKN pins. 3.5 mA drive ilvds_dat <2:0> LVDS current drive programmability for output data pins. 3.5 mA drive en_lvds_ term Enables internal termination for LVDS buffers. Termination disabled X term_lclk <2:0> Programmable termination for LCLKN and LCLKP buffers. Termination disabled 1 term_frame <2:0> Programmable termination for FCLKN and FCLKP buffers. Termination disabled 1 term_dat <2:0> Programmable termination for output data buffers. Termination disabled 1 invert_ch <4:1> Channel specific swapping of the analog input signal. IPx is positive input en_ramp Enables a repeating full-scale ramp pattern on the outputs. Inactive X 0 0 dual_ custom_pat Enable the mode wherein the output toggles between two defined codes. Inactive 0 X 0 single_ custom_pat Enables the mode wherein the output is a constant specified code. Inactive 0 0 X bits_ custom1 <15:0> Bits for the single custom pattern and for the first code of the dual custom pattern. <0> is the LSB. 0x0000 X X X X X X X X X X X X X X X X bits_ custom2 <15:0> Bits for the second code of the dual custom pattern. 0x0000 X X X X X X X X X X X X X X X X cgain_ch1 <3:0> Programmable coarse gain for channel 1 0dB gain X X X X cgain_ch2 <3:0> Programmable coarse gain for channel 2 0dB gain cgain_ch3 <3:0> Programmable coarse gain for channel 3 0dB gain cgain_ch4 <3:0> Programmable coarse gain for channel 4 0dB gain jitter_ctrl <7:0> Clock jitter adjustment. 130 fsrms clk_divide <1:0> * Define clock divider factor: 1, 2, 4 or 8 Divide by 1 coarse_ gain_cfg Configures the coarse gain setting dB-gain enabled fine_gain_ en Enable use of fine gain. Disabled fgain_ch1 <6:0> Programmable fine gain for ch 1 1x / 0dB gain X X X X X X X 0x34 fgain_ch2 <6:0> Programmable fine gain for ch 2 1x / 0dB gain X X X X X X X 0x35 fgain_ch3 <6:0> Programmable fine gain for ch 3 1x / 0dB gain X X X X X X X 0x36 fgain_ch4 <6:0> Programmable fine gain for ch 4. 1x / 0dB gain X X X X X X X 0x37 phase_ddr <1:0> Controls the phase of the LCLK output relative to data. 90 degrees X X pat_deskew Enable deskew pattern mode. Inactive 0 X pat_sync Enable sync pattern mode. Inactive X 0 btc_mode Binary two's complement format for ADC output data. Straight offset binary msb_first Serialized ADC output data comes out with MSB first. LSB first X X X X X X X 0x11 X X X X X 0x12 X X X X X X X X X X X X 0x24 0x25 0x26 0x27 X 0x2A X X X X X X X X X X X X X X X X X X 0x30 0 0 0 0 0x31 X 0x33 X 0 A / D Converters - SMT X 0x42 0x45 X 0x46 X For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 14 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Table 5. Register Map A / D Converters - SMT 0 Name Description Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 adc_curr <2:0> ADC current scaling. Nominal ext_vcm_ bc <1:0> VCM buffer driving strength control. Nominal lvds_pd_ mode Controls LVDS power down mode High z-mode lvds_ output_ mode <2:0> * Sets the number of LVDS output bits. 14 bit low_clk_ freq * Low clock frequency used. Inactive lvds_ advance Advance LVDS data bits and frame clock by one clock cycle Inactive 0 X lvds_delay Delay LVDS data bits and frame clock by one clock cycle Inactive X 0 fs_cntrl <5:0> Fine adjust ADC full scale range 0% change X X startup_ctrl <2:0> * Controls start-up time. `000' X X Hex Address X 0x50 X X X X X 0x52 X X 0x53 X X X X 0x55 X X X 0x56 D0 Hex Address X 0x00 Undefined register addresses must not be written to; incorrect behavior may be the result. Unused register bits (blank table cells) must be set to `0' when programming the registers. All registers can be written to while the chip is in power down mode. * These registers requires a power down cycle when written to (See Start up Initialization). Register Description Software Reset Name Description Default rst Self-clearing software reset. Inactive D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Setting the rst register bit to `1', restores the default value of all the internal registers including the rst register bit itself. Full-Scale Control Name Description Default fs_cntrl <5:0> Fine adjust ADC full scale range 0% change D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address X X X X X X 0x55 The full-scale voltage range of HMCAD1060 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl register. Changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. This leads to a maximum range of 10% adjustment. Table 6 shows how the register settings correspond to the full-scale range. Note that the values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be monotonous. The full-scale control and the programmable gain features differ in two major ways: 1.The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2.The programmable gain feature has much coarser gain steps and larger range than the full-scale control. 0 - 15 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Table 6. Register Values with Corresponding Change in Full-Scale Range Full-Scale Range Adjustment 111111 9.70% 111110 9.40% 100001 0.30% 100000 0% 11111 -0.3% 1 -9.7% 0 -10% Current Control Name Description Default adc_curr <2:0> ADC current scaling. Nominal ext_vcm_bc <1:0> VCM buffer driving strength control. Nominal D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X Hex Address 0x50 X X There are two registers that impact performance and power dissipation. The adc_curr register scales the current consumption in the ADC core. The performance is guaranteed at the nominal setting. Lower power consumption can be achieved by reducing the adc_curr value, see table 7. The impact on performance is low for settings down to minimum, but will depend on the ADC sampling rate. Table 7. ADC Current Control Settings adc_curr <2:0> ADC Core Current 100 -40% (lower performance) 101 -30% 110 -20% 111 -10% 000 (default) Nominal 1 Do not use 10 Do not use 11 Do not use 0 A / D Converters - SMT fs_cntrl <5:0> The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is not in use, the buffer can be switched off. If current is drawn from the VCM pin, the driving strength can be increased to keep the voltage on this pin at the correct level. Table 8. External Common Mode Voltage Buffer Driving Strength ext_vcm_bc <1:0> VCM buffer driving strength (A) Max current sinked/sourced from VCM pin with < 20 mV voltage change. 0 Off (VCM floating) 01 (default) +/- 20 10 +/- 400 11 +/- 800 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 16 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Start-up and Clock Jitter Control Name Description Default startup_ctrl <2:0> Controls start-up time. `000' jitter_ctrl <7:0> Clock jitter adjustment. 130 fsrms clk_divide <1:0> A / D Converters - SMT 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 X Define clock divider factor: 1, 2, 4 or 8 Divide by 1 X X D6 X D5 X D4 X D2 D1 D0 Hex Address X X X 0x56 X X X X 0x30 0 0 0 0 0x31 D3 To optimize start up time, a register is provided where the start-up time in clock cycles can be set. Some internal circuitry have start up times that are clock frequency independent. Default counter values are set to accommodate these start up times at the maximum clock frequency. This will lead to increased start up times at low clock frequency. Setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual start up time, such that the start up time will be reduced. The start up times from power down and sleep modes are changed by this register setting. Table 9. Start-up Time Control Settings startup_ctrl <2:0> Clock Frequency Range (MSPS) Start-up Delay (Clock Cycles) Start-up Delay (s) 100 80 - 125 1536 12.3 - 19.2 0 50 - 80 992 12.4 - 19.8 1 32,5 - 50 640 12.8 - 19.7 10 20 - 32,5 420 12.9 - 21 11 15 - 20 260 13 - 17.3 other Do not use - - jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. If all bits in the register is set low, the clock signal is stopped. The clock jitter depends on the number of bits set to `1' in the jitter_ctrl<7:0> register. Which bits are set high does not affect the result. Table 10. Clock Jitter Performance Number of Bits to `1' in Jitter_ctrl <7:0> Clock Jitter Performance (fsrms) Module Current Consumption (mA) 1 130 1 2 100 2 3 92 3 4 85 4 5 82 5 6 80 6 7 77 7 8 75 8 0 Clock Stopped clk_divide<1:0> allows the user to apply an input clock frequency higher than the sampling rate. The clock divider will divide the input clock frequency by a factor of 1, 2, 4, or 8, defined by the clk_divide<1:0> register. 0 - 17 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Table 11. Clock Divider Factor clk_divide <1:0> Clock Divider Factor Sampling Rate (FS) 00 (default) 1 Input clock frequency / 1 1 2 Input clock frequency / 2 10 4 Input clock frequency / 4 11 8 Input clock frequency / 8 LVDS Output Configuration and Control Description Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 lvds_output_ mode <2:0> Sets the number of LVDS output bits. 14 bit low_clk_freq Low clock frequency used. Inactive lvds_advance Advance LVDS data bits and frame clock by one clock cycle Inactive 0 X lvds_delay Delay LVDS data bits and frame clock by one clock cycle Inactive X 0 phase_ddr <1:0> Controls the phase of the LCLK output relative to data. 90 degrees btc_mode Binary two's complement format for ADC output data. Straight offset binary msb_first Serialized ADC output data comes out with MSB first. LSB first D3 D2 D1 D0 X X Hex Address X X 0x53 X X 0x42 X 0x46 X The HMCAD1060 serial LVDS output has three different modes selected by the register lvds_output_mode as defined in table 12. Power down mode, as described in section `Startup Initialization', must be activated after or during a change in the number of output bits to ensure correct behavior. Table 12. Number of Bits in LVDS Output lvds_output_mode <2:0> Number of Bits 10 14 bit 11 16 bit 100 Dual 8 bit Other Do not use If the 16-bit output mode is used the output data will be a 14-bit left justified word filled up with `0' on the LSB side. If the dual 8-bit output mode is used the 8 most significant bit of the 14 bit data word will be available on the LVDS `A' output and the remaining 6 bit will be left justified and filled up with `0' on the LVDS `B' output. The connection between the ADC channels and the LVDS outputs for the different LVDS modes is given by table 13. 0 A / D Converters - SMT Name Table 13. Connection Between ADC Channels and LVDS Outputs LVDS Set-Up LVDS Outputs Used Channel 1 - 14, 16-bit output D1A (D1B will be in power down - high Z) Channel 1 - Dual 8-bit output D1A, D1B Channel 2 - 14, 16-bit output D2A (D2B will be in power down - high Z) Channel 2 - Dual 8-bit output D2A, D2B Channel 3 - 14, 16-bit output D3A (D3B will be in power down - high Z) Channel 3 - Dual 8-bit output D3A, D3B Channel 4 - 14, 16-bit output D4A (D4B will be in power down - high Z) Channel 4 - Dual 8-bit output D4A, D4B For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 18 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Maximum data output bit-rate for the HMCAD1060 is 1 Gb/s. The maximum sampling rate for the different configurations is given by table 14. The sampling rate is set by the frequency of the input clock (FS). The frame-rate, i.e. the frequency of the FCLK signal on the LVDS outputs, equals FS for all LVDS output modes. Table 14. Maximum Input Clock Speed vs. Number of Output Bits for Different HMCAD1060 Configurations Number of Bits A / D Converters - SMT 0 Sampling Rate (MSPS) 14 70 16 62.5 Dual 8 1251 If the HMCAD1060 device is using a low frequency input clock, FS < 30 MHz, the register bit low_clk_freq has to be set to `1'. To ease timing in the receiver when using multiple HMCAD1060, the device has the option to adjust the timing of the output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS clock cycle forward or backward, by using lvds_delay and lvds_advance, respectively. See figure 8 for details. Note that LCLK is not affected by lvds_delay or lvds_advance settings. Figure 8. LVDS output timing adjustment The LVDS output interface of HMCAD1060 is a DDR interface. The default setting is with the LCLK rising and falling edge transitions in the middle of alternate data windows. The phase for LCLK can be programmed relative to the output frame clock and data bits using phase_ddr<1:0>. The LCLK phase modes are shown in figure 9. The default timing is identical to setting phase_ddr<1:0>='10'. 0 - 19 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Figure 9. Phase programmability modes for LCLK The default data output format is offset binary. Two's complement mode can be selected by setting the btc_mode bit to `1' which inverts the MSB. The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Programming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP rising edge. LVDS Drive Strength Programmability Name Description Default ilvds_lclk <2:0> LVDS current drive programmability for LCLKP and LCLKN pins. 3.5 mA drive ilvds_frame <2:0> LVDS current drive programmability for FCLKP and FCLKN pins. 3.5 mA drive ilvds_dat <2:0> LVDS current drive programmability for output data pins. 3.5 mA drive D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X Hex Address X 0x11 X The current delivered by the LVDS output drivers can be configured as shown in table 15. The default current is 3.5mA, which is what the LVDS standard specifies. Setting the ilvds_lclk<2:0> register controls the current drive strength of the LVDS clock output on the LCLKP and LCLKN pins. A / D Converters - SMT 0 Setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the FCLKP and FCLKN pins. Setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1]N pins. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 20 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Table 15. LVDS Output Drive Strength for LCLK, FCLK & Data A / D Converters - SMT 0 0 - 21 ilvds_* <2:0> LVDS Drive Strength 0 3.5 mA (default) 1 2.5 mA 10 1.5 mA 11 0.5 mA 100 7.5 mA 101 6.5 mA 110 5.5 mA 111 4.5 mA LVDS Internal Termination Programmability Name Description Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 en_lvds_ term Enables internal termination for LVDS buffers. Termination disabled X term_lclk <2:0> Programmable termination for LCLKN and LCLKP buffers. Termination disabled 1 term_frame <2:0> Programmable termination for FCLKN and FCLKP buffers. Termination disabled 1 term_dat <2:0> Programmable termination for output data buffers. Termination disabled 1 X X Hex Address X 0x12 X X X X X X The off-chip load on the LVDS buffers may represent a characteristic impedance that is not perfectly matched with the PCB traces. This may result in reflections back to the LVDS outputs and loss of signal integrity. This effect can be mitigated by enabling an internal termination between the positive and negative outputs of each LVDS buffer. Internal termination mode can be selected by setting the en_lvds_term bit to `1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table 16 shows how the internal termination of the LVDS buffers are programmed. The values are typical values and can vary by up to 20% from device to device and across temperature. Table 16. LVDS Output Internal Termination for LCLK, FCLK & Data term_* <2:0> LVDS Internal Termination 0 Termination disabled 1 260 10 150 11 94 100 125 101 80 110 66 111 55 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Power Mode Control Description Default sleep_ch <4:1> Channel-specific sleep mode. Inactive sleep Go to sleep-mode. Inactive pd Go to power-down. Inactive pd_pin_cfg Configures the PD pin function. <1:0> D15 D14 D13 D12 D11 D10 D9 Enable low power mode Inactive low_power_ cfg Configure low power mode behavior Low power mode configured as sleep lvds_pd_ mode Controls LVDS power down mode High z-mode D7 D6 D5 D4 D3 X D2 D1 D0 X X Hex Address X X X PD pin configured for power-down mode low_power_ en D8 X 0x0F X X X X 0x52 The HMCAD1060 device has several modes for power management, from sleep modes with short start up time to full power down with extremely low power dissipation. There are two sleep modes, both with the LVDS clocks (FCLK, LCLK) running, such that the synchronization with the receiver is maintained. The first is a light sleep mode (sleep_ch) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down. Setting sleep_ch<n> = `1' sets channel <n> in sleep mode. This is a light sleep mode with short start up time. Setting sleep = `1', puts all channels to sleep, but keeps FCLK and LCLK running to maintain LVDS synchronization. The start up time is the same as for complete power down. Power consumption is significantly lower than for setting all channels to sleep by using the sleep_ch register. Setting pd = `1' completely powers down the chip, including the band-gap reference circuit. Start-up time from this mode is significantly longer than from the sleep_ch mode. The synchronization with the LVDS receiver is lost since LCLK and FCLK outputs are put in high-Z mode. Setting pdn_pin_cfg<1:0> = `x1' configures the circuit to enter sleep channel mode (all channels off) when the PD pin is set high. This is equal to setting all channels to sleep by using sleep*_ch. The channels can not be powered down separately using the PD pin. Setting pdn_pin_cfg<1:0> = `10' configures the circuit to enter (deep) sleep mode when the PD pin is set high (equal to setting sleep='1'). When pdn_pin_cfg <1:0>= `00', which is the default, the circuit enters the power down mode when the PD pin is set high. The lvds_pd_mode register configures whether the LVDS data output drivers are powered down or kept alive in sleep and sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and sleep channel modes. If lvds_pd_mode is set low (default), the LVDS output is put in high Z mode, and the driver is completely powered down. If lvds_pd_mode is set high, the LVDS output is set to constant 0, and the driver is still on during sleep and sleep channel modes. 0 A / D Converters - SMT Name Setting the low_power_en register bit to `1' will set all channels to an low power mode with reduced performance and reduced power consumption. In this low power mode the power consumption and the start-up time back to normal mode is configured by register bit low_power_cfg. If low_power_cfg is set to `0' the start-up time back to normal mode will be the same as from sleep mode. And if low_power_cfg is set to `1' the start-up time will be as from power down. The current consumption reduction is highest with low_power_cfg set to `1' . For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 22 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Programmable Gain Name A / D Converters - SMT 0 Description Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address coarse_gain_ Configures the coarse gain setting cfg dB-gain enabled fine_gain_en Enable use of fine gain. Disabled cgain_ch1 <3:0> Programmable coarse gain for channel 1. 0dB gain cgain_ch2 <3:0> Programmable coarse gain for channel 2. 0dB gain cgain_ch3 <3:0> Programmable coarse gain for channel 3. 0dB gain cgain_ch4 <3:0> Programmable coarse gain for channel 4. 0dB gain fgain_ch1 <6:0> Programmable fine gain for channel 1 1x / 0dB gain X X X X X X X 0x34 fgain_ch2 <6:0> Programmable fine gain for channel 2 1x / 0dB gain X X X X X X X 0x35 fgain_ch3 <6:0> Programmable fine gain for channel 3 1x / 0dB gain X X X X X X X 0x36 fgain_ch4 <6:0> Programmable fine gain for channel 4 1x / 0dB gain X X X X X X X 0x37 X 0x33 X X X X X X X X X 0x2A X X X X X X X X The device includes a digital programmable gain in addition to the Full-scale control. The programmable gain of each channel can be individually set using a four bit code, indicated as cgain_ch*<3:0>. The gain is configured by the register cgain_cfg, when cgain_cfg equals `0' a gain in 0 1101 Not used dB steps is enabled as defined in table 17 otherwise 0 1110 Not used if cgain_cfg equals `1' the gain is defined by table 18. 0 Table 17. Gain Setting - dB Step cgain_cfg cgain_ch* <3:0> Implemented Gain (dB) 0 0 0 0 1 1 0 10 2 0 11 3 0 100 4 0 101 5 0 0 110 111 6 7 0 1000 8 0 1001 9 0 1010 10 0 1011 11 0 1100 12 32 1 1100 1 1101 50 1 1110 Not used 1 1111 Not used 1111 Not used Table 18. Gain Setting - x Step cgain_cfg cgain_ch* <3:0> 1 0 Implemented Gain Factor (X) 1 1 1 1.25 1 10 2 1 11 2.5 1 100 4 1 101 5 1 110 8 1 111 10 1 1000 12.5 1 1001 16 1 1010 20 1 1011 25 There is a digital fine gain implemented for each ADC to adjust the fine gain errors between the ADCs. The gain is controlled by fgain_branch* as defined in the following table. To enable the fine gain function the register bit fine_ gain_en has to be activated, set to `1'. 0 - 23 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Table 19. Fine Gain Setting Arithmetic Function Implemented Gain (X) 0 1 fgain_branchx <6:0> 1 1 1 1 1 OUT=(1+2-8+2-9+2-10+2-11+2-12+2-13)*IN 1.008 0.067 0 0 0 0 0 0 0 OUT=IN 1.000 0.000 1 1 1 1 1 1 1 OUT=IN 1.000 0.000 1 0 0 0 0 0 0 OUT=(1-2 -2 -2 -2 -2 -2 )*IN 0.992 -0.067 -8 -9 -10 -11 -12 -13 Gain (dB) Analog Input Invert Name Description Default invert_ch <4:1> Channel specific swapping of the analog input signal. IPx is positive input D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address X X X X 0x24 The IPx pin represents the positive analog input pin, and INx represents the negative (complementary) input. Setting the bits marked invert_ch<n:1> (individual control for each channel) causes the inputs to be swapped. INx would then represent the positive input, and IPx the negative input. 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address Name Description Default en_ramp Enables a repeating full-scale ramp pattern on the outputs. Inactive X 0 0 dual_custom_ pat Enable the mode wherein the output toggles between two defined codes. Inactive 0 X 0 single_custom_ pat Enables the mode wherein the output is a constant specified code. Inactive 0 0 X bits_custom1 <15:0> Bits for the single custom pattern and for the first code of the dual custom pattern. <0> is the LSB. 0x0000 X X X X X X X X X X X X X X X X 0x26 bits_custom2 <15:0> Bits for the second code of the dual custom pattern. 0x0000 X X X X X X X X X X X X X X X X 0x27 pat_deskew Enable deskew pattern mode. Inactive 0 X pat_sync Enable sync pattern mode. Inactive X 0 To ease the LVDS synchronization setup of HMCAD1060, several test patterns can be set up on the outputs. Normal ADC data are replaced by the test pattern in these modes. Setting en_ramp to `1' sets up a repeating full-scale ramp pattern on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero code and starts the ramp again after reaching the full-scale code. A constant value can be set up on the outputs by setting single_custom_pat to `1', and programming the desired value in bits_custom1<15:0>. In this mode, bits_custom1<15:0> replaces the ADC data at the output, and is controlled by LSB-first and MSB-first modes in the same way as normal ADC data are. The device may also be set up to alternate between two codes by programming dual_custom_pat to `1'. The two codes are the contents of bits_custom1<15:0> and bits_custom2<15:0>. Since bit_custom*<15:0> is a 16 bit word there will be a truncation at the LSB side when using less than 16 bits 0x25 0x45 in the LVDS output word. If 12-bit output is selected bit <15:4> will be used, if 14-bit output is used bit <15:2> will be used and if dual 8-bit is selected bit<15:8> will be put on the LVDS `A' output and bit <7:0> will be put on the LVDS `B' output. Two preset patterns can also be selected: A / D Converters - SMT LVDS Test Patterns 1. Deskew pattern: Set using pat_deskew, this mode replaces the ADC output with a pattern consisting of alternating zeros and ones - MSB will be a zero. For a 14-bit output the pattern will be: `01010101010101' 2.Sync pattern: Set using pat_sync, the normal ADC word is in this mode replaced by a fixed synchronization pattern where the output word is split in two and the upper part of the word is ones and the lower part is zeros. For a 14-bit output the pattern will be: `11111110000000' . Note: Only one of the above patterns should be selected at the same time. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 24 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Theory of Operation HMCAD1060 is a 4-channel, high-speed, CMOS ADC. HMCAD1060 utilizes a LVDS output, described in `Register Description, LVDS Output Configuration and Control'. The 8x/14x/16x clock required for the serializer is generated internally from FCLK. All four channels of HMCAD1060 operate from one clock input, which can be differential or single ended. The sampling clocks for each of the four channels are generated from the clock input using a carefully matched clock buffer tree. A / D Converters - SMT 0 HMCAD1060 uses internally generated references. The differential reference value is 1V. This results in a differential input of -1V to correspond to the zero code of the ADC, and a differential input of +1V to correspond to the full-scale code (code 16383). Figure 10 shows a simplified drawing of the input network. The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. DC-Coupling Figure 11 shows a recommended configuration for DC-coupling. Note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_EXT output should be used as reference to set the common mode voltage. The ADC employs a Pipeline converter architecture. Each Pipeline Stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at 14-bit level. HMCAD1060 operates from two sets of supplies and grounds. The analog supply and ground set is identified as AVDD and AVSS, while the digital set is identified by DVDD and DVSS. Recommended Usage Analog Input The analog input to HMCAD1060 is a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The VCM pin provides a voltage suitable as common mode voltage reference. The internal buffer for the VCM voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_bc<1:0> register. Figure 11. DC coupled input The input amplifier could be inside a companion chip or it could be a dedicated amplifier. Several suitable single ended to differential driver amplifiers exist in the market. The system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with HMCAD1060 input specifications. Detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 11 must be varied according to the recommendations for the driver. AC-Coupling Figure 12. Transformer coupled input Figure 10. Input configuration 0 - 25 A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 12 shows a recommended configuration using a For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. Figure 13. AC coupled input Figure 13 shows AC-coupling using capacitors. Resistors from the CM_EXT output, RCM, should be used to bias the differential input signals to the correct voltage. The series capacitor, CI, form the highpass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. Note that Start Up Time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. Clock Input and Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In HMCAD1060 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% are acceptable. The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, hence a wide common mode voltage range is accepted. Differential clock sources such as LVDS, LVPECL or differential sine wave can be connected directly to the input pins. For CMOS inputs, the CLKN pin should be connected to ground, and the CMOS clock signal should be connected to CLKP. For differential sine wave clock input the amplitude must be at least +/- 0.8 Vpp. No additional configuration is needed to set up the clock source format. The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation 1. SNRjitter = 20 * log (2 * * IN * t) (1) where fIN is the signal frequency, and t is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. 0 A / D Converters - SMT transformer. Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. The bandwidth should exceed the sampling rate of the ADC with at least a factor of 10. It is also important to minimize phase mismatch between the differential ADC inputs for good HD2 performance. This type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. If the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the ADC clock input. Outline Drawing For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 26 HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter A / D Converters - SMT 0 Table 20: Dimensions Symbol Millimeter Inch Min Typ Max Min Typ Max A 0.8 0.9 1 0.031 0.035 0.039 A1 0 0.02 0.05 0 0.001 0.002 A2 b 0.2 0.18 D 0.25 0.008 0.3 0.007 7.00 bsc 0.01 0.012 0.276 bsc D2 5.15 5.3 5.4 0.203 0.209 0.213 L 0.3 0.4 0.5 0.012 0.016 0.02 e F 0.50 bsc 0.8 0.020 bsc 0.031 Package Information Part Number Package Body Material Lead Finish MSL [1] Package Marking [2] HMCAD1060 RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn Level 2A ASD0610 XXXX XXXX [1] MSL, Peak Temp: The moisture sensitivity level rating classified according to the JEDEC industry standard and to peak solder temperature. [2] Proprietary marking XXXX, 4-Digit lot number XXXX 0 - 27 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1060 v02.0411 Quad 14-Bit 20 to 105 MSPS A/D Converter Notes: A / D Converters - SMT 0 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel * 978-250-3373 fax * Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 28