UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION DATE
Preliminary Rev. 0.5 Original. Mar, 2001
Preliminary Rev. 0.6
1. The symbols CE# and OE# and WE# are revised as.CE
and OEand WE .
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
Jun 21,2001
Preliminary Rev. 0.7 1. Add SOP and STSOP package Dec 18,2001
Preliminary Rev. 0.8
1. Revised 36-pin TFBGA package outline dimension：
a、 Rev. 0.7 : ball diameter=0.3mm
b、 Rev. 0.8 : ball diameter=0.35mm
2. Revised DC ELECTRICAL CHARACTERISTICS：
a、 Revised VIH as 2.2V
Apr 30,2002
Rev. 1.0
1. Revised Fast access time : 55/70/100ns
55ns (max.) for Vcc=3.0V~3.6V
70/100ns (max.) for Vcc=2.7V~3.6V
2. Revised Output Disable to Output in High Z (tOHZ*) : 3035ns
Aug 30,2002
Rev. 1.1
1. Revised Operation surrent :
-Icc(max) 45/35/25mA40/30/25mA
-Icc(Typ) 30/25/20mA30/20/16mA
2. Revised Standby current : 20/3uA20/2uA
3. Revised VOH(Typ) : NA2.7V
4. Add VIH(max)=VCC+2.0V for pulse width less than 10ns.
V
IL(min)=VSS-2.0V for pulse width less than 10ns.
5. Revised AC Table tOHZ* characteristics
6. Add order information for lead free product
May 06,2003
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
FEATURES
Fast access time : 55/70/100ns
CMOS Low power operating
Operating current : 40/30/25mA (Icc max.)
Standby current : 20µA (typ.) L-version
2µA (typ.) LL-version
Single 2.7V~3.6V power supply
Industrial Temperature : -40℃~85℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage : 1.5V (min)
Package : 32-pin 450mil SOP
32-pin 8mm × 20mm TSOP-I
32-pin 8mm × 13.4mm STSOP
36-pin 6mm × 8mm TFBGA
GENERAL DESCRIPTION
The UT62L5128(I) is a 4,194,304-bit low power CMOS
static random access memory organized as 524,288
words by 8 bits. It is fabricated using high performa nce,
high reliability CMOS technology.
The UT62L5128(I) operates from a wide range
2.7V~3.6V power supply and supports industrial
operating temperature range.
The UT62L5128(I) is desig ned for high density and low
power memory applications. The device has a data
retention mode that guarantees data to remain valid at
a minimum power supply voltage of 1.5V.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
512K
×
8
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A18
Vcc
Vss
I/O1-I/O8
CE
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
PIN CONFIGURATION
SOP
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
A17
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
A13
A14
A18
A16
Vcc
A15
29
30
31
32
OE
CE
WE
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4 A3
TSOP-1 / STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
A17
A18
A15
32
31
30
29
A16
OE CE
WE
A12A11 A13
NC
A17
A10 A14
A15
I/O6
I/O7
I/O8
A9
Vss
A8
A16
I/O5
Vcc
Vcc
I/O4
A18
Vss
A7
A0
I/O3
I/O2
I/O1
A6A1 A3
A5NC
A4A2
123456
H
G
C
D
E
F
A
B
TFBGA
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A18 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
Vcc Power Supply
Vss Ground
NC No Connection
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 4
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM -0.5 to 4.6 V
Operating Temperature Industrial TA -40 to 85 ℃
Storage Temperature TSTG -65 to 150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
Soldering Temperature (under 10 secs) Tsolder 260 ℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE WE CE OE I/O OPERATION SUPPLY CURRENT
Standby X H X High – Z ISB, ISB1
Output Disable H L H High – Z ICC , ICC1, ICC2
Read H L L DOUT I
CC , ICC1, ICC2
Write L L X DIN I
CC , ICC1, ICC2
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA = -40℃ to 85℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Power Voltage VCC
2.7 3.0 3.6 V
Input High Voltage VIH*1 2.2 - VCC+0.3 V
Input Low Voltage VIL*2 -0.2 - 0.6 V
Input Leakage Current ILI VSS ≦VIN ≦VCC - 1 - 1 µA
Output Leakage Current ILO VSS ≦VI/O ≦VCC; Output Disable - 1 - 1 µA
Output High Voltage VOH I
OH= -1mA 2.2 2.7 - V
Output Low Voltage VOL I
OL= 2.1mA - - 0.4 V
55 -
30 40 mA
70 -
20 30 mA
Operating Power
Supply Current ICC Cycle time=min, 100%duty
II/O=0mA, CE=VIL 100 - 16 25 mA
ICC1 TCycle=
1µs - 4 5 mA
Average Operation
Current ICC2
100% duty, II/O=0mA, CE≦0.2,
other pins at 0.2V or Vcc-0.2V Tcycle=
500ns - 8 10 mA
Standby Current (TTL) ISB CE=VIH, other pins = VIH or VIL - 0.3 0.5 mA
-L - 20 80 µA
Standby Current (CMOS) ISB1 CE=VCC-0.2V
other pins at 0.2V or Vcc-0.2V -LL - 2 20 µA
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 5
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance CIN - 6 pF
Input/Output Capacitance CI/O - 8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF+1TTL , IOH/IOL = -1mA / 2.1mA
AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA = -40℃ to 85℃)
(1) READ CYCLE UT62L5128(I)-55 UT62L5128(I)-70 UT62L5128(I)-100
PARAMETER SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time tRC 55 - 70 - 100 - ns
Address Access Time tAA - 55 - 70 - 100 ns
Chip Enable Access Time tACE - 55 - 70 - 100 ns
Output Enable Access Time tOE - 30 - 35 - 50 ns
Chip Enable to Output in Low Z tCLZ* 10 - 10 - 10 - ns
Output Enable to Output in Low Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High Z tCHZ* - 20 - 25 - 30 ns
Output Disable to Output in High Z tOHZ* - 20 - 25 - 30 ns
Output Hold from Address Change tOH 10 - 10 - 10 - ns
(2) WRITE CYCLE UT62L5128(I)-55 UT62L5128(I)-70 UT62L5128(I)-100
PARAMETER SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time tWC 55 - 70 - 100 - ns
Address Valid to End of Write tAW 50 - 60 - 80 - ns
Chip Enable to End of Write tCW 50 - 60 - 80 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 45 - 55 - 70 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 25 - 30 - 40 - ns
Data Hold from End of Write Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High Z tWHZ* - 30 - 30 - 40 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 6
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2) tRC
tAA
Data Valid
Address
Dout
tOH tOH
Previous data valid
READ CYCLE 2 (CEand OE Controlled) (1,3,4,5)
tRC
tAA
tACE
tOE
tOHZ
tCLZ
tOH
tOLZ
High-Z Da ta Va lid High-Z
tCHZ
Address
Dout
CE
OE
Notes :
1. WE is high for read cycle.
2.Device is continuously selectedOE =low,CE =low.
3.Address must be valid prior to or coincident withCE =low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 7
WRITE CYCLE 1 (WE Controlled) (1,2,3,5,6)
tWC
tAW
tCW
tAS tWP
tWHZ tOW
tWR
High-Z
(4) (4)
Address
CE
WE
Dout
Din D a ta V a lid
tDW tDH
WRITE CYCLE 2 (CEControlled) (1,2,5,6) tWC
tAW
tCW
tAS tWR
tWP
tWHZ
tDW tDH
D ata Valid
High-Z
(4)
Address
CE
WE
Dout
Din
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 8
Notes :
1. WE ,CE must be high during all address transitions.
2.A write occurs during the overlap of a lowCE , low WE .
3.During a WE controlled write cycle withOE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If theCE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = -40℃ to 85℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention VDR CE ≧ V
CC-0.2V 1.5 - 3.6 V
- L - 1 50 µA
Data Retention Current IDR Vcc=1.5V
CE ≧ V
CC-0.2V - LL - 0.5 20 µA
Chip Disable to Data
Retention Time tCDR See Data Retention
Waveforms (below) 0 - - ms
Recovery Time tR 5 - - ms
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (CE controlled)
VDR ≧ 1.5V
CE ≧ VCC-0.2V
Vcc(min.) Vcc(min.)
VIH VIH
VCC
tR
tCDR
CE
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 9
PACKAGE OUTLINE DIMENSION
32-pin 450mil SOP Package Outline Dimension
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.118 (MAX) 2.997 (MAX)
A1 0.004 (MIN) 0.102 (MIN)
A2 0.111 (MAX) 2.82 (MAX)
b 0.016 (TYP) 0.406 (TYP)
D 0.817 (MAX) 20.75 (MAX)
E 0.445
±0.005 11.303
±0.127
E1 0.555
±0.012 14.097
±0.305
e 0.050 (TYP) 1.270 (TYP)
L 0.0347
±0.008 0.881
±0.203
L1 0.055
±0.008 1.397
±0.203
S 0.026 (MAX) 0.660 (MAX)
y 0.004 (MAX) 0.101 (MAX)
Θ 0o ~10o 0
o ~10o
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 10
32-pin 8mm x 13.4mm STSOP Package Outline Dimension
1
16 17
32
c
L
HD
D"A"
E
e
Seating Plane y
32
17
16
1
A2A1
A
0.254
0
GAUGE PLANE
SEATING PLANE
"A" DATAIL VIEW L1
b
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1 0.004
±0.002 0.10
±0.05
A2 0.039
±0.002 1.00
±0.05
b 0.008
±0.001 0.200
±0.025
D 0.465
±0.004 11.800
±0.100
E 0.315
±0.004 8.000
±0.100
e 0.020 (TYP) 0.50 (TYP)
HD 0.528
±0.008 13.40
±0.20.
L1 0.0315
±0.004 0.80
±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ 0
o∼5o 0
o∼5o
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 11
32-pin 8mm x 20mm TSOP-Ⅰ Package Outline Dimension
HD
e
bE
"A"
1
16
32
17
Seating Plane y
C
L
16 17
132 "A" DETAIL VIEW
D
A2A1
A
L1
SEATING PLANE
0
0.254
GAUGE PLANE
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1 0.004
±0.002 0.10
±0.05
A2 0.039
±0.002 1.00
±0.05
b 0.008 + 0.002
- 0.001 0.20 + 0.05
-0.03
D 0.724
±0.004 18.40
±0.10
E 0.315
±0.004 8.00
±0.10
e 0.020 (TYP) 0.50 (TYP)
HD 0.787
±0.008 20.00
±0.20
L1 0.0315
±0.004 0.80
±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ 0
o∼5o 0
o∼5o
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 12
36-Pin 6.0mm X 8.0mm TFBGA Package Outline Dimension
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 13
ORDERING INFORMATION
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) typ. PACKAGE
UT62L5128SC-55LI 55 20 32 PIN SOP
UT62L5128SC-55LLI 55 2 32 PIN SOP
UT62L5128SC-70LI 70 20 32 PIN SOP
UT62L5128SC-70LLI 70 2 32 PIN SOP
UT62L5128SC-100LI 100 20 32 PIN SOP
UT62L5128SC-100LLI 100 2 32 PIN SOP
UT62L5128LS-55LI 55 20 32 PIN STSOP
UT62L5128LS-55LLI 55 2 32 PIN STSOP
UT62L5128LS-70LI 70 20 32 PIN STSOP
UT62L5128LS-70LLI 70 2 32 PIN STSOP
UT62L5128LS-100LI 100 20 32 PIN STSOP
UT62L5128LS-100LLI 100 2 32 PIN STSOP
UT62L5128LC-55LI 55 20
32 PIN TSOP-Ⅰ
UT62L5128LC-55LLI 55 2
32 PIN TSOP-Ⅰ
UT62L5128LC-70LI 70 20
32 PIN TSOP-Ⅰ
UT62L5128LC-70LLI 70 2
32 PIN TSOP-Ⅰ
UT62L5128LC-100LI 100 20 32 PIN TSOP-Ⅰ
UT62L5128LC-100LLI 100 2 32 PIN TSOP-Ⅰ
UT62L5128BS-55LI 55 20 36 PIN TFBGA
UT62L5128BS-55LLI 55 2 36 PIN TFBGA
UT62L5128BS-70LI 70 20 36 PIN TFBGA
UT62L5128BS-70LLI 70 2 36 PIN TFBGA
UT62L5128BS-100LI 100 20 36 PIN TFBGA
UT62L5128BS-100LLI 100 2 36 PIN TFBGA
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 14
ORDERING INFORMATION (for lead free product)
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) typ. PACKAGE
UT62L5128SCL-55LI 55 20 32 PIN SOP
UT62L5128SCL-55LLI 55 2 32 PIN SOP
UT62L5128SCL-70LI 70 20 32 PIN SOP
UT62L5128SCL-70LLI 70 2 32 PIN SOP
UT62L5128SCL-100LI 100 20 32 PIN SOP
UT62L5128SCL-100LLI 100 2 32 PIN SOP
UT62L5128LSL-55LI 55 20 32 PIN STSOP
UT62L5128LSL-55LLI 55 2 32 PIN STSOP
UT62L5128LSL-70LI 70 20 32 PIN STSOP
UT62L5128LSL-70LLI 70 2 32 PIN STSOP
UT62L5128LSL-100LI 100 20 32 PIN STSOP
UT62L5128LSL-100LLI 100 2 32 PIN STSOP
UT62L5128LCL-55LI 55 20
32 PIN TSOP-Ⅰ
UT62L5128LCL-55LLI 55 2 32 PIN TSOP-Ⅰ
UT62L5128LCL-70LI 70 20
32 PIN TSOP-Ⅰ
UT62L5128LCL-70LLI 70 2 32 PIN TSOP-Ⅰ
UT62L5128LCL-100LI 100 20 32 PIN TSOP-Ⅰ
UT62L5128LCL-100LLI 100 2 32 PIN TSOP-Ⅰ
UT62L5128BSL-55LI 55 20 36 PIN TFBGA
UT62L5128BSL-55LLI 55 2 36 PIN TFBGA
UT62L5128BSL-70LI 70 20 36 PIN TFBGA
UT62L5128BSL-70LLI 70 2 36 PIN TFBGA
UT62L5128BSL-100LI 100 20 36 PIN TFBGA
UT62L5128BSL-100LLI 100 2 36 PIN TFBGA
UTRON UT62L5128(I)
Rev. 1.1 512K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80052
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 15
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