FS6209 Dual PLL VCXO Clock Generator IC 1.0 Features 2.0 * Dual phase-locked loop (PLL) device two output clock frequencies * On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning * 3.3V supply voltage * Small circuit board footprint (8-pin 0.150 SOIC) * Custom frequency selections available - contact your local AMI Sales Representative for more information Figure 1: Pin Configuration 1 VDD 2 XTUNE 3 VSS 4 FS6209 XIN 8 XOUT 7 VSS 6 CLKB 5 CLKA Description The FS6209 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems. At the core of the FS6209 is circuitry that implements a voltage-controlled crystal oscillator when an external resonator (nominally 13.5MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. Two high-resolution phase-locked loops generate two output clocks (CLKA and CLKB) through an array of postdividers. All frequencies are ratiometrically derived from the VCXO frequency. The locking of all the output frequencies together can eliminate unpredictable artifacts in video systems and reduce electromagnetic interference (EMI) due to frequency harmonic stacking. Table 1: Crystal / Output Frequencies 8-pin (0.150) SOIC DEVICE fXIN (MHz) CLKA (MHz) FS6209-01 13.5 54.0000 CLKB (MHz) 22.5792 (+1.12ppm) NOTE: Contact AMI for custom PLL frequencies Figure 2: Block Diagram XIN VCXO CLKA PLL XOUT DIVIDER ARRAY XTUNE PLL CLKB FS6209 American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ISO9001 2.28.02 FS6209 Dual PLL VCXO Clock Generator IC Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME DESCRIPTION 1 AI XIN VCXO Feedback 2 P VDD Power Supply (+3.3V) 3 AI XTUNE VCXO Tune 4 P VSS 5 DO CLKA Clock Output A Ground 6 DO CLKB Clock Output B 7 DO VSS 8 AO XOUT Ground VCXO Drive 3.0 Functional Block Description 3.1 Phase-Locked Loop (PLL) The oscillator operates the crystal resonator in the parallel-resonant mode. Crystal warping, or the "pulling" of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. Specifically, the motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the warping capability of the crystal in the oscillator circuit. A simple formula to obtain the warping capability of a crystal oscillator is: The on-chip PLLs are a standard frequency- and phaselocked loop architecture. The PLL multiplies the reference oscillator to the desired frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error. 3.2 Voltage-Controlled Crystal Oscillator (VCXO) The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6209 system components. Loading capacitance for the crystal is internal to the FS6209. No external components (other than the resonator itself) are required for operation of the VCXO. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is ??? nominal. When using a crystal with a VCXO, it is important that the crystal load capacitance (as specified in Table 4: Operating Conditions be matched to the load capacitance as presented by the VCXO. The crystal must be specified with the correct load capacitance to obtain the maximum tuning range. f ( ppm) = 6 C1 x (C L 2 - C L1) x 10 2 x (C 0 + C L 2 ) x (C 0 + C L1) where CL1 and CL2 are the two extremes of the applied load capacitance. EXAMPLE: A crystal with the following parameters is used. With C1 = 0.02pF, C0 = 5pF, CL1 = 10pF, and CL2 = 22.66pF, the coarse tuning range is f = 0.02 x (22.66 - 10) x 10 6 = 305 ppm . 2 x (5 + 22.66 ) x (5 + 10 ) 2 ISO9001 2.28.02 FS6209 Dual PLL VCXO Clock Generator IC 4.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 125 C 260 C 2 kV Supply Voltage (VSS = ground) Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 4: Operating Conditions PARAMETER SYMBOL Supply Voltage VDD Ambient Operating Temperature Range TA Crystal Resonator Frequency fXTAL CONDITIONS/DESCRIPTION 3.3V 10% MIN. TYP. MAX. 3.0 3.3 3.6 V 70 C 18 MHz 0 Fundamental Mode 5 13.5 UNITS Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF Crystal Loading Capacitance CL(xtal) AT cut 20 pF 3 ISO9001 2.28.02 FS6209 Dual PLL VCXO Clock Generator IC Table 5: DC Electrical Specifications Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Supply Current, Dynamic, with Loaded Outputs IDD fXTAL = 13.5MHz; CL = 10pF, VDD = 3.6V 30 mA Supply Current, Static IDD XIN = 0V, VDD = 3.6V 3 mA 20 pF Voltage Controlled Crystal Oscillator Crystal Loading Capacitance CL(xtal) As seen by a crystal connected to XIN and XOUT (@ VXTUNE = 1.65V) Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF VCXO Tuning Range fXTAL = 13.5MHz; CL(xtal) = 20pF; C1(xtal) = 25fF 300 ppm VCXO Tuning Characteristic Note: positive -F for positive -V 100 ppm/V Crystal Drive Level RXTAL=20; CL = 20pF 200 uW Crystal Oscillator Feedback (XIN) Threshold Bias Voltage VTH 860 mV High-Level Input Current IIH 34 A Low-Level Input Current IIL -21 A Crystal Oscillator Drive (XOUT) High-Level Output Source Current IOH V(XIN) = 3.3V, VO = 0V -0.5 mA Low-Level Output Sink Current IOL V(XIN) = 0V, VO = 3.3V 15 mA IOH VO = 2.0V -40 mA mA Clock Outputs (CLKA, CLKB) High-Level Output Source Current * Low-Level Output Sink Current * IOL VO = 0.4V 17 zOH VO = 0.1VDD; output driving high 25 zOL VO = 0.1VDD; output driving low 25 Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. -55 mA Short Circuit Sink Current * IOSL VO = 3.3V; shorted for 30s, max. 55 mA Output Impedance * 4 ISO9001 2.28.02 FS6209 Dual PLL VCXO Clock Generator IC Table 6: AC Timing Specifications Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS Overall VCXO Stabilization Time * PLL Stabilization Time * tVCXOSTB tPLLSTB Synthesis Error From power valid 10 ms From VCXO stable 500 us (unless otherwise noted in Frequency Table) 0 ppm 55 % Clock Output (CLKA) Duty Cycle * Ratio of high pulse width (as measured from rising edge to next falling edge at VDD/2) to one clock period 54.00 45 Jitter, Period (peak-peak) * tj(P) From rising edge to next rising edge at VDD/2, CL = 10pF 54.00 390 ps Jitter, Long Term (y()) * tj(LT) From 0-500s at VDD/2, CL = 10pF compared to ideal clock source 54.00 155 ps Rise Time * tr VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1.7 ns Fall Time * tf VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF 1.7 ns Clock Output (CLKB) Duty Cycle * Ratio of high pulse width (as measured from rising edge to next falling edge at VDD/2) to one clock period 22.579 45 55 % Jitter, Period (peak-peak) * tj(P) From rising edge to next rising edge at VDD/2, CL = 10pF 22.579 290 ps Jitter, Long Term (y()) * tj(LT) From 0-500s at VDD/2, CL = 10pF compared to ideal clock source 22.579 450 ps Rise Time * tr VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1.7 ns Fall Time * tf VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF 1.7 ns Figure 3: VCXO Range vs. Tuning Voltage TBD 5 ISO9001 2.28.02 FS6209 Dual PLL VCXO Clock Generator IC 5.0 Package Information Table 7: 8-pin SOIC (0.150") Package Dimensions 8 DIMENSIONS INCHES MIN. MAX. MILLIMETERS MIN. MAX. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 0.191 0.249 D 0.189 0.196 4.80 4.98 E 0.150 0.157 3.81 3.99 e 0.050 BSC R E H AMERICAN MICROSYSTEMS, INC. 1 ALL RADII: 0.005" TO 0.01" h x 45 B 7 typ. e 1.27 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 0 8 0 8 A2 A D C A1 BASE PLANE L SEATING PLANE Table 8: 8-pin SOIC (0.150") Package Characteristics PARAMETER SYMBOL Thermal Impedance, Junction to Free-Air 8-pin 0.150" SOIC JA Lead Inductance, Self L11 CONDITIONS/DESCRIPTION TYP. UNITS Air flow = 0 m/s 110 C/W Corner lead 2.0 Center lead 1.6 nH Lead Inductance, Mutual L12 Any lead to any adjacent lead 0.4 nH Lead Capacitance, Bulk C11 Any lead to VSS 0.27 pF 6 ISO9001 2.28.02 FS6209 Dual PLL VCXO Clock Generator IC 6.0 Ordering Information ORDERING CODE DEVICE NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11640-801 FS6209-01 8-pin (0.150") SOIC (Small Outline Package) 0C to 70C (Commercial) Tape and Reel 11640-811 FS6209-01 8-pin (0.150") SOIC (Small Outline Package) 0C to 70C (Commercial) Tubes Copyright (c) 1999 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com 7 ISO9001 2.28.02