FS6209-01 - AMI Semiconductor, Inc.

American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2.28.02

FS6209

FS6209FS6209

FS6209

Dual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator ICDual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

1.0 Features

• Dual phase-locked loop (PLL) device two output

clock frequencies

• On-chip tunable voltage-controlled crystal oscillator

(VCXO) allows precise system frequency tuning

• 3.3V supply voltage

• Small circuit board footprint (8-pin 0.150″ SOIC)

• Custom frequency selections available - contact your

local AMI Sales Representative for more information

Figure 1: Pin Configuration

1 8

XIN

VDD

XTUNE

VSS

CLKB

CLKA

XOUT

FS6209

8-pin (0.150″) SOIC

2.0 Description

The FS6209 is a monolithic CMOS clock generator IC

designed to m inim ize cost a nd com ponen t count in digi tal

video/audio systems.

At the core of the FS6209 is circuitry that implements a

voltage-controlled crystal oscillator when an external

resonator (nominally 13.5MHz) is attached. The VCXO

allows device frequencies to be precisely adjusted for use

in systems that have frequency matching requirements,

such as digital satellite receivers.

Two high-resolution phase-locked loops generate two

output clock s (C LKA and CL KB) through a n ar r ay of post-

dividers. All frequencies are ratiometrically derived from

the VCXO frequency. The locking of all the output fre-

quencies together can elim inate unpred ictable ar tifacts in

video systems and reduce electromagnetic interference

(EMI) due to frequency harmonic stacking.

Table 1: Crystal / Output Frequencies

DEVICE fXIN (MHz) CLKA (MHz) CLKB (MHz)

FS6209-01 13.5 54.0000 22.5792

(+1.12ppm)

NOTE: Contact AMI for custom PLL frequencies

Figure 2: Block Diagram

VCXO

FS6209

PLL

XOUT

XIN

CLKB

CLKA

XTUNE

DIVIDER

ARRAY

PLL

22.28.02

FS6209

FS6209FS6209

FS6209

Dual PLL VCXO

Dual PLL VCXODual PLL VCXO

Dual PLL VCXO Clock Generator IC

Clock Generator ICClock Generator IC

Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

Table 2: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digi tal Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN TYPE NAME DESCRIPTION

1 AI XIN VCXO Feedback

2 P VDD Power Supply (+3.3V)

3 AI XTUNE VCXO Tune

4 P VSS Ground

5DOCLKAClock Output A

6DOCLKBClock Output B

7 DO VSS Ground

8 A O XOUT VCXO Drive

3.0 Functional Bl ock Descripti on

3.1 Phase-Locked Loop (PLL)

The on-chip PLLs are a standard frequency- and phase-

lock ed loop archi tec tur e. The PLL multiplies t he r ef er enc e

oscillator to the desired frequency by a ratio of integers.

The frequency multiplication is exact with a zero synthe-

sis error.

3.2 Voltage-Controlled Crystal

Oscillator (VCXO)

The VCXO provides a tunable, low-jitter frequency refer-

ence for the rest of the FS6209 system components.

Loading capacitance for the crystal is internal to the

FS6209. No external components (other than the reso-

nator itself) are required for operation of the VCXO.

Continuous fine-tuning of the VCXO frequency is accom-

plished by varying the voltage on the XTUNE pin. The

total change (from one extreme to the other) in effective

loading capacitance is ??? nominal.

W hen using a crystal with a VCXO, it is im portant that th e

crystal load capacitance (as specified in Table 4: Oper-

ating Conditions be matched to the load capacitance as

presented by the VCXO. The crystal must be specified

with the correct load capacitance to obtain the maximum

tuning range.

The oscillator operates the crystal resonator in the paral-

lel-reso nant mode. Cr ystal warpin g, or the “pul ling” of the

crystal oscillation frequency, is accomplished by altering

the eff ective load ca pacitance presented to the crystal b y

the oscillator circuit. T he actual amount that changin g the

load capacitance alters the oscillator frequency will be

dependent o n the charac teristics of the cr ystal as well as

the oscillator circuit itself.

Specifically, the motional capacitance of the cr ystal (usu-

ally referr ed to by cr ystal m anufactur ers as C1), the st atic

capacitance of the crystal (C0), and the load capacitance

(CL) of the oscillator determine the warping capability of

the crystal in the oscillator circuit.

A simple formula to obtain the warping capability of a

crystal oscillator is:

()

()()

CCCC CCC

ppmf LL

1020

121

210

)( +×+× ×−×

=∆

where CL1 and CL2 are the two extremes of the applied

load capacitance.

EXAMPLE: A crystal with the following parameters is

used. With C1 = 0.02 pF, C0 = 5pF, CL1 = 10pF, a nd CL2 =

22.66pF, the coarse tuning range is

()

()()

ppm

f305

105662252 106

106622020 =

+×+× ×−×

=∆ .

32.28.02

FS6209

FS6209FS6209

FS6209

Dual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator ICDual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

4.0 Electrical Specifications

Table 3: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER SYMBOL MIN. MAX. UNITS

Supply Voltage (VSS = ground) VDD VSS-0.5 7 V

Input Voltage, dc VIVSS-0.5 VDD+0.5 V

Output Voltage, dc VOVSS-0.5 VDD+0.5 V

Input Clamp Current, dc (V I < 0 or VI > VDD)I

IK -50 50 mA

Output Clamp Current, dc (VI < 0 or VI > VDD)I

OK -50 50 mA

Storage Temperature Range (non-condensing) TS-65 150 °C

Ambient Temperature Range, Under Bias TA-55 125 °C

Junction Temperature TJ125 °C

Lead Temperature (soldering, 10s) 260 °C

Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage res ulting in a loss of functi onality or performance may occur if this devic e is subjected to a high-energy elec-

trostatic discharge.

Table 4: Operating Conditions

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Supply Voltage VDD 3.3V ± 10% 3.0 3.3 3.6 V

Ambient Operating Temperature Range TA070°C

Crystal Resonator Frequency fXTAL Fundamental Mode 5 13.5 18 MHz

Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF

Crystal Loadi ng Capaci tance CL(xtal) AT cut 20 pF

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FS6209

FS6209FS6209

FS6209

Dual PLL VCXO

Dual PLL VCXODual PLL VCXO

Dual PLL VCXO Clock Generator IC

Clock Generator ICClock Generator IC

Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

Table 5: DC Electrical Specifications

Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

Supply Current, Dynamic, with Loaded

Outputs IDD fXTAL = 13.5MHz; CL = 10pF, VDD = 3.6V 30 mA

Supply Current, Static IDD XIN = 0V, VDD = 3.6V 3 mA

Voltage Controlled Crystal Oscillator

Crystal Loadi ng Capaci tance CL(xtal) As seen by a crystal connect ed to XIN and

XOUT (@ VXTUNE = 1.65V) 20 pF

Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF

VCXO Tuning Range fXTAL = 13.5MHz; CL(xtal) = 20pF; C1(xtal) = 25fF 300 ppm

VCXO Tuning Characterist ic Note: positive -F for positive -V100 ppm/V

Crystal Dri ve Level RXTAL=20Ω; CL = 20pF 200 uW

Crystal Oscillator Feedback (XIN)

Threshold Bias Voltage VTH 860 mV

High-Level Input Current IIH 34 µA

Low-Level Input Current IIL -21 µA

Crystal Oscillator Drive (XOUT)

High-Level Output Sourc e Current IOH V(XIN) = 3.3V , VO = 0V -0.5 mA

Low-Level Output Sink Current IOL V(XIN) = 0V, VO = 3.3V 15 mA

Clock Outputs (CLKA, CLKB)

High-Level Output Sourc e Current * IOH VO = 2.0V -40 mA

Low-Level Output Sink Current * IOL VO = 0.4V 17 mA

zOH VO = 0.1VDD; out put driving hi gh 25

Output Impedance * zOL VO = 0.1VDD; out put driving l ow 25 Ω

Short Circuit S ource Current * IOSH VO = 0V; shorted for 30s, max. -55 mA

Short Circuit S i nk Current * IOSL VO = 3.3V; shorted for 30s, max. 55 mA

52.28.02

FS6209

FS6209FS6209

FS6209

Dual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator ICDual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

Table 6: AC Timing Specifications

Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK

(MHz) MIN. TYP. MAX. UNITS

Overall

VCXO Stabilization Time * tVCXOSTB From power valid 10 ms

PLL Stabilization Time * tPLLSTB From VCXO stable 500 us

Synthesis Error (unless otherwise noted in Frequency Table) 0 ppm

Clock Output (CLKA)

Duty Cycle * Ratio of high pulse width (as measured from rising edge

to next falling edge at VDD/2) to one clock period 54.00 45 55 %

Jitter, Period (peak-peak) * tj(∆P) From rising edge to next rising edge at

VDD/2, CL = 10pF 54.00 390 ps

Jitter, Long Term (σy(τ)) * tj(LT) From 0-500µs at VDD/2, CL = 10pF

compared to ideal clock source 54.00 155 ps

Rise Time * trVDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1.7 ns

Fall Time * tfVDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF 1.7 ns

Clock Output (CLKB)

Duty Cycle * Ratio of high pulse width (as measured from rising edge

to next falling edge at VDD/2) to one clock period 22.579 45 55 %

Jitter, Period (peak-peak) * tj(∆P) From rising edge to next rising edge at

VDD/2, CL = 10pF 22.579 290 ps

Jitter, Long Term (σy(τ)) * tj(LT) From 0-500µs at VDD/2, CL = 10pF

compared to ideal clock source 22.579 450 ps

Rise Time * trVDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1.7 ns

Fall Time * tfVDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF 1.7 ns

Figure 3: VCXO Range vs. Tuning Voltage

TBD

62.28.02

FS6209

FS6209FS6209

FS6209

Dual PLL VCXO

Dual PLL VCXODual PLL VCXO

Dual PLL VCXO Clock Generator IC

Clock Generator ICClock Generator IC

Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

5.0 Package Information

Table 7: 8-pin SOIC (0.150") Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

MIN. MAX. MIN. MAX.

A 0.061 0.068 1.55 1.73

A1 0.004 0.0098 0.102 0.249

A2 0.055 0.061 1.40 1.55

B 0.013 0.019 0.33 0.49

C 0.0075 0.0098 0.191 0.249

D 0.189 0.196 4.80 4.98

E 0.150 0.157 3.81 3.99

e 0.050 BSC 1.27 BSC

H 0.230 0.244 5.84 6.20

h 0.010 0.016 0.25 0.41

L 0.016 0.035 0.41 0.89

Θ0°8°0°8°

SEATING

PLANE

1ALL RADII:

0.005" TO 0.01"

BASE

PLANE

AMERICAN MICROSYSTEMS, INC.

7° typ.h x 45°

Table 8: 8-pin SOIC (0.150") Package Characteristics

PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS

Thermal Impedance, Junction to Free-Air

8-pin 0.150” SOIC ΘJA Air flow = 0 m/s 110 °C/W

Corner lead 2.0

Lead Inductanc e, Self L11 Center lead 1.6 nH

Lead Inductanc e, Mutual L12 Any lead to any adjacent l ead 0.4 nH

Lead Capacitance, Bulk C11 Any lead to VSS 0.27 pF

72.28.02

FS6209

FS6209FS6209

FS6209

Dual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator ICDual PLL VCXO Clock Generator IC

Dual PLL VCXO Clock Generator IC

ISO9001

ISO9001ISO9001

ISO9001

6.0 Ordering Information

ORDERING CODE DEVICE NUM BER PACKAGE TYPE OPERATING

TEMPERATURE RANGE SHIPPING

CONFIGURATION

11640-801 FS6209-01 8-pin (0.150”) S OIC

(Small Outl i ne Package) 0°C to 70°C (Commercial) Tape and Reel

11640-811 FS6209-01 8-pin (0.150”) S OIC

(Small Outl i ne Package) 0°C to 70°C (Commercial) Tubes

Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI

makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom

of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-

serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are

intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-

ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not rec om-

mended without additional processing by AMI for such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,

WWW Address: http://www.amis.com E-mail: tgp@amis.com