_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
19-5122; Rev 2; 11/10
Ordering Information
Functional Diagram
General Description
The MAX5392 dual, 256-tap, volatile, low-voltage, lin-
ear taper digital potentiometer offers three end-to-end
resistance values of 10kI, 50kI, and 100kI. Operating
from a single +1.7V to +5.5V power supply, the device
provides a low 35ppm/NC end-to-end temperature coef-
ficient. The device features an I2C interface.
The small package size, low supply operating voltage,
low supply current, and automotive temperature range
of the MAX5392 makes the device uniquely suited for
the portable consumer market, battery-backup industrial
applications, and the automotive market.
The MAX5392 is specified over the automotive -40NC to
+125NC temperature range and is available in a 16-pin
TSSOP package.
Applications
Low-Voltage Battery Applications
Portable Electronics
Mechanical Potentiometer Replacement
Offset and Gain Control
Adjustable Voltage References/Linear Regulators
Automotive Electronics
Features
S Dual, 256-Tap Linear Taper Positions
S Single +1.7V to +5.5V Supply Operation
S Low 12µA Quiescent Supply Current
S 10kI, 50kI, 100kI End-to-End Resistance Values
S I2C-Compatible Interface
S Wiper Set to Midscale on Power-Up
S -40NC to +125NC Operating Temperature Range
Note: All devices are specified over the -40°C to +125NC oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
PART PIN-PACKAGE END-TO-END
RESISTANCE (kI)
MAX5392LAUE+ 16 TSSOP 10
MAX5392MAUE+ 16 TSSOP 50
MAX5392NAUE+ 16 TSSOP 100
LATCH
I2C
CHARGE
PUMP
BYP
GND
VDD
256 DECODER
256 DECODER
WA
HA LA
HB
WB
LB
LATCH
POR
SCL
SDA
A0
A1
A2
MAX5392
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
2 ______________________________________________________________________________________
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VDD to GND ...........................................................-0.3V to +6V
H_, W_, L_ to GND ......................................-0.3V to the lower of
(VDD + 0.3V) and +6V
All Other Pins to GND .............................................-0.3V to +6V
Continuous Current in to H_, W_, and L_
MAX5392L ..................................................................... Q5mA
MAX5392M .................................................................... Q2mA
MAX5392N ..................................................................... Q1mA
Continuous Power Dissipation (TA = +70NC)
16-Pin TSSOP (derate 11.1mW/NC above +70NC) ...888.9mW
Operating Temperature Range ....................... -40NC to +125NC
Junction Temperature ....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V,
TA = +25NC.) (Note 1)
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Resolution N 256 Tap
DC PERFORMANCE (Voltage Divider Mode)
Integral Nonlinearity INL (Note 2) -0.5 +0.5 LSB
Differential Nonlinearity DNL (Note 2) -0.5 +0.5 LSB
Dual Code Matching Register A = Register B -0.5 +0.5 LSB
Ratiometric Resistor Tempco (DVW/VW)/DT, no load 5ppm/NC
Full-Scale Error Code = FFh
MAX5392L -3 -2.2
LSBMAX5392M -1 -0.6
MAX5392N -0.5 -0.3
Zero-Scale Error Code = 00h
MAX5392L 2.2 3
LSBMAX5392M 0.6 1.0
MAX5392N 0.3 0.5
DC PERFORMANCE (Variable Resistor Mode)
Integral Nonlinearity R-INL
MAX5392L (Note 3) -1.5 +1.5
LSBMAX5392M (Note 3) -0.75 +0.75
MAX5392N (Note 3) -0.5 +0.5
Differential Nonlinearity R-DNL (Note 3) -0.5 +0.5 LSB
DC PERFORMANCE (Resistor Characteristics)
Wiper Resistance RWL (Note 4) 200 I
Terminal Capacitance CH_, CL_ Measured to GND 10 pF
Wiper Capacitance CW_ Measured to GND 50 pF
End-to-End Resistor Tempco TCRNo load 35 ppm/NC
End-to-End Resistor Tolerance DRHL Wiper not connected -25 +25 %
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V,
TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC PERFORMANCE
Crosstalk (Note 5) -90 dB
-3dB Bandwidth BW
Code = 80H,
10pF load,
VDD = 1.8V
MAX5392L 600
kHzMAX5392M 100
MAX5392N 50
Total Harmonic Distortion Plus
Noise THD+N Measured at W, VH_ = 1VRMS at 1kHz 0.02 %
Wiper Settling Time tS(Note 6)
MAX5392L 400
nsMAX5392M 1200
MAX5392N 2200
Charge-Pump Feedthrough at W_ VRW fCLK = 600kHz, CBYP = 0nF 600 nVP-P
POWER SUPPLIES
Supply Voltage Range VDD 1.7 5.5 V
Standby Current VDD = 5.5V 27 FA
VDD = 1.7V 12
DIGITAL INPUTS
Minimum Input High Voltage VIH
VDD = 2.6V to 5.5V 70 % x VDD
VDD = 1.7V to 2.6V 75
Maximum Input Low Voltage VIL
VDD = 2.6V to 5.5V 30 % x VDD
VDD = 1.7V to 2.6V 25
Input Leakage Current -1 +1 FA
Input Capacitance 5 pF
TIMING CHARACTERISTICS—I2C (Notes 7 and 8)
Maximum SCL Frequency fSCL 400 kHz
Setup Time for START Condition tSU:STA 0.6 Fs
Hold Time for START Condition tHD:STA 0.6 Fs
SCL High Time tHIGH 0.6 Fs
SCL Low Time tLOW 1.3 Fs
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
4 ______________________________________________________________________________________
Figure 1. Voltage-Divider and Variable Resistor Configurations
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V,
TA = +25NC.) (Note 1)
Note 1: All devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design
and characterization.
Note 2: DNL and INL are measured with the potentiometer configured as a voltage-divider (Figure 1) with H_ = VDD and L_ = GND.
The wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
Note 3: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). DNL and INL are mea-
sured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ = GND. For VDD = +5V, the wiper
terminal is driven with a source current of 400FA for the 10kI configuration, 80FA for the 50kI configuration, and 40FA for
the 100kI configuration. For VDD = +1.7V, the wiper terminal is driven with a source current of 150FA for the 10kI configu-
ration, 30FA for the 50kI configuration, and 15FA for the 100kI configuration.
Note 4: The wiper resistance is the worst value measured by injecting the currents given in Note 3 to W_ with L_ = GND.
RW_ = (VW_ - VH_)/IW_.
Note 5: Drive HA with a 1kHz GND to VDD amplitude tone. LA = LB = GND. No load. WB is at midscale with a 10pF load. Measure
WB.
Note 6: The wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. H_ = VDD, L_ = GND,
and the wiper terminal is loaded with 10pF capacitance to ground.
Note 7: Digital timing is guaranteed by design and characterization, not production tested.
Note 8: The SCL clock period includes rise and fall times (tR = tF). All digital input signals are specified with tR = tF = 2ns and timed
from a voltage level of (VIL + VIH)/2.
Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. For I2C-bus specification infor-
mation from NXP Semiconductor (formerly Philips Semiconductor), refer to the UM10204: I2C-Bus Specification and User
Manual.
H
L
W W
N.C.
L
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Setup Time tSU:DAT 100 ns
Data Hold Time tHD:DAT 0Fs
SDA, SCL Rise Time tR0.3 Fs
SDA, SCL Fall tF0.3 Fs
Setup Time for STOP Condition tSU:STO 0.6 Fs
Bus Free Time Between STOP and
START Condition tBUF Minimum power-up rate = 0.2V/Fs1.3 Fs
Pulse Suppressed Spike Width tSP 50 ns
Capacitive Load for Each Bus CB(Note 9) 400 pF
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX5392 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
1109580655035205-10-20
5
10
15
20
25
30
0
-40 125
VDD = 5V
VDD = 1.8V
VDD = 2.6V
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
MAX5392 toc02
DIGITAL INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
4.54.03.53.02.52.01.51.00.5
10
100
1000
10,000
1
0 5.0
VDD = 5V
VDD = 2.6V
VDD = 1.8V
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5392 toc03
VDD (V)
IDD (µA)
5.24.74.23.73.22.72.2
15
20
25
30
10
1.7
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (10kI)
MAX5392 toc04
TAP POSITION
W_-TO-L_ RESISTANCE (kI)
1
2
3
4
5
6
7
8
9
10
0
204153102510 255
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (50kI)
MAX5392 toc05
TAP POSITION
W_-TO-L_ RESISTANCE (kI)
5
10
15
20
25
30
35
40
45
50
0
204153102510 255
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (100kI)
MAX5392 toc06
TAP POSITION
W_-TO-L_ RESISTANCE (kI)
10
20
30
40
50
60
70
80
90
100
0
204153102510 255
WIPER RESISTANCE
vs. WIPER VOLTAGE (10kI)
WIPER VOLTAGE (V)
WIPER RESISTANCE (I)
0.5
80
100
120
140
60
0 1.0
MAX5392 toc07
VDD = 5V
VDD = 2.6V
VDD = 1.8V
5.04.54.03.53.02.52.01.5
END-TO-END RESISTANCE PERCENTAGE
CHANGE vs. TEMPERATURE
MAX5392 toc08
TEMPERATURE (°C)
END-TO-END RESISTANCE % CHANGE
11095-25 -10 5 35 50 6520 80
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
100kI
10kI
50kI
-0.03
-40 125
VARIABLE RESISTOR DNL
vs. TAP POSITION (10kI)
MAX5392 toc09
TAP POSITION
DNL (LSB)
20415310251
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
0 255
IWIPER = 150µA
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
6 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
VARIABLE RESISTOR DNL
vs. TAP POSITION (50kI)
MAX5392 toc10
TAP POSITION
DNL (LSB)
20415310251
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
0 255
IWIPER = 30µA
VARIABLE RESISTOR DNL
vs. TAP POSITION (100kI)
MAX5392 toc11
TAP POSITION
DNL (LSB)
20415310251
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
0 255
IWIPER = 15µA
VARIABLE RESISTOR INL
vs. TAP POSITION (10kI)
MAX5392 toc12
TAP POSITION
INL (LSB)
20415310251
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 255
IWIPER = 150µA
VARIABLE RESISTOR INL
vs. TAP POSITION (50kI)
MAX5392 toc13
TAP POSITION
INL (LSB)
20415310251
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 255
IWIPER = 30µA
VARIABLE RESISTOR INL
vs. TAP POSITION (100kI)
MAX5392 toc14
TAP POSITION
INL (LSB)
20415310251
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 255
IWIPER = 15µA
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (10kI)
MAX5392 toc15
TAP POSITION
DNL (LSB)
20415310251
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
0 255
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (50kI)
MAX5392 toc16
TAP POSITION
DNL (LSB)
20415310251
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
0 255
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (100kI)
MAX5392 toc17
TAP POSITION
DNL (LSB)
20415310251
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
0 255
VOLTAGE-DIVIDER INL
vs. TAP POSITION (10kI)
MAX5392 toc18
TAP POSITION
INL (LSB)
20415310251
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 255
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
VOLTAGE-DIVIDER INL
vs. TAP POSITION (100kI)
MAX5392 toc20
TAP POSITION
INL (LSB)
20415310251
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 255
VOLTAGE-DIVIDER INL
vs. TAP POSITION (50kI)
MAX5392 toc19
TAP POSITION
INL (LSB)
20415310251
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 255
TAP-TO-TAP SWITCHING TRANSIENT
(CODE 127 TO 128) 10kI
MAX5392 toc21
VW_-L_
20mV/div
SCL
5V/div
400ns/div
VDD = 5V
TAP-TO-TAP SWITCHING TRANSIENT
(CODE 127 TO 128) 100kI
MAX5392 toc23
VW_-L_
20mV/div
SCL
5V/div
1µs/div
VDD = 5V
TAP-TO-TAP SWITCHING TRANSIENT
(CODE 127 TO 128) 50kI
MAX5392 toc22
VW_-L_
20mV/div
SCL
5V/div
1µs/div
VDD = 5V
P0WER-ON TRANSIENT (50kI)
MAX5392 toc24
VW_-L_
1V/div
VCC
5V/div
2µs/div
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
8 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = 1.8V, TA = +25°C, unless otherwise noted.)
CROSSTALK vs. FREQUENCY
MAX5392 toc28
FREQUENCY (kHz)
CROSSTALK (dB)
1001010.1
-120
-100
-80
-60
-40
-20
0
-140
0.01 1000
100kI
50kI
10kI
CHARGE-PUMP FEEDTHROUGH
AT W_ vs. CBYP
MAX5392 toc31
CAPACITANCE (pF)
VOLTAGE (nVRMS)
600400200
100
200
300
400
500
600
700
0
0 800
BYP RAMP TIME vs. CBYP
MAX5392 toc30
BYP CAPACITANCE (µF)
RAMP TIME (ms)
0.080.050.040.02
20
40
60
80
100
120
0
0 0.10
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX5392 toc29
FREQUENCY (kHz)
THD+N (%)
1010.1
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0
0.01 100
10kI
50kI
100kI
CHARGE-PUMP FEEDTHROUGH AT W_
vs. FREQUENCY
MAX5392 toc32
FREQUENCY (kHz)
AMPLITUDE (µVRMS)
800700600500400
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
300 900
MIDSCALE FREQUENCY
RESPONSE (10kI)
FREQUENCY (kHz)
GAIN (dB)
10001001010.1
-20
-10
0
10
-30
0.01 10,000
MAX5392 toc25
VDD = 1.8V
VDD = 5V
VIN = 1VP-P
CW = 10pF
MIDSCALE FREQUENCY
RESPONSE (50kI)
FREQUENCY (kHz)
GAIN (dB)
10001001010.1
-20
-10
0
10
-30
0.01 10,000
MAX5392 toc26
VDD = 1.8V
VDD = 5V
VIN = 1VP-P
CW = 10pF
MIDSCALE FREQUENCY
RESPONSE (100kI)
FREQUENCY (kHz)
GAIN (dB)
10001001010.1
-20
-10
0
10
-30
0.01 10,000
MAX5392 toc27
VDD = 1.8V
VDD = 5V
VIN = 1VP-P
CW = 10pF
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
_______________________________________________________________________________________ 9
Pin Description
Pin Configuration
16
15
14
13
12
11
10
1
2
3
4
5
6
7
VDD
N.C.
SCL
SDAHB
LA
WA
HA
TOP VIEW
MAX5392 A0
A1
A2BYP
LB
98 GNDI.C.
WB
+
TSSOP
PIN NAME FUNCTION
1 HA Resistor A High Terminal. The voltage at HA can be higher or lower than the voltage at LA. Current
can flow into or out of HA.
2 WA Resistor A Wiper Terminal
3 LA Resistor A Low Terminal. The voltage at LA can be higher or lower than the voltage at HA. Current
can flow into or out of LA.
4 HB Resistor B High Terminal. The voltage at HB can be higher or lower than the voltage at LB. Current
can flow into or out of HB.
5 WB Resistor B Wiper Terminal
6 LB Resistor B Low Terminal. The voltage at LB can be higher or lower than the voltage at HB. Current
can flow into or out of LB.
7 BYP Internal Power-Supply Bypass. For additional charge-pump filtering, bypass to GND with a capaci-
tor close to the device.
8 I.C. Internally Connected. Connect to GND.
9 GND Ground
10 A2 Address Input 2. Connect to VDD or GND.
11 A1 Address Input 1. Connect to VDD or GND.
12 A0 Address Input 0. Connect to VDD or GND.
13 SDA I2C-Compatible Serial-Data Input/Output. A pullup resistor is required.
14 SCL I2C-Compatible Serial-Clock Input. A pullup resistor is required.
15 N.C. No Connection. Not internally connected.
16 VDD Power-Supply Input. Bypass VDD to GND with a 0.1FF capacitor close to the device.
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
10 _____________________________________________________________________________________
Detailed Description
The MAX5392 dual, 256-tap, volatile, low-voltage linear
taper digital potentiometer offers three end-to-end resis-
tance values of 10kI, 50kI, and 100kI. The potenti-
ometer consists of 255 fixed resistors in series between
terminals H_ and L_. The potentiometer wiper, W_, is
programmable to access any one of the 256 tap points
on the resistor string.
The potentiometers are programmable independently of
each other. The MAX5392 features an I2C interface.
Charge Pump
TThe MAX5392 contains an internal charge pump that
guarantees the maximum wiper resistance, RWL, to be
less than 200Ω for supply voltages down to 1.7V. Pins
H_, W_, and L_ are still required to be less than VDD +
0.3V. A bypass input, BYP, is provided to allow addi-
tional filtering of the charge-pump output, further reduc-
ing clock feedthrough that can occur on H_, W_, or L_.
The nominal clock rate of the charge pump is 600kHz.
BYP should remain resistively unloaded as any addi-
tional load would increase clock feedthrough. See the
Charge-Pump Feedthrough at W_ vs. CBYP graph in the
Typical Operating Characteristics for CBYP sizing guide-
lines with respect to clock feedthrough to the wiper. The
value of CBYP does affect the startup time of the charge
pump; however, CBYP does not impact the ability to
communicate with the device, nor is there a minimum
CBYP requirement. The maximum wiper impedance
specification is not guaranteed until the charge pump is
fully settled. See the BYP Ramp Time vs. CBYP graph in
the Typical Operating Characteristics for CBYP impact on
charge-pump settling time.
I2C Digital Interface
The I2C interface contains a shift register that decodes
the command and address bytes, routing the data to the
appropriate control registers. Data written to a control
register immediately updates the wiper position. The
wipers A and B power up in midposition, D[7:0] = 80h.
Serial Addressing
The MAX5392 operates as a slave device that receives
data through an I2C/SMBusK-compatible 2-wire serial
interface. The interface uses a serial-data access line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master(s) and slave(s).
A master, typically a microcontroller, initiates all data
transfers to the port and generates the SCL clock that
synchronizes the data transfer. See Figure 2. Connect a
pullup resistor, typically 4.7kI, between each of the SDA
and SCL lines to a voltage between VDD and 5.5V.
SMBus is a trademark of Intel Corp.
Figure 2. I2C Serial-Interface Timing Diagram
SDA
SCL
START
CONDITION
(S)
tLOW
tBUF
tHIGH
tHD:STA
tHD:STA
tSU:DAT
tRtF
tSU:STD
REPEATD
START CONDITION
(Sr)
ACKNOWLEDGE (A) STOP CONDITION
(P)
START CONDITION
(S)
tHD:DAT
tSU:DTA
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
______________________________________________________________________________________ 11
Figure 3. START and STOP Conditions
Figure 4. Slave Address
Figure 5. Bit Transfer
Each transmission consists of a START (S) condition sent
by a master, followed by a 7-bit slave address plus a
NOP/W bit. See Figures 3, 4, and 7.
START and STOP Conditions
SCL and SDA remain high when the interface is inactive.
A master controller signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. The master controller
issues a STOP condition by transitioning the SDA from
low to high while SCL is high, after finishing communi-
cating with the slave. The bus is then free for another
transmission. See Figure 2.
Bit Transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable while SCL is
high. See Figure 5.
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data. See
Figure 6. Each byte transferred requires a total of 9 bits.
The master controller generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line remains stable low during
the high period of the clock pulse.
P
STOP
CONDITION
S
START CONDITION
SDA
SCL
LSBMSB
START
SDA
SCL
0 1 0 1 A2 A1 A0 ACKNOP/W
SDA
SCL
DATA STABLE,
DATA VALID
CHANGE OF
DATA ALLOWED
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
12 _____________________________________________________________________________________
Slave Address
The MAX5392 includes a 7-bit slave address (Figure 4).
The 8th bit following the 7th bit of the slave address is the
NOP/W bit. Set the NOP/W bit low for a write command
and high for a no-operation command. The device does
not support readback.
The device provides three address inputs (A0, A1, and
A2), allowing up to eight devices to share a common
bus (Table 1). The first 4 bits (MSBs) of the factory-set
slave addresses are always 0101. A2, A1, and A0 set the
next 3 bits of the slave address. Connect each address
input to VDD or GND. Each device must have a unique
address to share a common bus.
Message Format for Writing
Write to the devices by transmitting the device’s slave
address with NOP/W (8th bit) set to zero, followed by
at least 2 bytes of information. The first byte of informa-
tion is the command byte. The second byte is the data
byte. The data byte goes into the internal register of the
device as selected by the command byte (Figure 7 and
Table 2).
Table 1. Slave Addresses
Figure 6. Acknowledge
Figure 7. Command and Single Data Byte Received
9821
START
CONDITION
SCL
SDA
CLOCK PULSE FOR
ACKNOWLEDGMENT
NOT ACKNOWLEDGE
ACKNOWLEDGE
ADDRESS INPUTS SLAVE ADDRESS
A2 A1 A0
GND GND GND 0101000
GND GND VDD 0101001
GND VDD GND 0101010
GND VDD VDD 0101011
VDD GND GND 0101100
VDD GND VDD 0101101
VDD VDD GND 0101110
VDD VDD VDD 0101111
S 0 A A A P
ACKNOWLEDGE
NOP/W
HOW CONTROL BYTE AND DATA
BYTE MAP INTO DEVICE REGISTERS
ACKNOWLEDGE
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ADDRESS COMMAND BYTE 1 DATA BYTE
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
______________________________________________________________________________________ 13
Command Byte
Use the command byte to select the destination of the
wiper data. See Table 2.
Command Descriptions
REG A: The data byte writes to register A and the wiper
of potentiometer A moves to the appropriate position.
D[7:0] indicates the position of the wiper. D[7:0] = 00h
moves the wiper to the position closest to LA. D[7:0] = FFh
moves the wiper closest to HA. D[7:0] is 80h following
power-on.
REG B: The data byte writes to register B and the wiper
of potentiometer B moves to the appropriate position.
D[7:0] indicates the position of the wiper. D[7:0] = 00h
moves the wiper to the position closest to LB. D[7:0] = FFh
moves the wiper to the position closest to HB. D[7:0] is
80h following power-on.
REG A and B: The data byte writes to registers A and
B and the wipers of potentiometers A and B move to
the appropriate position. D[7:0] indicates the position
of the wiper. D[7:0] = 00h moves the wipers to the posi-
tion closest to L_. D[7:0] = FFh moves the wipers to the
position closest to H_. D[7:0] is 80h following power-on.
Applications Information
Variable Gain Amplifier
Figure 8 shows a potentiometer adjusting the gain of a
noninverting amplifier. Figure 9 shows a potentiometer
adjusting the gain of an inverting amplifier.
Adjustable Dual Regulator
Figure 10 shows an adjustable dual linear regulator
using a dual potentiometer as two variable resistors.
Table 2. I2C Command Byte Summary
Figure 8. Variable Gain Noninverting Amplifier
Figure 9. Variable Gain Inverting Amplifier
Figure 10. Adjustable Dual Linear Regulator
ADDRESS BYTE COMMAND BYTE DATA BYTE
SCL
CYCLE
NUMBER
START (S)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
STOP (P)
A6 A5 A4 A3 A2 A1 A0 WACK
(A) R7 R6 R5 R4 R3 R2 R1 R0 ACK
(A) D7 D6 D5 D4 D3 D2 D1 D0 ACK
(A)
REG A 0 1 0 1 A2 A1 A0 0 0 0 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0
REG B 0 1 0 1 A2 A1 A0 0 0 0 0 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0
REG A AND B 0 1 0 1 A2 A1 A0 0 0 0 0 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0
VIN
VOUT
H
L
W
VIN
VOUT
HL
W
VOUT1
VOUT2
OUT1
OUT2
SET1
SET2
IN
V+
L
L
H
H
W
W
MAX8866
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
14 _____________________________________________________________________________________
Adjustable Voltage Reference
Figure 11 shows an adjustable voltage reference circuit
using a potentiometer as a voltage-divider.
Variable Gain Current to Voltage Converter
Figure 12 shows a variable gain current to voltage con-
verter using a potentiometer as a variable resistor.
LCD Bias Control
Figure 13 shows a positive LCD bias control circuit using
a potentiometer as a voltage-divider.
Figure 14 shows a positive LCD bias control circuit using
a potentiometer as a variable resistor.
Programmable Filter
Figure 15 shows a programmable filter using a dual
potentiometer.
Offset Voltage Adjustment Circuit
Figure 16 shows an offset voltage adjustment circuit
using a dual potentiometer.
Figure 11. Adjustable Voltage Reference
Figure 12. Variable Gain I-to-V Converter
Figure 13. Positive LCD Bias Control Using a Voltage Divider
Figure 14. Positive LCD Bias Control Using a Variable Resistor
Chip Information
PROCESS: BiCMOS
OUT
IN
+2.5V
VREF
GND L
H
W
MAX6037
L
R1 R2
R3
VOUT
IS
H
W
VOUT = -IS x ((R3 x (1 + R2/R1)) + R2)
L
VOUT
H
W
1.8V
L
VOUT
H
W
1.8V
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
______________________________________________________________________________________ 15
Figure 15. Programmable Filter Figure 16. Offset Voltage Adjustment Circuit
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
16 TSSOP U16+2 21-0066 90-0117
VOUT
VIN
LA
HA
WB
LB
HB
R2
R1
R3
WA
VOUT
LB
HB
WB
WA
LA
HA
1.8V
Dual, 256-Tap, Volatile, Low-Voltage,
Linear Taper Digital Potentiometer
MAX5392
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/10 Initial release —
1 4/10
Added Soldering Temperature in Absolute Maximum Ratings; corrected
code in Conditions of -3dB Bandwidth specification in Electrical
Characteristics
2, 3
2 11/10 Changed Electrical Characteristics heading and corrected Figures 9, 12,
14, 15, 16 2, 3, 4, 13, 14, 15
