IDT74AUC16373PFI - Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

IDT74AUC16373

1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

1FEBRUARY 2003

IDT74AUC16373

INDUSTRIAL TEMPERATURE RANGE

1.8V CMOS 16-BIT TRANSPARENT

D-TYPE LATCH WITH

3-STATE OUTPUTS

DESCRIPTION:

This 16-bit transparent D-type latch is built using advanced CMOS technol-

ogy. The device can be used as a single 16-bit latch or as two 8-bit latches. When

the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When

LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output enable (OE) input can be used to place the eight outputs

in either a normal logic state (high or low logic levels) or a high-impedance state.

In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The OE input does not affect the internal operation of the latch.

This device is fully specified for partial power-down applications using IOFF.

The IOFF circuitry disables the outputs, preventing damaging current backflow

through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE

should be tied to VDD through a pull-up resistor; the minimum value of the resistor

is determined by the current-sinking capability of the driver.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• 1.8V Optimized

• 0.8V to 2.7V Operating Range

• Inputs/outputs tolerant up to 3.6V

• Output drivers: ±9mA @ 2.3V

• Supports hot insertion

• Available in TSSOP, TVSOP, and VFBGA packages

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS:

• high performance, low voltage communications systems

• high performance, low voltage computing systems

1Q1

1LE

1D1

1OE

TO SEVEN O THER CHANNELS

2Q1

2LE

2D1

2OE

TO SEVEN OTHER CHANNELS

INDUSTRIAL TEMPERATURE RANGE

IDT74AUC16373

1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

PINOUT CONFIGURATION

ABCDEFGHJK

1LE

1OE

1D2

1D1

GND

1Q1 1Q3 1Q7 2Q2 2Q4 2Q6 2Q81Q5

1D4

1D3

VDD

1D8

1D7

2D1

2D2

2D3

2D4

GND

2D5

2D6

VDD

2D7

2D8

GND

2LE

2OE

1D6

1D5

GND

11Q2 1Q4 1Q8 2Q1 2Q3 2Q5 2Q71Q6

56 BALL VFBGA P ACKAGE LAYOUT

VFBGA

TOP VIEW

NOTE:

NC = No Internal Connection

INDUSTRIAL TEMPERATURE RANGE

IDT74AUC16373

1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

TSSOP/ TVSOP

TOP VIEW

PIN CONFIGURATION Symbol Description Max Unit

VTERM Terminal Voltage with Respect to GND –0.5 to +3.6 V

(all input and VDD terminals)

VTERM Terminal Voltage with Respect to GND –0.5 to +3.6 V

(any I/O or Output terminals in high-

impedance or power-off state)

TSTG Storage Temperature –65 to +150 °C

IOUT Continuous DC Output Current ±20 mA

IIK Continuous Clamp Current, ±50 mA

VI < 0, or VI > VDD

IOK Continuous Clamp Current, VO < 0 –50 mA

IDD Continuous Current through ±100 mA

ISS each VDD or GND

ABSOLUTE MAXIMUM RA TINGS(1)(1)

(1)(1)

(1)

NOTE:

1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

FUNCTION TABLE (EACH 8-BIT LATCH)(1)

NOTES:

1 . H = HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

Z = High-Impedance

2. Level of Q before the indicated steady-state conditions were established.

Inputs Output

xOE xLE xDx xQx

LHH H

LHL L

LLX Q

(2)

HXX Z

PIN DESCRIPTION

Pin Names Description

xDx Data Inputs

xLE Latch Enable Inputs

xQx 3-State Outputs

xOE 3-State Output Enable Inputs (Active LOW)

1OE

1Q1

1Q2

GND

1Q3

1Q4

VDD

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

2Q4

2OE

GND

VDD

2Q5

2Q6

GND

2Q7

11LE

1D1

1D2

GND

1D3

1D4

VDD

1D5

1D6

1D7

1D8

2D1

GND

2D3

2D4

2D5

2D6

GND

2D7

2D8

2LE

2Q3

2Q8

VDD

2D2

GND

Symbol Parameter Conditions Typ. Max. Unit

CIN(1) Input Capacitance VIN = 0V 3 4 pF

COUT(2) Output Capacitance VOUT = 0 V 5.5 6.5 pF

CI(3) Input Port Capacitance VIN = 0V 3 4 pF

CAPACITANCE (TA = +25°C, f = 1.0MHz, VDD = 2.5V)

NOTES:

1. Applies to Control Inputs.

2. Applies to Data Outputs.

3 . Applies to Data Inputs.

INDUSTRIAL TEMPERATURE RANGE

IDT74AUC16373

1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

Symbol Parameter Test Conditions Min. Max. Unit

VDD Supply Voltage 0.8 2.7 V

VDD = 0.8V VDD —

VDD = 1.1V to 1.3V 0.65 x VDD —

VIH Input HIGH Voltage Level VDD = 1.4V to 1.6V 0.65 x VDD —V

VDD = 1.65V to 1.95V 0.65 x VDD —

VDD = 2.3V to 2.7V 1 . 7 —

VDD = 0.8V — 0

VDD = 1.1V to 1.3V — 0.35 x VDD

VIL Input LOW Voltage Level VDD = 1.4V to 1.6V — 0.35 x VDD V

VDD = 1.65V to 1.95V — 0.35 x VDD

VDD = 2.3V to 2.7V — 0 . 7

VIInput Voltage 0 2.7 V

VOOutput Voltage Active State 0 VDD V

3-State 0 2.7

VDD = 0.8V — –0.7

VDD = 1.1V — –3

IOH HIGH Level Output Current VDD = 1.4V — –5 mA

VDD = 1.65V — –8

VDD = 2.3V — –9

VDD = 0.8V — 0 .7

VDD = 1.1V — 3

IOL LOW Level Output Current VDD = 1.4V — 5 mA

VDD = 1.65V — 8

VDD = 2.3V — 9

∆t/∆v Input Transition Rise or Fall Time — 20 ns/V

TAOperating Free-Air Temperature –40 +85 °C

RECOMMENDED OPERATING CHARACTERISTICS(1)

NOTE:

1. All unused inputs of the device must be held at VDD or GND to ensure proper operation.

Symbol Parameter Test Conditions Min. Typ. Max. Unit

IIH Input HIGH or LOW Current VDD = 2.7V, VI = VDD or GND — — ±5 µ A

IIL All Inputs

IOFF Input/Output Power Off Leakage VDD = 0V, VIN or VO ≤ 2.7V — — ± 10 µA

IOZH High Impedance Output Current VDD = 2.7V VO = VDD — — ±10 µA

IOZL (3-State Output Pins) VO = GND — — ±10

IDDL Quiescent Power Supply Current VDD = 0.8V to 2.7V — — 20 µA

IDDH VIN = GND or VDD

IDDZ

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1)

Following Conditions Apply Unless Otherwise Specified:

Operating Conditions: TA = –40°C to +85°C

NOTE:

1. All unused inputs of the device must be held at VDD or GND to ensure proper operation.

INDUSTRIAL TEMPERATURE RANGE

IDT74AUC16373

1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

Symbol Parameter Test Conditions(1) Min. Typ. Max. Unit

VOH Output HIGH Voltage VDD = 0.8V - 2.7V IOH = –100µAVDD - 0.1 — —

VDD = 0.8V IOH = –0.7mA — 0.55 —

VDD = 1.1V(2) IOH = –3mA 0 .8 — — V

VDD = 1.4V(3) IOH = –5mA 1 — —

VDD = 1.65V(4) IOH = –8mA 1 .2 — —

VDD = 2.3V(5) IOH = –9mA 1 .8 — —

VOL Output LOW Voltage VDD = 0.8V - 2.7V IOH = 100µA — — 0.2

VDD = 0.8V IOL = 0.7mA — 0.25 —

VDD = 1.1V(2) IOL = 3mA — — 0.3 V

VDD = 1.4V(3) IOL = 5mA — — 0.4

VDD = 1.65V(4) IOL = 8 mA — — 0.45

VDD = 2.3V(5) IOH = 9mA — — 0.6

OUTPUT DRIVE CHARACTERISTICS

NOTES:

1. VIL and VIH must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS table for the appropriate VDD range. TA = -40°C to +85°C.

2. Demonstrates operation for nominal VDD = 1.2V.

3. Demonstrates operation for nominal VDD = 1.5V.

4. Demonstrates operation for nominal VDD = 1.8V.

5. Demonstrates operation for nominal VDD = 2.5V.

SWITCHING CHARACTERISTICS(1)

NOTE:

1. See TEST CIRCUITS AND WAVEFORMS. TA = -40°C to +85°C.

VDD = 0.8V VDD = 1.2V±0.1V VDD = 1.5V±0.1V VDD = 1.8V±0.15V VDD = 2.5V±0.2V

Symbol Parameter Typ. Min. Max. Min. Max. Min. Typ. Max. Min. Max. Unit

tPLH Propagation Delay xDx to xQx 8 1.1 3.8 0.6 2.4 0.7 1.5 2.4 0.6 1.9 ns

tPHL xLE to xQx 10.6 1.4 4.9 0.7 3.2 0.7 1.6 2.8 0.6 2.1

tPZH Output Enable Time 9 1.3 4.5 0.6 2.9 0.8 1.7 2.9 0.7 2.2 ns

tPZL xOE to xQx

tPHZ Output Disable Time 13 2.4 7 2.4 4.8 1.1 2.7 4.6 0.4 2.5 ns

tPLZ xOE to xQx

tSU Set-up Time, Data before LE↓1.7 0.7 — 0.5 — 0.4 — — 0.4 — ns

tHHold Time, Data after LE↓— 1.2 — 0.8 — 0.7 — — 0.6 — ns

tWPulse Duration, LE HIGH 4. 2 2 .9 — 2.3 — 2.1 — — 1 .7 — ns

OPERATING CHARACTERISTICS, TA = 25°C

Symbol Parameter Test Conditions VDD = 0.8V VDD = 1.2V VDD = 1.5V VDD = 1.8V VDD = 2.5V Unit

CPD Power Dissipation Capacitance CL = 0pF 21 22 23 25 29 pF

Outputs Enabled f = 10MHz

CPD Power Dissipation Capacitance 5 5 6 7 10 pF

Outputs Disabled

INDUSTRIAL TEMPERATURE RANGE

IDT74AUC16373

1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

Open

VLOAD

GND

VDD

Pulse

Generator D.U.T.

VIN VOUT

(1)

SAME PHASE

INPUT TRANSITION

OPPOSITE PHASE

INPUT TRANSITION

VOH

VOL

tPLH tPHL

tPHL

tPLH

OUTPUT

VDD

CONTROL

INPUT tPLZ 0V

OUTPUT

NORMALLY

LOW tPZH

SWITCH

CLOSED

OUTPUT

NORMALLY

HIGH

ENABLE DISABLE

SWITCH

OPEN

tPHZ

VOL + VLZ

VOH

tPZL

VLOAD/2 VLOAD/2

VDD

VOL

VOH - VHZ

TIMING

INPUT

DATA

INPUT

tSU tH

VDD

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

VDD

TEST CIRCUITS AND WAVEFORMS

Propagation Delay

Test Circuits for All Outputs

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTE:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; Slew Rate ≥ 1V/ns.

Test Switch

Open Drain

Disable Low VLOAD

Enable Low

Disable High GND

Enable High

All Other Tests Open

SWITCH POSITION

Setup and Hold Times

TEST CONDITIONS(1)

Symbol VDD = 0.8V VDD = 1.2V±0.1V VDD = 1.5V±0.1V VDD = 1.8V±0.15V VDD = 2.5V±0.2V Unit

VLOAD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD V

VTVDD/2 VDD/2 VDD/2 VDD/2 VDD/2 V

VLZ 100 100 100 150 150 mV

VHZ 100 100 100 150 150 mV

RL2 2 2 1 0.5 KΩ

CL15 15 15 30 30 pF

Pulse Width

INDUSTRIAL TEMPERATURE RANGE

IDT74AUC16373

1.8V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

ORDERING INFORMATION

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459

www.idt.com

IDT XX AUC XXX XX

Package

Device Type

Temp. R ange

Very Fine Pitch Ball Gr id Array

Thin Shrink Small Outline Package

Thin Very Small O utlin e Pa ckage

16-Bit Trans pare nt D- Type Latch

with 3-State Outputs

– 40°C to +85°C

Family

373

Double-Density

Bus- Hold

Blank No bus-hold

Temp.

IIndustrial Temperature Range