DS1486P-120+ - Maxim Integrated Products, Inc.

1 of 14 REV: 012505

FEATURES

§ 128 kbytes of User NV RAM

§ Integrated NV SRAM, Real-Time Clock,

Crystal, Power-Fail Control Circuit and

Lithium Energy Source

§ Totally Nonvolatile with Over 10 years of

Operation in the Absence of Power

§ Watchdog Timer Restarts an Out-of-Control

Processor

§ Alarm Function Schedules Real-Time-Related

Activities such as System Wakeup

§ Programmable Interrupts and Square-Wave

Output

§ All Registers are Individually Addressable

Through the Address and Data Bus

§ Interrupt Signals Active in Power-Down

Mode

PIN CONFIGURATIONS

ORDERING INFORMATION

PART TEMP

RANGE

PIN-

PACKAGE

TOP

MARK**

DS1486-120 0°C to

+70°C 32 EDIP (0.740”) DS1486-120

DS1486-120+ 0°C to

+70°C 32 EDIP (0.740”) DS1486-120

DS1486P-120 0°C to

+70°C 34 PowerCap®* DS1486P-

120

DS1486P-120+ 0°C to

+70°C 34 PowerCap* DS1486P-

120

DS9034PCX 0°C to

+70°C PowerCap DS9034PC

DS9034PCX+ 0°C to

+70°C PowerCap DS9034PC

*DS9034PCX PowerCap required (must be ordered separately).

**A ‘+’ indicates lead-free. The top mark will include a ‘+’ symbol

on lead-free devices.

PowerCap is a registered trademark of Dallas Semiconductor.

DS1486/DS1486P

RAMified Watchdog Timekeepers

www.maxim-ic.com

INT

(

INTB

)

128k x 8

32-Pin Encapsulated Package

(32 PIN 740)

A14

DQ1

DQ0

VCC

DQ7

DQ5

DQ6

A16

A12

DQ2

GND

DQ4

DQ3

DS1486

INT

(

INTB

)

A15

A16

VCC

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

SQW

X1 GND VBAT X2

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

DS1486P

TOP VIEW

DS1486/DS1486P

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PIN DESCRIPTION

PDIP PowerCap NAME FUNCTION

1 1

INTB (INTB) Active-Low Interrupt B, Output, Push-Pull

2 3 A16

3 32 A14

4 30 A12

5 25 A7

6 24 A6

7 23 A5

8 22 A4

9 21 A3

10 20 A2

11 19 A1

12 18 A0

23 28 A10

25 29 A11

26 27 A9

27 26 A8

28 31 A13

31 2 A15

Address Input

13 16 DQ0

14 15 DQ1

15 14 DQ2

17 13 DQ3

18 12 DQ4

19 11 DQ5

20 10 DQ6

21 9 DQ7

Data Input/Output

16 17 GND Ground

22 8 CE Active-Low Chip Enable

24 7 OE Active-Low Output Enable

29 6 WE Active-Low Write Enable

30 — INTA/SQW

Active-Low, Interrupt A, Open-Drain Output and Square-Wave

Output, Shared. Note: Both functions must not be enabled at the same

time, or a conflict could occur.

32 5 VCC Power-Supply Input

— 4 PFO Active-Low Power-Fail Output, Open Drain. Requires a pullup

resistor for proper operation.

— 33 SQW Square-Wave Output

— 34 INTA Active-Low Interrupt A, Output, Open Drain. Requires a pullup

resistor for proper operation.

— X1, X2, VBAT Crystal Connections and Battery Connection

DS1486/DS1486P

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DESCRIPTION

The DS1486 is a nonvolatile static RAM with a full-function real-time clock (RTC), alarm, watchdog

timer, and interval timer, which are all accessible in a byte-wide format. The DS1486 contains a lithium

energy source and a quartz crystal, which eliminate the need for any external circuitry. Data contained

within 128K by 8-bit memory and the timekeeping registers can be read or written in the same manner as

byte-wide static RAM. The timekeeping registers are located in the first 14 bytes of memory space. Data

is maintained in the RAMified timekeeper by intelligent control circuitry, which detects the status of VCC

and write-protects memory when VCC is out of tolerance. The lithium energy source can maintain data and

real time for over 10 years in the absence of VCC. Timekeeper information includes hundredths of

seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is

automatically adjusted for months with fewer than 31 days, including correction for leap year. The

RAMified timekeeper operates in either 24-hour or 12-hour format with an AM/PM indicator. The

watchdog timer provides alarm interrupts and interval timing between 0.01 seconds and 99.99 seconds.

The real time alarm provides for preset times of up to one week. Interrupts for both watchdog and RTC

will operate when the system is powered down. Either can provide system “wake-up” signals.

PACKAGES

The DS1486 is available in two packages: a 32-pin DIP module and 34-pin PowerCap module. The 32-

pin DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The 32-

pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap

(DS90934PCX) that contains the crystal and battery. The design allows the PowerCap to be mounted on

top of the DS1486P after the completion of the surface mount process. Mounting the PowerCap after the

surface mount process prevents damage to the crystal and battery due to high temperatures required for

solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and

PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap

is DS9034PCX.

Table 1. Truth Table

VCC CE OE WE MODE DQ POWER

VIH X X Deselect High-Z Standby

X X X Deselect High-Z Standby

VIL X VIL Write Data In Active

VIL V

IL V

IH Read Data Out Active

5V ±10%

VIL V

IH V

IH Read High-Z Active

<4.5V > VBAT X X X Deselect High-Z CMOS Standby

<VBAT X X X Deselect High-Z Data Retention Mode

OPERATION—READ REGISTERS

The DS1486 executes a read cycle whenever WE (Write Enable) is inactive (High), CE (Chip Enable)

and OE (Output Enable) are active (Low). The unique address specified by the address inputs (A0–A16)

defines which of the registers is to be accessed. Valid data will be available to the eight data output

drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE

access times are also satisfied. If OE and CE access times are not satisfied, then data access must be

measured from the latter occurring signal (CE or OE) and the limiting parameter is either tCO for CE or

tOE for OE rather than address access.

DS1486/DS1486P

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OPERATION—WRITE REGISTERS

The DS1486 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in

the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE

will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE

or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state

for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data

bus with sufficient Data Set-Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of

CE or WE. The OE control signal should be kept inactive (High) during write cycles to avoid bus

contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the

outputs in tODW from its falling edge.

DATA RETENTION

The RAMified Timekeeper provides full functional capability when VCC is greater than 4.5V. When VCC

falls below the power fail trip-point (VTP), the internal CE signal is forced high, blocking access (Write-

Protect). While in the data retention mode, all inputs are “don’t cares,” SQW and DQ0–DQ7 go to a high-

impedance state. The two interrupts INTA and INTB (INTB) and the internal clock and timers continue

to run regardless of the level of VCC. However, it is important to insure that the pull-up resistors used with

the interrupt pins are never pulled up to a value that is greater than VCC + 0.3V. As VCC falls below

approximately 3.0V, a power switching circuit turns the internal lithium energy source on to maintain the

clock and timer data functionality. It is also required to ensure that during this time (battery-backup

mode), that the voltage present at INTA and INTB (INTB) never exceeds VBAT. During power-up, when

VCC rises above VBAT, the power-switching circuit connects external VCC and disconnects the internal

lithium energy source. Normal operation can resume after VCC exceeds 4.5V for a period of 200ms.

RAMIFIED TIMEKEEPER REGISTERS

The RAMified timekeeper has 14 registers that are 8 bits wide that contain all the timekeeping, alarm,

watchdog, and control information. The clock, calendar, alarm, and watchdog registers are memory

locations that contain external (user-accessible) and internal copies of the data. The external copies are

independent of internal functions, except that they are updated periodically by the simultaneous transfer

of the incremented internal copy (see Figure 1). The Command Register bits are affected by both internal

and external functions. This register will be discussed later. Registers 0, 1, 2, 4, 6, 8, 9, and A contain

time-of-day and date information (see Figure 2). Time-of-day information is stored in BCD. Registers 3,

5, and 7 contain the Time-of-Day Alarm information. Time-of-Day Alarm information is stored in BCD.

Watchdog Alarm Registers and information that is stored in these two registers is in BCD. Registers E

through 1FFFF are user bytes and can be used to maintain data at the user’s discretion.

CLOCK ACCURACY (DIP MODULE)

The DS1486 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C.

CLOCK ACCURACY (PowerCap MODULE)

The DS1486P and DS9034PCX are each individually tested for accuracy. Once mounted together, the

module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C.

DS1486/DS1486P

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Figure 1. Block Diagram

DS1486/DS1486P

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TIME-OF-DAY REGISTERS

Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time-of-Day data in BCD. Ten bits within these eight registers

are not used and will always read 0 regardless of how they are written. Bits 6 and 7 in the Months

bit is set to logic 1 as shipped from Dallas Semiconductor to prevent lithium energy consumption during

storage and shipment (DIP Module only). This bit will normally be turned on by the user during device

initialization. However, the oscillator can be turned on and off as necessary by setting this bit to the

appropriate level. The INTA and Square Wave Output signals are tied together at pin 30 on the 32-pin

DIP module. With this package, ESQW (Bit 6) of the Months Register (9) controls the function of this

pin. When set to logic 0, the pin will output a 1024 Hz square wave signal. When set to logic 1, the pin is

available for interrupt A output (INTA) only. The INTA and Square Wave Output signals are separated

on the 34-pin PowerCap module. With this package, ESQW controls only the Square Wave Output (pin

33). When set to logic 0, pin 33 will output a 1024 Hz square wave signal. When set to logic 1, pin 33 is

in a high impedance state. Pin 34 (INTA) is not affected by the setting of bit 6. Bit 6 of the Hours register

is defined as the 12- or 24-hour select bit. When set to logic 1, the 12-hour format is selected. In the 12-

hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-

hour bit (20-23 hours). The Time-of-Day registers are updated every 0.01 seconds from the real-time

clock, except when the TE bit (bit 7 of Register B) is set low or the clock oscillator is not running. The

preferred method of synchronizing data access to and from the RAMified Timekeeper is to access the

Command register by doing a write cycle to address location B and setting the TE bit (Transfer Enable

bit) to a logic 0. This will freeze the External Time-of-Day registers at the present recorded time,

allowing access to occur without danger of simultaneous update. When the watch registers have been read

or written, a second write cycle to location B setting the TE bit to a logic 1 will put the Time-of-Day

Registers back to being updated every 0.01 second. No time is lost in the real-time clock because the

internal copy of the Time-of-Day register buffers is continually incremented while the external memory

registers are frozen. An alternate method of reading and writing the Time-of-Day registers is to ignore

synchronization. However, any single reading may give erroneous data as the real-time clock may be in

the process of updating the external memory registers as data is being read. The internal copies of seconds

through years are incremented and the Time-of-Day Alarm is checked during the period that hundreds of

seconds reads 99. The copies are transferred to the external register when hundredths of seconds roll from

99 to 00. A way of making sure data is valid is to do multiple reads and compare. Writing the registers

can also produce erroneous results for the same reasons. A way of making sure that the write cycle has

caused a proper update is to perform read verifies and re-execute the write cycle if data is not correct.

While the possibility of erroneous results from read and write cycles has been stated, it is worth noting

that the probability of an incorrect result is kept to a minimum due to the redundant structure of the

RAMified Timekeeper.

TIME-OF-DAY ALARM REGISTERS

Registers 3, 5, and 7 contain the Time-of-Day Alarm Registers. Bits 3, 4, 5, and 6 of Register 7 will

always read 0 regardless of how they are written. Bit 7 of Registers 3, 5, and 7 are mask bits (Figure 3).

When all of the mask bits are logic 0, a Time-of-Day Alarm will only occur when Registers 2, 4, and 6

match the values stored in Registers 3, 5, and 7. An alarm will be generated every day when bit 7 of

is set to a logic 1. When bit 7 of Registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute

when Register 1 (seconds) rolls from 59 to 00.

Time-of-Day Alarm Registers are written and read in the same format as the Time-of-Day Registers. The

Time-of-Day Alarm Flag and Interrupt are always cleared when Alarm Registers are read or written.

DS1486/DS1486P

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WATCHDOG ALARM REGISTERS

Registers C and D contain the time for the Watchdog Alarm. The two registers contain a time count from

00.01 to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be written or

read in any order. Any access to Register C or D will cause the Watchdog Alarm to reinitialize and clears

the Watchdog Flag bit and the Watchdog Interrupt Output. When a new value is entered or the Watchdog

Registers are read, the Watchdog Timer will start counting down from the entered value to 0. When 0 is

reached, the Watchdog Interrupt Output will go to the active state. The Watchdog Timer Countdown is

interrupted and reinitialized back to the entered value every time either of the registers is accessed. In this

manner, controlled periodic accesses to the Watchdog Timer can prevent the Watchdog Alarm from

going to an active level. If access does not occur, countdown alarm will be repetitive. The Watchdog

Alarm Registers always read the entered value. The actual countdown register is internal and is not

readable. Writing registers C and D to 0 will disable the Watchdog Alarm feature.

DS1486/DS1486P

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Figure 2. RAMified Timekeeper Registers

Figure 3. Time-of-Day Alarm Mask Bits

(3) MINUTES (5) HOURS (7) DAYS ALARM RATE

1 1 1 Alarm once per minute

0 1 1 Alarm when minutes match

0 0 1 Alarm when hours and minutes match

0 0 0 Alarm when hours, minutes, and days match

Note: Any other bit combinations of mask bit settings produce illogical operation.

DS1486/DS1486P

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COMMAND REGISTER (0Bh)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TE IPSW IBH/LO PU/LVL WAM TDM WAF TDF

Bit 7: Transfer Enable (TE). This bit when set to a logic 0 will disable the transfer of data between

internal and external clock registers. The contents in the external clock registers are now frozen and reads

or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.

Bit 6: Interrupt Switch (IPSW). When set to a logic 1, INTA is the Time-of-Day Alarm and INTB

(INTB) is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the

Watchdog Alarm output and INTB (INTB) is the Time-of-Day Alarm output. The INTA/SQW output pin

shares both the interrupt A and square-wave output function. INTA and the square wave function should

never be simultaneously enabled or a conflict may occur (32-pin DIP module only).

Bit 5: Interrupt B Sink or Source Current (IBH/LO). When this bit is set to a logic 1 and VCC is

applied, INTB (INTB) will source current (see DC characteristics IOH). When this bit is set to a logic 0,

INTB will sink current (see IOL in the DC Characteristics).

Bit 4: Interrupt Pulse Mode or Level Mode (PU/LVL). This bit determines whether both interrupts

will output a pulse or level signal. When set to a logic 0, INTA and INTB (INTB) will be in the level

mode. When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a

minimum of 3ms and then release. INTB (INTB) will either sink or source current, depending on the

condition of Bit 5, for a minimum of 3ms and then release. INTB will only source current when there is a

voltage present on VCC.

Bit 3: Watchdog Alarm Mask (WAM). When this bit is set to a logic 0, the Watchdog Interrupt output

will be activated. The activated state is determined by bits 1, 4, 5, and 6 of the Command Register. When

this bit is set to a logic 1, the Watchdog interrupt output is deactivated.

Bit 2: Time-of-Day Alarm Mask (TDM). When this bit is set to a logic 0, the Time-of-Day Alarm

Interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the Command

Bit 1: Watchdog Alarm Flag (WAF). This bit is set to a logic 1 when a watchdog alarm interrupt

occurs. This bit is read only. The bit is reset when any of the Watchdog Alarm registers are accessed.

When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only

during the time the interrupt is active.

Bit 0: Time-of-Day Flag (TDF). This is a read-only bit. This bit is set to a logic 1 when a Time-of-Day

alarm has occurred. The time the alarm occurred can be determined by reading the Time-of-Day Alarm

registers. This bit is reset to a logic 0 state when any of the Time-of-Day Alarm registers are accessed.

When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only

during the time the interrupt is active.

DS1486/DS1486P

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground…………….……………………………….-0.3V to +6.0V

Operating Temperature Range (Noncondensing)….………………………………………….0°C to +70°C

Storage Temperature Range…………………………….…………………………………..-40°C to +85°C

Soldering Temperature (EDIP) (leads, 10 seconds)…………………...…+260°C for 10 seconds (Note 14)

Soldering Temperature……………………………….See IPC/JEDEC J-STD-020 Specification (Note 14)

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of

time may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0°C to +70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Power-Supply Voltage VCC 4.5 5.0 5.5 V 10

Input Logic 1 VIH 2.2

VCC +

0.3 V 10

Input Logic 0 VIL -0.3 +0.8 V 10

DC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = 0°C to +70°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current IIL -1.0 +1.0

Output Leakage Current ILO -1.0 +1.0

I/O Leakage Current ILIO -1.0 +1.0

Output Current at 2.4V IOH -1.0 mA 13

Output Current at 0.4V IOL 2.1 mA 13

Standby Current CE = 2.2V ICCS1 3.0 7.0 mA

Standby Current CE = VCC -0.5 ICCS2 4.0 mA

Active Current ICC 85 mA

Write Protection Voltage VTP 4.0 4.25 4.5 V

CAPACITANCE

(TA = +25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance CIN 7 15 pF

Output Capacitance COUT 7 15 pF

Input/Output Capacitance CI/O 7 15 pF

DS1486/DS1486P

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AC ELECTRICAL CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0°C to +70°C.)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Read Cycle Time tRC 120 ns 1

Address Access Time tACC 120 ns

CE Access Time tCO 120 ns

OE Access Time tOE 100 ns

OE or CE to Output Active tCOE 10 ns

Output High-Z from Deselect tOD 40 ns

Output Hold from Address Change tOH 10 ns

Write Cycle Time tWC 120 ns

Write Pulse Width tWP 110 ns 3

Address Setup Time tAW 0 ns

Write Recovery Time tWR 10 ns

Output High-Z from WE tODW 40 ns

Output Active from WE tOEW 10 ns 4

Data Setup Time tDS 85 ns 4

Data Hold Time tDH 10 ns 4, 5

INTA, INTB Pulse Width tIPW 3 ms 11, 12

READ CYCLE (Note 1)

DS1486/DS1486P

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WRITE CYCLE 1 (Notes 2, 6, 7)

WRITE CYCLE 2 (Notes 2, 8)

TIMING DIAGRAM: INTERRUPT OUTPUTS PULSE MODE (Notes 11, 12)

DS1486/DS1486P

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POWER-UP/POWER-DOWN TIMING

(TA = 0°C to +70°C)

PARAMETER SYMBOL MIN MAX UNITS NOTES

CE High to Power-Fail tPF 0 ns

Recovery at Power-Up tREC 200 ms

VCC Slew Rate

Power-Down

4.0 £ VCC £ 4.5V 300 ms

VCC Slew Rate

Power-Down

tFB

3.0 £ VCC £ 4.25V 10 ms

VCC Slew Rate Power-Up tR

4.5V ³ VCC ³ 4.0V 0

Expected Data Retention tDR 10 years 9

POWER-DOWN/POWER-UP TIMING

WARNING:

Under no circumstances are negative undershoots, of any amplitude, allowed when device is in

battery-backup mode.

DS1486/DS1486P

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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

NOTES:

1) WE is high for a read cycle.

2) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.

3) tWP is specified as the logical AND of the CE and WE. tWP is measured from the latter of CE or WE

going low to the earlier of CE or WE going high.

4) tDS or tDH are measured from the earlier of CE or WE going high.

5) tDH is measured from WE going high. If CE is used to terminate the write cycle, then tDH = 20ns.

6) If the CE low transition occurs simultaneously with or later than the WE low transition in write cycle

1, the output buffers remain in a high-impedance state during this period.

7) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

buffers remain in a high impedance state during this period.

8) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,

the output buffers remain in a high-impedance state during this period.

9) Each DS1486 is marked with a four-digit date code AABB. AA designates the year of manufacture.

BB designates the week of manufacture. The expected tDR is defined for DIP Modules as starting at

the date of manufacture.

10) All voltages are referenced to ground.

11) Applies to both interrupt pins when the alarms are set to pulse.

12) Interrupt output occurs within 100ns on the alarm condition existing.

13) Both INTA and INTB (INTB) are open-drain outputs.

14) Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering

techniques as long as temperature exposure to the lithium energy source contained within does not

exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that

ultrasonic vibration is not used. See the PowerCap package drawing for details regarding the

PowerCap package.

AC TEST CONDITIONS

Output Load: 50pF + 1TTL Gate

Input Pulse Levels: 0 to 3.0V

Timing Measurement Reference Levels

Input: 1.5V

Output: 1.5V

Input Pulse Rise and Fall Times: 5ns

PACKAGE INFORMATION

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.

28-pin 740 EDIP Module Document number: 56-G0002-001

32-pin PowerCap Module Document number: 56-G0003-001