CY7C09269/79/89 PREUIMINSRY CY7C09369/79/89 16K/32K/64K x16/18 Synchronous Dual Port Static RAM Low operating power Active= 195 mA (typical) Features * True Dual-Ported memory cells which allow simulta- neous access of the same memory location Standby= 0.05 mA (typical) * 6 Flow-Through/Pipelined devices + Fully synchronous interface for easier operation 16K x 16/18 organization (CY7C09269/369) + Burst counters increment addresses internally 32K x 16/18 organization (CY7C09279/379) Shorten cycle times 64K x 16/18 organization (C7C09289/389) Minimize bus noise * 3 Modes Supported in Flow-Through and Pipelined modes Flow-Through + Dual Chip Enables for easy depth expansion Pipelined + Upper and Lower Byte Controls for Bus Matching + Automatic power-down Burst oo. + Commercial and Industrial temperature ranges + Pipelined output mode on both ports allows fast ~ Available in 100-pin TQFP 100-MHz cycle time * 0.35-micron CMOS for optimum speed/power * High-speed clock to data access 6.5/7.5/9/12 ns (max.) + Pin-compatible and functionally equivalent to IDT709269, IDT70927, and IDT709279 Logic Block Diagram RAW, RW UB, UBa CE CEgr CEy, CEiR [B, [Ba OE, OER FT/Pipe, FT/Pipe, (1] [1] VOst-VO1stz77 AaVO1s7R ie) Control vO Control 8/9 8/9 [2] [2] Oo _VOz a VOgpVOs aR 13] 14/1516 145/46 3] Agi Arana Counter! Counter/ 13/1 4/15R ounter, ounter CLK, Address True Dual-Ported Address CLKR ADS, Register RAM Array Register ADSR CNTEN: Decode Decode CNTEN, CNTRST, CNTRSTp Notes: 1. VO,-1/O,, for x16 devices; 1/O9-I/0,, for x18 devices. 2. Oe 1/05 for x16 devices. lO _-l/O, for x18 devices. 3. Ag-Aqy for 16K; Ap-A,, for 32K; Ap-Ays for 64K devices. For the most recent information, visit the Cypress web site af www.cypress.com Cypress Semiconductor Corporation + 3901 North First Street + SanJose CA95134 + 408-943-2600 November 23, 1998FRSECUMINARY CY7C09269/79/89 CY7C09369/79/89 Functional Description The CY7C09269/79/89 and CY/CO9369/79/89 are high speed synchronous CMOS 16K, 32K, and 64K x 16/18 du- al-port static RAMs. Two ports are provided, permitting inde- pendent, simultaneous access for reads and writes to any lo- cation in memory 4! Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined out- put mode, data is registered for decreased cycle time. Clock to data valid teps = 6.5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to elimi- nate access latency. In flow-through mode data will be avail- able tep; = 15 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/PIPE pin. Each port contains a burst counter on the input address regis- ter. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. Pin Configurations A HIGH on CE, or LOW on CE, for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE, LOW and CE, HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's address strobe (ADS). When the port's count enable (CNTEN) is asserted, the address counter will incrernent on each LOW-to-HIGH transi- tion of that ports clock signal. This will read/write_one word fromAnto each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST} is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatoack (TQFP} packages. 100-Pin TQFP (Top View) NL iy Jo pesedesegeeke @eee22282 2 265 ~ |E ce crrreere aA wz ae Oot oO ory O10 < fatgaqtcged MAINO 100 99 98 97 96 95 S94 93 92 91 90 39 88 87 86 85 84 83 82 81 80 79 78 FF 7B ro C=) 1 75 L_] aor Ato. [__] 2 74 [_] ator AliL[L_] 3 73 [_] atir Ata L_] 4 yz [7_] Aiar Ais. C=] 5 7 C=) ai3r [Note 5] aia. [] 6 70 [7 ] aun [Note 5] [Note 6] AisL [___] 7 69 [=] Aisa [Note 6] ne] 8 ss [I ne nc(lL_] 9 67 [_] nc tat CL _] 10 es [__] fer va CS 1 CY7C09289 (64K x 16) sl ceo. L_] 12 64 [__] CER cr 13 CY7C09279 (32K x 16) es od cet CNTRSTL CL] 14 62 [__] tnTRSTA vec ] 15 CY7C09269 (16K x 16) | Len AWC Eo) 16 co [=] Rw co C_ 17 59 [__] OfF [Note 7] FuPIPEL [I] 18 ss [7] Freirer (Note 7] cnD [C_] 19 s7 [-] end voisL [7] 20 56 [__] VoisR voi. [C=] 21 55 Co] vor7 voisL [C] 22 s4 [=] vos, vo1aL [_] 23 53 [_] voter voit [-==] 24 sz [-_] our voto. [=|] 25 st [-] rotor 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 UOUUUUUUUUUUUU UU UUUUUU UU rs) a J a a a = cor fr grrr go > Oo om T+ S _ asegsbse885 5 8 SBS 888 FESS BSH eeg<sgeegeegeees2oee8resegerssges sg Notes: 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. This pin is NC for CY7C09269. 6. This pin is NC for CY7C09269 and CY7C09279. 7. For C7C09269 and CY7C09279, pin #18 connected to Var is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-through device.CY7C09269/79/89 FSELIAUNASY CY7C09369/79/89 Pin Configurations (continued) 100-Pin TGFP (Top View) gedeeadebSb22boseesesees AINA nonnonnnnn OTT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 8&3 82 81 80 79 78 77 76 aL 1 Ato. __] 2 AliLl_] 3 Ata_ LL _] 4 AtsL CZ) 5 [Note 8] 14. La) 6 [Note 9] AisL[[__] 7 tar C_] s ta. 9 ceo (=) 10 ce. 11 CY7C09389 (64K x 18) ONTRSTIL L__] 12 pt 1s CY7C09379 (32K x 18) oe CJ 14 _ oL CY7C09369 (16K x 18) Freire. L) 16 vot7L C=) 17 vote. [==] 18 enp [C_] 19 vois. [7 _] 20 voi4. (=) 21 voi3sL [7] 22 Voie. (=) 23 votiL [=] 24 voro. LJ 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 [J] asr 74 [-_] aon 73 ] Aion 72 [_] aur 71 (=) ater 70 [_] ai3r 69 ] A14R [Note 8] 68 ] A15R [Note 9] ey [] (BR 66 ] uBR 6s [__] tenn e4 (=) ce1r 63 LW] CNTASTA 62 ] RAW 61 [__] end seo [__] oERA 59 [__] FripiPER 58 [-__] voir 57 ] GND 56 ] voter 55 [7] loisr 54 [7 _] vorar, 63 [7] vo13R 52 ] vo12R s1 [2 J] our, Oo YX x = LY ee = Selection Guide MOUTON OTONOTTL Q oc oO > VOFR VO8R WOR CY7C09269/79/89 | CY7C09269/79/89 | CY7C09269/79/89 | CY7C09269/79/89 CY7C09369/79/89 | CY7C09369/79/89 | CY7C09369/79/89 | CY7C09369/79/89 -6 7 9 -12 fmaxe (MHz) (Pipelined) 100 83 67 50 Max Access Time (ns) (Clock to Data, 6.5 75 9 12 Pipelined) Typical Operating Current Igg (mA) 250 235 215 195 Typical Standby Current for Iga, (mA) 45 40 35 30 (Both ports TTL Level} Typical Standby Current for Iga (mA) 0.05 0.05 0.05 0.05 (Both ports GMOS level) Notes: 8. This pin is NC for CY7C09369. 9. This pin is NC for CY7C09369 and CY7C09379.a Pin Definitions CY7C09269/79/89 RRECIANNARY CY7C09369/79/89 Left Port Right Port Description AgtAis. Aor-Aisa Address Inputs (AgAy4 for 32K, ApA;3 for 16K devices). ADSL ADSp Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE g,,CEy, | CEgR.CEyR_ | Chip Enable Input. To select either the left or right port, both CE, AND CE, must be asserted to their active states (CE, < V_ and CE, > Vj,). CLK. CLK Glock Signal. This input can be free running or strobed. Maximum clock input rate is fyjax. CNTEN_ CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRST_, CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst_address counter of its respec- tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN. VWOgr-VOy7L | VOoR-VOy7_ | Data Bus Input/Output (I/O p-1/O; 5 for x16 devices). LBL LBr Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/OgI/Og for x18, I/O 9-1/0; for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. UBL UBRA Upper Byte Select Input. Same function as LB, but to the upper byte (I/OQg/,-W/Oy5471). OE, OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. RM, RW, Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPE, FT/PIPER Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NG No Gonnect. Voc Power Input. Maximum Ratings Output Current into Outputs (LOW)... ccc 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage 00.00.0000. >1100V lines, not tested.) Lateh-Up Current... eee tee eee >200 mA 3 o Storage Temperature 0.0.0... 65G to +150C Operating Range Ambient Temperature with Power Applied .55C to +125C Amb Supply Voltage to Ground Potential .............. 0.3V to +7.0V Range Temperature Voc DC Voltage Applied to Commercial 0C to +70C 5V + 10% Outputs in High 7 State oe. 0.5V to +7.0V - Industria 40S to +85C BV + 10% D Input Voltage... ee 0.5V to +7.0V Shaded area contains acvance information.CY7C09269/79/89 BRSLIMINASY CY7C09369/79/89 ee Le Electrical Characteristics Over the Operating Range CY7C09269/79/89 CY7C09369/79/89 -6 7 -9 -12 Symbol Parameter Min | Typ | Max |} Min | Typ | Max] Min | Typ | Max | Min | Typ | Max | Units Vou Qutput HIGH Voltage (Vec=Min, | 2.4 24 24 24 Vv VoL Output LOW Voltage (Vcc=Min, 04 0.4 0.4 0.4 Vv loH= +4.0 mA) Vi Input HIGH Voltage 2.2 2.2 2.2 2.2 Vv VIL Input LOW Voltage 0.8 0.8 0.8 08 V loz Output Leakage Current 10 10 | -10 10 | -10 10 | -10 10 | pA lec Operating Current Goml. 250 | 450 235 | 420 215 | 360 195 |} 300 | mA (Voo=Max, lour=0 MA) Pindust. 260 | 445 245 | 410 225 | 375 | mA Quiputs Disabled Isp Standby Current (Both Com. 45 | 115 40 | 105 35 | 95 30 |] 85 | mA Ports TTL Level)! " CE, & CEn > Vi, fhyax Indust. 55 | 120 50 | 110 45 [100[ mA Isp Standby Current (One Com. 175 | 235 160 | 220 145 | 205 125)190| mA Port TTL Level)" CEL | Tindust. 175 | 235 160 | 220 140 | 205 | mA CER = Vin, feimax Isa3 Standby Current (Both Com. 0.05 | 0.25 0.05 | 0.25 0.05 | 0.25 0.05]0.25| mA Ports CMOS Level) CE, &CEp>Vog-0.2V indust. 0.05 | 6.25 0.05 | 0.25 0.05/0.25) mA f=0 lopa Standby Current (ane Gom'l. 160 | 200 145 | 185 130 | 170 110] 150] mA Port CMOS Level) CE, | CEq > Vin, Ffrnax Indust. 160 | 200 145 | 185 125 | 165] mA Shaded area contains advance information. Capacitance Parameter Description Test Conditions Max. Unit Cn Input Capacitance Ta =25C, f =1 MHz, 10 pF Court Output Capacitance Voc = 5.0V 10 pF AC Test Loads 5V 5V Ri = 8930 Rry = 2502 OUTPUT, OUTPUT Ri = 9930 C= 300F OUTPUT eT R2= 3470 TL C= 5 pF = = = 8 Ving 14V R2 = 3470 (b) Thvenin Equivalent (Load 1) (a) Normal Load (Load 1) ALLINPUTPULSES (c) Three-State Delay (Load 2) (Used for texiz, torz, & tonz 3.0V including scope and jig) GND <3ns <3ns Note: 10. CE, and CE, are internal signals. To select either the left or right port, both CE, AND CE, must be asserted to their active states (CE, < V\_ and CE, > Vj)CY7C09269/79/89 SELINA RY CY7C09369/79/89 ae Switching Characteristics Over the Operating Range C7C09269/79/89 CY7C09369/79/89 -6 7 3 12 Symbol Parameter Min | Max | Min | Max | Min | Max | Min | Max | Units fmaxt fax Flow-Through 53 45 40 33 MHz fMmaxe fax Pipelined 100 83 67 50 MHz teyer Clock Cycle Time - Flow-Through 19 22 25 30 ns teyce Clock Cycle Time - Pipelined 10 12 15 20 ns tou1 Clock HIGH Time - Flow-Through 6.5 75 12 12 ns teu Clock LOW Time - Flow-Through 6.5 75 12 12 ns teye Clock HIGH Time - Pipelined 4 3 6 8 ns toLe Clock LOW Time - Pipelined 4 5 6 8 ns tr Glock Rise Time 3 3 3 3 ns te Clock Fall Time 3 3 3 3 ns tsa Address Set-Up Time 3.5 4 4 4 ns tha Address Hold Time 0 0 1 1 ns tse Chip Enable Set-Up Time 3.5 4 4 4 ns tue Chip Enable Hold Time 0 0 1 1 ns tow R/W Set-Up Time 3.5 4 4 4 ns tuw RAW Hold Time 0 0 1 1 ns tsp Input Data Set-Up Time 3.5 4 4 4 ns tup Input Data Hold Time 0 0 1 1 ns tsap ADS Set-Up Time 35 4 4 4 ns tuap ADS Hold Time 0 0 1 1 ns tscn CNTEN Set-Up Time 3.5 4 4 4 ns ton CNTEN Hold Time 0 0 1 1 ns tsast CNTRST Set-Up Time 3.5 4 4 4 ns turst CNTRST Hold Time 0 0 1 1 ns toe Qutput Enable to Data Valid 8 9 10 12 ns torz''121 | OE to Low Z 2 2 2 2 ns toll | OE to High Z 1 7 1 7 1 7 1 7 ns tep1 Clock to Data Valid - Flow-Through 15 18 20 25 ns tep2 Clock to Data Valid - Pipelined 6.5 75 9 12 ns too Data Output Hold After Clock HIGH 2 2 2 2 ns toxyz!!t-121 | Clock HIGH to Output High Z 2 9 2 9 2 9 2 9 ns toxigt!114I | Glock HIGH to Output Low Z 2 2 2 2 ns Port to Port Delays tewpp Write Port Glock HIGH to Read Data Delay 30 30 40 40 ns tecs Clock to Glock Set-Up Time 9 10 15 15 ns Notes: 11. Test conditions used are Load 2. 12. This parameter is guaranteed by design, but it is not production tested.CY7C09269/79/89 BRSLIMINASY CY7C09369/79/89 Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V,, )!13-14.15.16] teyer He toy + tol clk __ fON FN NN tse tue nit DN | KOKI | OOO ODIO | XOXO tow tw tga ADDRESS DATAgut Read Cycle for Pipelined Operation (FT/PIPE = Vj4)!'9:'415-16] leye2 a, 7 \V_# \VN_#* \ os OO | KKK | XKXKKY TROOOOKn_ | KXOOKOK WY DIO | OOOO | XO XOOOO | XOOOO tsw tHw tsa tua ADDRESS An Anat Anse Ansa DATA 1 Latency e tape toc OUT Q, Qnt Qhi2 ton zt texz toLz OE toe Notes: 13. GEis asynchronously controlled; all other inputs are synchronous to the rising clock edge. 14. ADS = V\_, CNTEN and CNTRST = Vix. 15. The output is disabled (high-impedance state) by CE,=V\, or CE, = Vj, following the next rising edge of the clock. 16. Addresses do not have to be accessed sequentially since ADS = V|_ constantly loads the address on the rising edge of the CLK. Numbers are for reference only.CY7C09269/79/89 BRSLIMINASY CY7C09369/79/89 Switching Waveforms (continued) Bank Select Pipelined Read!'7.15] lever teHe CLK, ADDRESS 1) CE gt) DATAoutiet ADDRESS pa) CE pinay DATAguT B2) Left Port Write to Flow-Through Right Port Read!'9.20.21.22] CLK, RAW ADDRESS, DATAInL CLKr RW ADDRESSp DATAoutR toc toe Notes: 17. Inthis depth expansion example, B1 represents Bank #1 and B2 is Bank #2; each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS,a1) = ADDRESSp 2). ? a Ss 18. UB, LB, OF and ADS = V)_; CEy(a4), CEqap). RAW, CNTEN, and CNTRST = Vix. 19. The same wavetorms apply for a right port write to flow-through left port read. 20. CE,, UB, LB, and ADS = V|_; CE,, CNTEN, and CNTRST = Vj. 21. GE = Vj, for the Right Port, which is being read from. OE = V),, for the Lett Port, which is being written to. 22. Itteeg < maximum specified, then data from right port READ is not valid until the maximum specitied for teypp. Ifteeg>maximum specified, then data is not valid until tees + tep1. tewpp does not apply in this case.CY7C09269/79/89 BRSLIMINASY CY7C09369/79/89 Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = Vj, )!'5.29.24.25] lovee CLK 7 ~ f KK \Y\ NAN DN SL AXA AKA | AKA LAA te ADDRESS DATA DATAguT Qn Ong NO OPERATION WRITE READ - - Pipelined Read-to-Write-to-Read (OE Controlled)!' 29.24.25] teyc2 ce, KON | AKA | AKA | KAKA LAKA LAKXA | KKA tsc tue iy oc, KM | NY | KOO, |, SOO | OO | OOM | SOO tow] tHw, f KX RAW NY | SOA LT AXY |XX tsw tw ADDRESS Isa | tua ts typ DATA Dawe KKK ons KK tep2 toKLz tepe2 DATAguT Q, Qa44 WRITE Notes: 23. Qutput state (HIGH, LOW,or High-lmpedance} is determined by the previous cycle control signals. 24. CE, and ADS = V|; GE,, CNTEN, and GNTRST = Vz. 25. During No operation, data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.CY7C09269/79/89 BRSLIMINASY CY7C09369/79/89 Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = V,, )I'14.16.23.24] tover tout tou CLK fa sf ADDRESS DATA DATAout NO OPERATIO Flow-Through Read-to-Write-to-Read (OE Controlled)!'4:'6.23.24] teyc1 tout tou CLK fa m ADDRESS DATAIn DATAgur OE 10CY7C09269/79/89 a cet SOS! AIAN A RY CY7C09369/79/89 =e Switching Waveforms (continued) Pipelined Read with Address Counter Advance!l lovee tele tone CLK tHA ADDRESS Qe Qn43 DATAouT Qy4 Qy Q, One READ tbe COUNTER HOLD _ EXTERNAL ADDRESS READ WITH COUNTER READ WITH COUNTER Flow-Through Read with Address Counter Advance!*l teyer ten tout CLK ADDRESS tap CNTEN tHon DATAgut Q, Qt One Qn43 be READ READ = EXTERNAL READ WITH COUNTER COUNTER HOLD WITH ADDRESS COUNTER Note: 26. CE, and OE = V,; CE,, R/W and CNTRST = Vip, 11SESE FRSECUMINARY CY7C09269/79/89 CY7C09369/79/89 Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)!2 78 CLK ADDRESS INTERNAL ADDRESS AOS KY he - CNTEN x teyc2 toHe | tote tsa ta Ke ROKK KORE OOOO KKK A, x Ant Anse mx Ansa x An tsap tab AKY Yr NA LAO | KY NON tsen tHoN DATA BD, Der KKK Oe Dniz Drig Disa tsp tub WRITE EXTERNAL WRITE WITH | WRITE COUNTER 7 ADDRESS ~" COUNTER HOLD ~% WRITE WITH COUNTER Notes: 27. CE , UB, LB, and RAW = V; CE, and CNTRST = Vy. 28. The Internal Address is equal to the External Address when ADS = V|, and equals the counter output when ADS = V\,.. 12CY7C09269/79/89 = FRECIMINSSY CY7C09369/79/89 Switching Waveforms (continued) Counter Reset (Pipelined Outputs)!'.28.29.30] tevea toe | tote CLK oN a tsa | tua | | WENA R_ >X Ka Ke tsw | tow aw XD | KO |X XY (XY SAD HAD 78 RY |XOOY AXX_ |AKX tsen then enTeN OY [NOY | SOO OOKN KOO ROOD IKK tgrstT tHRST CRTRST DOOD | AY 0 [OOK KR KY XY RKY DATA COUNTER RESET WRITE ~~ ADDRESS 0 *|* ADDRESS 07] READ READ ADDRESS 1-7 ADDRESSn READ Notes: 29. CE,, UB, andCB = Vv); CE, = Vip. 30. Nodead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 13CY7C09269/79/89 SELINA RY CY7C09369/79/89 Read/Write and Enable Operation!" 42.73! Inputs Outputs OE | CLK | CE, | CE, | RAW] VOg4+0,7 Operation igh- [34] x __ H x x High-2 Deselected igh- [34] xX ir xX L X High-Z Deselected 4 cr L H L Din Write Lp oe L H H Dout Read!*4] H x H X High-7 Qutputs Disabled Address Counter Control Operation!?! 95.56.97] Previous Address | Address | CLK | ADS | CNTEN | CNTRST i) Mode Operation X X _ x X L Doutioy Reset Counter Reset to Address 0 An x _ L x H Deuttn) Load Address Load into Counter Xx An _ H H H Doutiny Hold External Address BlockedCounter Disabled Xx An cr H L H Douynet) | Increment | Counter EnabledInternal Address Generation Notes: 31. X" = Don't Care, *H" = Vj4, L=V_. 32. | DS, CNTEN, CNTRST = Don't Care. 33. OE is an_asynchronous input signal. 34. When GE chan v 35. CE, and OE = ,; CE, and RW = Vj. 36. Data shown for flow-through mode: pipelined mode output will be delayed by one cycle. 37. Counter operation is independent of CE, and GE, 14 state in the pipelined mode, deselection and read happen in the following clock cycle.CY7C09269/79/89 SELINA RY CY7C09369/79/89 Ordering Information 16K x16 Synchronous Dual-Port SRAM Speed Package Operating ns) Ordering Code Name Package Type ange 6.5 CY7C09269-6AG A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09269-7AG A100 100-Pin Thin Quad Flat Pack Commercial C7G09269-7Al At0G 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09269-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09269-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09269-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C092689-12Al Atoo 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 32K x16 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C09279-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09279-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-7Al Atoo 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09279-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09279-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09279-12Al A100 106-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x16 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C09289-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09289-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09289-7Al A100 106-Pin Thin Quad Flat Pack Industrial 9 CY7C09289-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09289-9Al AtoG 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09289-12AC A100 100-Pin Thin Quad Flat Pack Commercial GY7C09289-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 15CY7C09269/79/89 SELINA RY CY7C09369/79/89 Ordering Information (continued) 16K x18 Synchronous Dual-Port SRAM Speed Package Operating ns) Ordering Code Name Package Type ange 6.5 CY7C09369-6AG A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09369-7AG A100 100-Pin Thin Quad Flat Pack Commercial C7G09369-7Al At0G 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09369-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09369-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09369-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-12Al Atoo 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advancd information. 32K x18 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C09379-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09379-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09379-7Al Atoo 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09379-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09379-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09379-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09379-12Al A100 106-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x18 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C09389-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09389-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-7Al A100 106-Pin Thin Quad Flat Pack Industrial 9 CY7C09389-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09389-9Al AtoG 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09389-12AC A100 100-Pin Thin Quad Flat Pack Commercial GY7G09389-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. Document #: 38-00664-D 16CY7C09269/79/89 OSHRSS PRE UANNARY CY7C09369/79/89 Sao ke EE ead Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 16002025 SO 14.0020.05 $0 DIMENSIONS ARE IN MILLIMETERS. 0222005 R 0.09 MIN. O MIN. 20 MAX. STAND-DFF 0.05 MIN. ( oo \ | 0.25 | O15 MAX. | C GAUGE PLANE r =-3-5 = ite om 050 020 MIN. TYP. == 1.602015 1.00 REF. - 51-85048-A DETAIL A SEE DETAIL A Cypress Semiconductor Corporation, 1998. The information contained herein is subject io change without notice. Cypress Semiconductor Corporation assumes no responsibility tor the use ofany circuitry other than circuliry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical componenis in life-support systems where a maliunction or failure may reasonably be expected io resull in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.