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FEATURES
DESCRIPTION
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
EN1
EN2
A
’LVDS104
EN4
logic diagram (positive logic)
EN3
B
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
EN1
EN2
A
’LVDS105
EN4
EN3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN1
EN2
EN3
VCC
GND
A
B
EN4
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
SN65LVDS104
D OR PW PACKAGE
(Marked as LVDS104)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN1
EN2
EN3
VCC
GND
A
NC
EN4
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
SN65LVDS105
D OR PW PACKAGE
(Marked as LVDS105)
(TOP VIEW)
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
•Receiver and Drivers Meet or Exceed theRequirements of ANSI EIA/TIA-644 Standard– SN65LVDS105 Receives Low-Voltage TTL(LVTTL) Levels– SN65LVDS104 Receives Differential InputLevels, ±100 mV•Typical Data Signaling Rates to 400 Mbps orClock Frequencies to 400 MHz•Operates From a Single 3.3-V Supply•Low-Voltage Differential Signaling WithTypical Output Voltage of 350 mV and a 100- ΩLoad
•Propagation Delay Time– SN65LVDS105 – 2.2 ns (Typ)– SN65LVDS104 – 3.1 ns (Typ)•LVTTL Levels Are 5-V Tolerant•Electrically Compatible With LVDS, PECL,LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,SSTL, or HSTL Outputs With ExternalNetworks
•Driver Outputs Are High Impedance WhenDisabled or With V
CC
<1.5 V•Bus-Pin ESD Protection Exceeds 16 kV•SOIC and TSSOP Packaging
The SN65LVDS104 and SN65LVDS105 are a differ-ential line receiver and a LVTTL input (respectively)connected to four differential line drivers that im-plement the electrical characteristics of low-voltagedifferential signaling (LVDS). LVDS, as specified inEIA/TIA-644 is a data signaling technique that offerslow-power, low-noise coupling, and switching speedsto transmit data at relatively long distances. (Note:The ultimate rate and distance of data transfer isdependent upon the attenuation characteristics of themedia, the noise coupling to the environment, andother system characteristics.)
The intended application of this device and signaling technique is for point-to-point baseband data transmissionover controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit boardtraces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulseskew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
300 kΩ300 kΩ
VCC
7 V 7 V
A
Input B
Input 7 V
300 kΩ
50 Ω
VCC
EN and
A (’LVDS105)
Input
VCC
5 Ω
7 V
Y or Z
Output
10 kΩ
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40 °C to 85 °C.
The SN65LVDS104 and SN65LVDS105 are members of a family of LVDS repeaters. A brief overview of thefamily is provided in the table below.
Selection Guide to LVDS Repeaters
DEVICE NO. INPUTS NO. OUTPUTS PACKAGE COMMENT
SN65LVDS22 2 LVDS 2 LVDS 16-pin D Dual multiplexed LVDS repeaterSN65LVDS104 1 LVDS 4 LVDS 16-pin D 4-Port LVDS repeaterSN65LVDS105 1 LVTTL 4 LVDS 16-pin D 4-Port TTL-to-LVDS repeaterSN65LVDS108 1 LVDS 8 LVDS 38-pin DBT 8-Port LVDS repeaterSN65LVDS109 2 LVDS 8 LVDS 38-pin DBT Dual 4-port LVDS repeaterSN65LVDS116 1 LVDS 16 LVDS 64-pin DGG 16-Port LVDS repeaterSN65LVDS117 2 LVDS 16 LVDS 64-pin DGG Dual 8-port LVDS repeater
Function Tables
(1)
SN65LVDS104 SN65LVDS105
INPUT OUTPUT INPUT OUTPUT
V
ID
= V
A
- V
B
xEN xY xZ A ENx xY xZ
X X Z Z L H L HX L Z Z H H H LV
ID
≥100 mV H H L Open H L H–100 mV < V
ID
< 100 mV H ? ? X L Z ZV
ID
≤–100 mV H L H X X Z Z
(1) H = high level, L = low level, Z = high impedance, ? = indeterminate, X = don't care
2
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage range, V
CC
(2)
–0.5 to 4 VEnables, A ('LVDS105) –0.5 to 6 VVoltage range
A, B, Y or Z –0.5 to 4 VElectrostatic discharge
(3)
A, B, Y, Z, and GND Class 3, A:16 kV, B: 400 VContinuous power dissipation See Dissipation Rating TableStorage temperature range –65 °C to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7
T
A
≤25 °C OPERATING FACTOR
(1)
T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING
D 950 mW 7.6 mW/ °C 494 mWPW 774 mW 6.2 mW/ °C 402 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) andwith no air flow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.8 VV
I
or V
IC
Voltage at any bus terminal (separately or common-mode) 0 V
CC
–0.8T
A
Operating free-air temperature –40 85 °C
3
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SN65LVDS104 ELECTRICAL CHARACTERISTICS
SN65LVDS104 SWITCHING CHARACTERISTICS
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input voltage threshold 100See Figure 1 and Table 1 mVV
IT-
Negative-going differential input voltage threshold –100|V
OD
| Differential output voltage magnitude 247 340 454R
L
= 100 Ω, V
ID
=±100 mV,
mVChange in differential output voltage magnitude between logic
See Figure 1 and Figure 2∆|V
OD
| –50 50statesV
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 VChange in steady-state common-mode output voltage be-∆V
OC(SS)
See Figure 3 –50 50 mVtween logic statesV
OC(PP)
Peak-to-peak common-mode output voltage 25 150 mVEnabled, R
L
= 100 Ω23 35 mAI
CC
Supply current
Disabled 3 8 mAV
I
= 0 V –2 –11 –20I
I
Input current (A or B inputs) µAV
I
= 2.4 V –1.2 –3I
I(OFF)
Power-off Input current V
CC
= 1.5 V, V
I
= 2.4 V 20 µAI
IH
High-level input current (enables) V
IH
= 2 V 20 µAI
IL
Low-level input current (enables) V
IL
= 0.8 V 10 µAV
OY
or V
OZ
= 0 V ±10 mAI
OS
Short-circuit output current
V
OD
= 0 V ±10 mAI
OZ
High-impedance output current V
O
= 0 V or 2.4 V ±1 µAI
O(OFF)
Power-off output current V
CC
= 1.5 V, V
O
= 2.4 V ±1 µAC
IN
Input capacitance (A or B inputs) V
I
= 0.4 sin (4E6 πt) + 0.5 V 3 pFV
I
= 0.4 sin (4E6 πt) + 0.5 V,C
O
Output capacitance (Y or Z outputs) 9.4 pFDisabled
(1) All typical values are at 25 °C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2.4 3.2 4.2 nst
PHL
Propagation delay time, high-to-low-level output 2.2 3.1 4.2 nst
r
Differential output signal rise time 0.3 0.8 1.2 nsR
L
= 100 Ω, C
L
= 10 pF,See Figure 4t
f
Differential output signal fall time 0.3 0.8 1.2 nst
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) 150 500 pst
sk(o)
Channel-to-channel output skew
(2)
20 100 pst
sk(pp)
Part-to-part skew
(3)
1.5 nst
PZH
Propagation delay time, high-impedance-to-high-level output 7.2 15 nst
PZL
Propagation delay time, high-impedance-to-low-level output 8.4 15 nsSee Figure 5t
PHZ
Propagation delay time, high-level-to-high-impedance output 3.6 15 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 6 15 ns
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
of all drivers of a single device with all of their inputs connectedtogether.
(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
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SN65LVDS105 ELECTRICAL CHARACTERISTICS
SN65LVDS105 SWITCHING CHARACTERISTICS
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
|V
OD
| Differential output voltage magnitude 247 340 454R
L
= 100 Ω,V
ID
=±100 mV, mVChange in differential output voltage magnitude between logic∆|V
OD
| –50 50See Figure 6 and Figure 7states
1.37V
OC(SS)
Steady-state common-mode output voltage 1.125 V5Change in steady-state common-mode output voltage between See Figure 8∆V
OC(SS)
–50 50 mVlogic statesV
OC(PP)
Peak-to-peak common-mode output voltage 25 150 mVEnabled, R
L
= 100 Ω23 35 mAI
CC
Supply current
Disabled 0.7 6.4 mAI
IH
High-level input current V
IH
= 2 V 20 µAI
IL
Low-level input current V
IL
= 0.8 V 10 µAV
OY
or V
OZ
= 0 V ±10 mAI
OS
Short-circuit output current
V
OD
= 0 V ±10 mAI
OZ
High-impedance output current V
O
= 0 V or 2.4 V ±1 µAI
O(OFF)
Power-off output current V
CC
= 1.5 V, V
O
= 2.4 V 0.3 ±1 µAC
IN
Input capacitance V
I
= 0.4 sin (4E6 πt) + 0.5 V 5 pFV
I
= 0.4 sin (4E6 πt) + 0.5 V,C
O
Output capacitance (Y or Z outputs) 9.4 pFDisabled
(1) All typical values are at 25 °C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 1.7 2.2 3 nst
PHL
Propagation delay time, high-to-low-level output 1.4 2.3 3.5 nst
r
Differential output signal rise time 0.3 0.8 1.2 nsR
L
= 100 Ω, C
L
= 10 pF,See Figure 9t
f
Differential output signal fall time 0.3 0.8 1.2 nst
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) 150 500 pst
sk(o)
Channel-to-channel output skew
(2)
20 100 pst
sk(pp)
Part-to-part skew
(3)
1.5 nst
PZH
Propagation delay time, high-impedance-to-high-level output 7.2 15 nst
PZL
Propagation delay time, high-impedance-to-low-level output 8.4 15 nsSee Figure 10t
PHZ
Propagation delay time, high-level-to-high-impedance output 3.6 15 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 6 15 ns
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
of all drivers of a single device with all of their inputs connectedtogether.
(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
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PARAMETER MEASUREMENT INFORMATION
II
VIB
VID
VIA
A
B
IIB VOD
VOZ
VOY
VOC
IOY
IOZ
Z
Y
VOY VOZ
2
±
3.75 kΩ
0 V ≤ VTEST ≤ 2.4 V
Y
ZVOD
Input 100 Ω
3.75 kΩ
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
Figure 1. 'LVDS104 Voltage and Current Definitions
Table 1. SN65LVDS104 Minimum and Maximum Input Threshold Test Voltages
RESULTING RESULTINGAPPLIED
DIFFERENTIAL COMMON-MODEVOLTAGES
INPUT VOLTAGE INPUT VOLTAGE
V
IA
V
IB
V
ID
V
IC
1.25 V 1.15 V 100 mV 1.2 V1.15 V 1.25 V –100 mV 1.2 V2.4 V 2.3 V 100 mV 2.35 V2.3 V 2.4 V –100 mV 2.35 V0.1 V 0 V 100 mV 0.05 V0 V 0.1 V –100 mV 0.05 V1.5 V 0.9 V 600 mV 1.2 V0.9 V 1.5 V –600 mV 1.2 V2.4 V 1.8 V 600 mV 2.1 V1.8 V 2.4 V –600 mV 2.1 V0.6 V 0 V 600 mV 0.3 V0 V 0.6 V –600 mV 0.3 V
Figure 2. 'LVDS104 V
OD
Test Circuit
6
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Y
Z
49.9 Ω ± 1% (2 Places)
VOC
VO
VOC(PP) VOC(SS)
1 V
1.4 V
VI
Input
(see Note A)
VI
CL = 10 pF
(2 Places)
(see Note B)
1.4 V
1.2 V
1 V
tPLH tPHL
100%
80%
20%
0%
Input
Output
0 V
tftr
VOD(H)
VOD(L)
VIB
VIA
Y
ZVOD 100 Ω ± 1%
A
Input
(see Note A)
CL = 10 pF
(2 Places)
(see Note B)
B
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns.B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V
OC(PP)
is madeon test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. 'LVDS104 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulsewidth = 10 ±0.2 ns.B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 4. 'LVDS104 Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
7
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II
VIA
AVOD
VOZ
VOY
VOC
IOY
IOZ
Z
Y
VOY VOZ
2
±
3.75 kΩ
0 V ≤ VTEST ≤ 2.4 V
Y
ZVOD
Input 100 Ω
3.75 kΩ
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns.B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 5. 'LVDS104 Enable and Disable Time Circuit and Definitions
Figure 6. 'LVDS105 Voltage and Current Definitions
Figure 7. 'LVDS105 VOD Test Circuit
8
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Y
Z
49.9 Ω ± 1% (2 Places)
VOC
VO
VOC(PP) VOC(SS)
0 VA
3 V
CL = 10 pF
(2 Places)
(see Note B)
Input
(see Note A)
Y
ZVOD
Input
(see Note A)
CL = 10 pF
(2 Places)
(see Note B)
100 Ω ± 1%
3 V
1.5 V
0 V
tPLH tPHL
100%
80%
20%
0%
Input
Output
0 V
tftr
VOD(H)
VOD(L)
VIA
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns.B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of V
OC(PP)
is madeon test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 8. 'LVDS105 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulsewidth = 10 ±0.2 ns.B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 9. 'LVDS105 Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
9
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tPZH tPHZ
tPZL tPLZ
3 V
1.5 V
0 V
≅ 1.4 V
1.25 V
1.2 V
≅ 1 V
1.2 V
1.15 V
EN
VOY
or
VOZ
VOZ
or
VOY
Y
Z
CL = 10 pF
(2 Places)
(see Note B)
49.9 Ω ± 1% (2 Places)
1.2 V
VOY VOZ
0.8 V or 2 V
EN
Input
(see Note A)
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns.B. C
L
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 10. 'LVDS105 Enable and Disable Time Circuit and Definitions
10
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TYPICAL CHARACTERISTIC
25
30
35
40
45
50
55
60
50 100 150 200 250 300 350
f − Frequency − MHz
− Supply Current − mA
ICC
VCC = 3.6 V
VCC = 3 V
All Outputs Loaded
and Enabled
VCC = 3.3 V
20
25
30
35
40
45
50
50 100 150 200 250 300 350
f − Frequency − MHz
− Supply Current − mA
ICC
VCC = 3.6 V
VCC = 3 V
All Outputs Loaded
and Enabled
VCC = 3.3 V
−4 IOH − High-Level Output Current − mA
3.5
2.5
0−2 0
1.5
−3
0.5
VOH− High-Level Output Voltage − V
−1
3
2
1
VCC = 3.3 V
TA = 25°C
0IOL − Low-Level Output Current − mA
4
3
04 6
2
2
VCC = 3.3 V
TA = 25°C
1
VOL − Low-Level Output Voltage − V
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
SN65LVDS104 SN65LVDS105SUPPLY CURRENT SUPPLY CURRENTvs vsFREQUENCY FREQUENCY
Figure 11. Figure 12.
DRIVER DRIVERLOW-LEVEL OUTPUT VOLTGE HIGH-LEVEL OUTPUT VOLTGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 13. Figure 14.
11
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TA − Free-Air Temperature − °C
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−50 −25 0 25 50 75 100
tPLH − Low-To-High Propagation Delay Time − ns
VCC = 3.6 V
VCC = 3 V
VCC = 3.3 V
TA − Free-Air Temperature − °C
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−50 −25 0 25 50 75 100
tPHL − High-To-Low Propagation Delay Time − ns
VCC = 3.6 V
VCC = 3 V
VCC = 3.3 V
TA − Free-Air Temperature − °C
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
−50 −25 0 25 50 75 100
tPLH − Low-To-High Propagation Delay Time − ns
VCC = 3.6 V
VCC = 3 V
VCC = 3.3 V
TA − Free-Air Temperature − °C
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
−50 −25 0 25 50 75 100
tPHL − High-To-Low Propagation Delay Time − ns
VCC = 3.6 V
VCC = 3 V
VCC = 3.3 V
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC (continued)
SN65LVDS104 SN65LVDS104LOW-TO-HIGH PROPAGATION DELAY TIME HIGH-TO-LOW PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 15. Figure 16.
SN65LVDS105 SN65LVDS105LOW-TO-HIGH PROPAGATION DELAY TIME HIGH-TO-LOW PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 17. Figure 18.
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0
100
200
300
400
500
600
700
800
0 100 200 300 400 500 600
Signaling Rate − Mbps
VCC = 3.6 V
VCC = 3 V
Peak-to-Peak Jitter − ps
TA = 25C
0
2
4
6
8
10
12
14
16
18
0 100 200 300 400 500 600
Clock Frequency − MHz
Peak-to-Peak Jitter − ps
TA = 25C
VCC = 3 V
VCC = 3.6 V
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC (continued)
SN65LVDS104 P-P EYE-PATTERN JITTERvsPRBS SIGNALING RATE
NOTES: Input: 2
15
PRBS with peak-to-peak jitter <115 ps at 100 Mbps. Test board adds about 70 ps p-p jitter. All outputsenabled and loaded with differential 100- Ωloads, worst-case output, supply decoupled with 0.1-µF ceramic 0603-stylecapacitors 1 cm from the device.
Figure 19.
SN65LVDS104 P-P PERIOD JITTERvsCLOCK FREQUENCY
NOTES: Input: 50% duty cycle square wave with period jitter < 9 ps at 100 MHz. Test board adds about 5 ps p-p jitter. Alloutputs enabled and loaded with differential 100- Ωloads, worst-case output, supply decoupled with 0.1-µF and0.001-µF ceramic 0603-style capacitors 1 cm from the device.
Figure 20.
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0
100
200
300
400
500
600
0 100 200 300 400 500 600
Signaling Rate − Mbps
VCC = 3.6 V
VCC = 3 V
Peak-to-Peak Jitter − ps
TA = 25C
0
2
4
6
8
10
12
14
0 100 200 300 400 500 600
Clock Frequency − MHz
Peak-to-Peak Jitter − ps
TA = 25C
VCC = 3 V
VCC = 3.6 V
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC (continued)
SN65LVDS105 P-P EYE-PATTERN JITTERvsPRBS SIGNALING RATE
NOTES: Input: 2
15
PRBS with peak-to-peak Jitter < 147 ps at 100 Mbps, Test board adds about 43 ps p-p jitter. All outputsenabled and loaded with differential 100- Ωloads, worst-case output, supply decoupled with 0.1-µF and 0.001-µFceramic 0603-style capacitors 1 cm from the device.
Figure 21.
SN65LVDS105 P-P PERIOD JITTERvsCLOCK FREQUENCY
NOTES: Input: 50% duty cycle square wave with period jitter < 10 ps at 100 MHz. Test board adds about 5 ps p-p jitter. Alloutputs enabled and loaded with differential 100- Ωloads, worst-case output, supply decoupled with 0.1-µF and0.001-µF ceramic 0603-style capacitors 1 cm from the device.
Figure 22.
14
www.ti.com
APPLICATION INFORMATION
INPUT LEVEL TRANSLATION
VDD
50 Ω
25 Ω
50
Ω
A
B
1/2 VDD
0.1 µFLVDS Receiver
VDD
50 Ω
50 Ω
A
B
1.35 V < VTT < 1.65 V
0.1 µFLVDS Receiver
VDD
A
B
1.14 V < VTT < 1.26 V
LVDS Receiver
2 kΩ
50 Ω
0.1 µF
50 Ω1 kΩ
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
An LVDS receiver can be used to receive various other types of logic signals. Figure 23 through Figure 32 showthe termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
Figure 23. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
Figure 24. Center-Tap Termination (CTT)
Figure 25. Gunning Transceiver Logic (GTL)
15
www.ti.com
A
B
1.47 V < VTT < 1.62 V
0.1 µFLVDS Receiver
Z0Z0
3.3 V
33 Ω
A
B
3.3 V
LVDS Receiver
33 Ω
51 Ω
ECL
50 Ω
50 Ω
51 Ω
120 Ω120 Ω
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Figure 26. Backplane Transceiver Logic (BTL)
Figure 27. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
16
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5 V
100 Ω
A
B
5 V
LVDS Receiver
100 Ω
33 Ω
ECL
50 Ω
50 Ω
33 Ω
82 Ω82 Ω
3.3 V
A
B
3.3 V
LVDS Receiver
7.5 kΩ0.1 µF
7.5 kΩ
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Figure 28. Positive Emitter-Coupled Logic (PECL)
Figure 29. 3.3-V CMOS
17
www.ti.com
5 V
A
B
5 V
LVDS Receiver
3.32 kΩ0.1 µF
10 kΩ
560 Ω
560 Ω
5 V
A
B
5 V
LVDS Receiver
4.02 kΩ0.1 µF
10 kΩ
470 Ω
3.3 V
3.3 V
A
B
3.3 V
LVDS Receiver
3.01 kΩ0.1 µF
4.02 kΩ
560 Ω
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Figure 30. 5-V CMOS
Figure 31. 5-V TTL
Figure 32. LVTTL
18
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FAIL SAFE
Rt = 100 Ω (Typ)
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
BY
SN65LVDS104
SN65LVDS105
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
A common problem with differential signaling applications is how the system responds when no differentialvoltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its outputlogic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and withinits recommended input common-mode voltage range. Hovever, TI LVDS receivers handles the open-input circuitsituation differently.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverpulls each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 33 . The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force theoutput to a high-level regardless of the differential input voltage.
Figure 33. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differentialinput voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function aslong as it is connected as shown in Figure 33 . Other termination circuits may allow a dc current to ground thatcould defeat the pullup currents from the receiver and the fail-safe feature.
19
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDS104D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS104DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS104DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS104DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS104PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS104PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS104PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS104PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS105PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS104DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS104PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDS105DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS105PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS104DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDS104PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDS105DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDS105PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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