AW87319 datasheet Dec. 2016 V1.2 8.5V Large Volume Ultra Low Bass 2-in-1 TLTR-AGC 2nd Smart K Audio Amplifier FEATURES DESCRIPTION Triple-Level Triple-Rate AGC algorithm AW87319 is specifically designed to improve the musical output dynamic range, enhance the overall sound quality, which is a new high efficiency, low noise, constant large volume, 2nd Smart K audio amplifiers. AW87319 integrates the high-voltage synchronous Boost with efficiency up to 84% as the Class D power stage supply. It significantly improves the output dynamic range of music. AW87319 integrates Awinic's proprietary Triple-Level Triple-Rate AGC audio algorithm, effectively eliminating music noise and improving sound quality and volume. AW87319 noise floor is as low as to 47uV, with 102dB high signal-to-noise-ratio (SNR). The ultra-low distortion 0.015% and unique Triple-Level Triple-Rate AGC technology bring high quality music enjoyment. AW87319 supports speaker and receiver 2-in-1 applications. In the receiver application, Class D power stage voltage is straightly supplied by battery. AW87319 controls internal registers through the I2C interface. Register parameters include Boost Output Voltage, Boost maximum input peak current, Class D gain, Triple-Level Triple-Rate AGC parameters. AW87319 built-in over current protection, over-temperature protection and short circuit protection function, effectively protect the chip. AW87319 uses small 2.76mm*2.36mm CSP-19 package. Enhance the bass, improve the dynamic range Increase volume, eliminate noise, timely and effectively protect the speaker 8.5V Boost Output Power4.1W@8 4.6W@6 Low Noise47V Low THD+N0.015% Overall efficiency up to 72% Support speaker, receiver 2-in-1 application Receiver mode: Noise 20V, THD+N 0.02% Support 1.8V I2C Control Interface Battery tracking AGC, for low-voltage protection Over current protection, over-temperature protection and short-circuit protection Super TDD-Noise suppression Excellent pop-click suppression High PSRR-70dB217Hz Small 2.76mm*2.36mm CSP-19 package APPLICATIONS Smart phone APPLICATION DIAGRAM VBAT C4 0.1uF 10V L 1uH 3.6A(8) / 4A(6) C2 10uF 10V C3 0.1uF 10V D4 VDD D3 GPIO 2 I C Interface E3 { E4 D2 I2C Address Select Cin47nF Cin+ 47nF E2 E1 For details, See "Boost Inductor Selection" A4,B3 SW RSTN PVDD SCL AD1 C1 0805 10uF 25V See"Boost capacitor Selection" AW87319 INN VOP A1 B+ C+ 0.1nF 16V INP VON See"PCB AND DEVICE LAYOUT CONSIDERATION" A2,B2,C2 C0 0805 10uF 25V SDA AD2 C3 GND BGND D1 B4,C4 PGND B1 12V SPK C1 BC0.1nF 16V 12V See"Output beads, capacitors, TVS" Figure1 AW87319 Single-ended input mode Application Diagram (c) 2016 www.awinic.com.cn 1 AW87319 datasheet Dec. 2016 V1.2 VBAT C4 0.1uF 10V L 1uH 3.6A(8) / 4A(6) C2 10uF 10V C3 0.1uF 10V D4 VDD D3 GPIO I2C Interface E3 { E4 D2 I2C Address Select Cin47nF E2 Speaker Audio DAC Cin+ 47nF MUX Receiver E1 A4,B3 SW RSTN PVDD C0 0805 10uF 25V SCL C1 0805 10uF 25V AD1 AW87319 INN VOP A1 B+ C+ 0.1nF 16V INP BB VON AD2 C3 Figure2 A2,B2,C2 SDA GND BGND D1 B4,C4 12V SPK C1 BC0.1nF 16V PGND B1 12V AW87319 Receiver Mode Application Diagram All trademarks are the property of their respective owners. PIN CONFIGURATION AND TOP MARK AW87319 CSR MARKING AW87319 CSR TOP VIEW 1 2 A VOP PVDD B PGND PVDD C VON D E 3 1 4 SW A SW BGND B PVDD AD2 BGND C GND AD1 RSTN VDD D INP INN SDA SCL E 2 3 4 AW87319 XXXX AW87319 - AW87319 CSR XXXX - Production tracking code Figure3 AW87319CSR pin diagram top view and device marking (c) 2016 www.awinic.com.cn 2 AW87319 datasheet Dec. 2016 V1.2 PIN DESCRIPTION Number Symbol Description A1 VOP A2,B2,C2 PVDD A4,B3 SW B1 PGND Amplifier power ground B4,C4 BGND Boost power ground C1 VON Negative audio output terminal C3 AD2 I2C address pin2 D1 GND Ground D2 AD1 I2C address pin1 D3 RSTN D4 VDD Power supply E1 INP Positive audio input terminal E2 INN Negative audio input terminal E3 SDA I2C-bus data input/output E4 SCL I2C-bus clock input Positive audio output terminal Boost charge pump output voltage Boost Switch pin Reset pin ORDERING INFORMATION Product Type Operation temperature range Package Device Marking AW87319CSR -40C85C CSP-19 AW87319 Moisture Sensitivity Level Environmental Information MSL1 ROHS+HF Device Marking Delivery Form AW87319 Tape and Reel 6000 pcs AW87319 Shipment R : Tape & Reel Package type CS : CSP19 (c) 2016 www.awinic.com.cn 3 AW87319 datasheet Dec. 2016 V1.2 FUNCTIONAL DIAGRAM VDD RSTN SCL RSTN BIAS&OT I2C SYSCTRL SW LOW-BAT DETECT BOOST PVDD SDA OVP OSC AD1 BAT SAFE AGC AD AD2 INP VOP Class-K Modulator INPUT BUFFER INN OCP Speaker protection PWM Driver OUTPUT STAGE VON Voltage sensing GND BGND Figure 4 PGND AW87319 functional diagram ABSOLUTE MAXIMUM RATING(Note1) Parameter Range Supply Voltage VDD -0.3V to 6V Input Pin Voltage -0.3V to VDD+0.3V INNINP Boost output voltage PVDD -0.3V to 15V SW -0.3V to PVDD+2V VOP, VON -0.3V to PVDD+0.3V Minimum load resistance RL 5 Package Thermal Resistance JA 60C/W Ambient Temperature Range -40C to 85C Maximum Junction Temperature TJMAX 125C Storage Temperature Range TSTG -65C to 150C Lead TemperatureSoldering 10 Seconds 260C ESD Rating (Note 2) HBMhuman body model 7kV CDMcharge device mode 2kV Latch-up (c) 2016 www.awinic.com.cn 4 AW87319 datasheet Dec. 2016 V1.2 Test ConditionJEDEC STANDARD NO.78B DECEMBER 2008 +IT450mA -IT-450mA Note 1Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Note 2The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. Test method: MIL-STD-883G Method 3015.7 (c) 2016 www.awinic.com.cn 5 AW87319 datasheet Dec. 2016 V1.2 ELECTRICAL CHARACTERISTICS Test conditionTA=25CVDD=3.6VPVDD=8VRL=8+33Hf=1kHzunless otherwise noted Parameter VDD UVP VIH VIL Test conditions Power supply voltage Min Typ 3.3 Max Units 5.5 V Under-voltage protection voltage 2.9 V Under-voltage voltage 150 mV protection RSTN, SCL, SDA, high-level input voltage RSTN, hysteresis AD1, SCL, SDA, AD1, AD2 AD2 low-level input voltage 1.3 VDD V 0 0.35 V 1 A ISD Shutdown current 0.1 TSD Over temperature protection threshold 160 C TSDR Over temperature protection recovery threshold 130 C TON Turn-On time 40 ms TOFF Turn-Off time VDD=3.6VRSTN=0V 150 500 s Boost PVDD The maximum Output voltage VDD=3.3V to 5.5V 8.5 (Note1 V OVP voltage VDD=3.3V to 5.5V 1.1*VPVDD V 400 mV 1.6 MHz Soft-start Switching frequency 0.4 MHz The maximum duty cycle 90% OVP OVP hysteresis voltage Operating Frequency VDD=3.3V to 5.5V F1 DMAX TST Soft-start time No loadCOUT=22F 1 84% Boost converter efficiency VDD=3.6V, RL=8,PO=1W IL_PEAK Inductor peak current limit VDD=3.3V to 5.5V ISHORT Current limit when PVDD short to ground ms Note1 A 4 300 mA Class D VOS Output offset voltage Vin=0VVDD=3.3V to 5.5V -30 0 30 mV VDD=4.2V, Po=2.5W, RL=8+33H, PVDD=8.5V 72 % Speaker Quiescent current VDD=3.6V, input ac grounded, RL=8+33H 14 mA Receiver Quiescent current VDD=3.6V, input ac grounded, RL=8+33H 6 mA VDD=3V to 5.5V 800 kHz 217Hz -70 dB 1kHz -65 dB total efficiencyBoost+Class D Iq Fosc Modulation frequency PSRR Power supply rejection ratio VDD=4.2V Vp-p_sin=200mV (c) 2016 www.awinic.com.cn 6 AW87319 datasheet Dec. 2016 V1.2 SNR Signal-to-noise ratio Parameter VDD=4.2VPVDD=8.5V Po=4.1WRL=8+33H Av=8V/V 102 dB VDD=4.2VPVDD=8.5V Po=0.8WRL=8+33H Av=8V/V 94 dB Test conditions Av=16 V/V Speaker Output noise EN Av=8 V/V Receiver Output noise Av=1 V/V Min Typ 47 Po V 20 (Note1 Speaker gain 24 Receiver gain 0 dB (Note1 Speaker Inner input resistance Av=16 V/V 9 Speaker Inner input resistance Av=8 V/V 18 Receiver Inner input resistance Av=1 V/V 95 Speaker input Cut-off frequency Cin=47nF, Av=16 V/V 376 Speaker input Cut-off frequency Cin=47nF, Av=8 V/V 188 Receiver input Cut-off frequency Cin=47nF, Av=1 V/V 36 Speaker input Cut-off frequency Cin=68nF, Av=16 V/V 260 Speaker input Cut-off frequency Cin=68nF, Av=8 V/V 130 Receiver input Cut-off frequency Cin=68nF, Av=1 V/V 25 Fin THD+N Units 58 20Hz to 20kHz, input ac grounded, A-weighting Av Rini Max k Hz Total harmonic distortion plus noise Speaker Output Power VDD=4.2V, Po=0.6W, RL=8+33H, f=1kHz PVDD=8.5V THD+N=1%RL=8+33H VDD=4.2VPVDD=8.5V IL_PEAK=4A THD+N=10% RL=8+33HVDD=4.2V PVDD=8.5V IL_PEAK=4A THD+N=1%RL=6+33H VDD=4.2VPVDD=8.5V IL_PEAK=4A THD+N=10% RL=6+33HVDD=4.2V PVDD=8.5V IL_PEAK=4A 0.015 % 4.1 W 4.9 W 4.6 W 5.1 W (Note1 V Battery Tracking AGC VBSGD Battery protection threshold voltage VBSGD_HYS Battery protection Hysteresis voltage 3.5 100 mV Triple-Level Triple-Rate AGC (Note1) ms/dB (Note1 ms/dB TAT1 AGC1 Attack Time 0.08 TAT2 AGC2 Attack Time 0.64 (Note1 ms/dB (Note1 ms/dB TAT3 AGC3 Attack Time 41 TRLT Release time 21 AMAX The maximum attenuation gain -13.5 dB Note 1Registers are adjustable; Refer to the list of registers. (c) 2016 www.awinic.com.cn 7 AW87319 datasheet Dec. 2016 V1.2 MEASUREMENT SETUP AW87319 features switching digital output, as shown in Figure 5. Need to connect a low pass filter to VOP/VON output respectively to filter out switch modulation frequency, then measure the differential output of filter to obtain analog output signal. 10nF 500 VOP INP Cin 30kHz Low-Pass Fliter AW87319 VON INN 500 Cin 10nF Figure 5 AW87319 test setup Low pass filter uses resistance and capacitor values listed in Table 1. Rfilter Cfilter Low-pass cutoff frequency 500 10nF 32kHz 1k 4.7nF 34kHz Table 1 AW87319 recommended values for low pass filter Output Power Calculation According to the above test methods, the differential analog output signal is obtained at the output of the low pass filter. The valid values Vo_rms of the differential signal as shown below: Vo_rms Figure 6 Output RMS value The power calculation of Speaker is as follows (c) 2016 www.awinic.com.cn 8 AW87319 datasheet Dec. 2016 V1.2 PL (Vo _ rms) 2 RL RLload impedance of the spea ker TYPICAL CHARACTERISTICS (c) 2016 www.awinic.com.cn 9 AW87319 datasheet Dec. 2016 V1.2 Efficiency vs Po Efficiency vs Po 100 100 PVDD=8.5V VDD=4.2V f=1kHz IL_PEAK=4A 90 80 70 Efficiency( % ) Efficiency( % ) 80 PVDD=8.5V VDD=4.2V f=1kHz IL_PEAK=4A 90 60 50 40 70 60 50 40 30 30 20 20 RL=8+33H 10 RL=6+33H 10 0 0 0 1 2 3 4 0 5 1 2 Po ( W ) 5 2500 PVDD=8.5V VDD=4.2V f=1kHz IL_PEAK=4A 2250 2000 PVDD=8.5V VDD=4.2V f=1kHz IL_PEAK=4A 2250 2000 1750 I_VDD_supply (mA ) 1750 1500 1250 1000 1500 1250 1000 750 750 500 500 RL=6+33H 250 RL=8+33H 250 0 0 0 1 2 3 4 0 5 1 2 Po ( W ) 3 4 5 Po ( W ) Gain vs frequency Po vs Vin 2 36 33 PVDD=8V VDD=3.6V Cin=1F RL=8+33H 30 27 Gain=24dB Gain=18dB 1 PVDD=8V VDD=3.6V f=1kHz RL=8+33H 24 Po (W) Gain (dB ) 4 I_VDD_supply vs Po I_VDD_supply vs Po 2500 I_VDD_supply (mA ) 3 Po ( W ) 21 18 0.5 0.295 1.394 AGC3 on 0.272 1.287 15 0.239 1.13 12 0.21 9 0.992 6 3 0 20 50 100 1K 10K 20K 0.1 0.1 0.5 1 2 Vin ( Vp ) frequency ( Hz ) (c) 2016 www.awinic.com.cn 10 AW87319 datasheet Dec. 2016 V1.2 THD+N vs frequency THD+N vs frequency 10 10 Po=1W PVDD=8.5V Cin=1F RL=8+33H VDD=4.2V VDD=5.5V 1 THD+N (%) THD+N (%) 1 Po=1W PVDD=8.5V Cin=1F RL=6+33H VDD=3.6V 0.1 0.01 VDD=5.5V 0.1 50 100 10K 1K 0.001 20 20K 50 100 10K 1K frequency ( Hz ) 20K frequency ( Hz ) THD+N vs frequency THD+N vs frequency 10 10 Receiver mode VDD=3.6V Cin=1F RL=6+33H Po=10mW Receiver mode VDD=3.6V Cin=1F RL=8+33H Po=100mW 1 THD+N (%) 1 THD+N (%) VDD=4.2V 0.01 0.001 20 0.1 0.01 Po=10mW Po=100mW 0.1 0.01 0.001 20 50 100 10K 1K 20K 0.001 20 50 100 10K 1K frequency ( Hz ) 20K frequency ( Hz ) THD+N vs frequency THD+N vs frequency 100 100 PVDD=8.5V f=1kHz IL_PEAK=4A RL=8+33H PVDD=8.5V f=1kHz IL_PEAK=4A RL=6+33H 10 THD+N (%) 10 THD+N (%) VDD=3.6V VDD=3.6V VDD=4.2V 1 0.1 VDD=3.6V VDD=4.2V 1 0.1 0.01 0.01 0.1 0.2 0.3 0.5 1 2 3 5 0.1 0.2 0.3 0.5 1 2 3 frequency( W ) frequency( W ) (c) 2016 www.awinic.com.cn 11 5 AW87319 datasheet Dec. 2016 V1.2 Start-up sequence Shuntdown sequence SDA SDA VOP&VON VOP&VON 10ms/div 50us/div Triple-Level Triple-Rate AGC Release Timing Triple-Level Triple-Rate AGC Attack Timing Vin Vin VOP-VON VOP-VON 100ms/div 20ms/div PSRR vs frequency 0 -10 PVDD=8V VDD=3.6V Cin=1F RL=8+33H -20 VDD=3.6V VDD=4.2V VDD=5.5V PSRR (dB) -30 -40 -50 -60 -70 -80 -90 20 100 1K 10K 20K frequency ( Hz ) (c) 2016 www.awinic.com.cn 12 AW87319 datasheet Dec. 2016 V1.2 DETAILED FUNCTIONAL DESCRIPTION AW87319 is specifically designed to improve the musical output dynamic range, enhance the overall sound quality, which is a new high efficiency, low noise, constant large volume, 2nd Smart K audio amplifiers. AW87319 integrates the high-voltage synchronous Boost with efficiency up to 84% as the Class D power stage supply. It significantly improves the output dynamic range of music. AW87319 integrates Awinic's proprietary Triple-Level Triple-Rate AGC audio algorithm, effectively eliminating music noise and improving sound quality and volume. AW87319 noise floor is as low as to 47uV, with 102dB high signal-to-noise-ratio (SNR). The ultra-low distortion 0.015% and unique Triple-Level Triple-Rate AGC technology bring high quality music enjoyment. AW87319 supports speaker and receiver 2-in-1 applications. In the receiver application, Class D power stage voltage is straightly supplied by battery. AW87319 controls internal registers through the I2C interface. Register parameters include Boost Output Voltage, Boost maximum input peak current, Class D gain, Triple-Level Triple-Rate AGC parameters. AW87319 built-in over current protection, over-temperature protection and short circuit protection function, effectively protect the chip. AW87319 uses small 2.76mm*2.36mm CSP-19 package. CONSTANT OUTPUT POWER In the mobile phone audio applications, the AGC function to promote music volume and quality is very attractive, but as the lithium battery voltage drops, general power amplifier output power will reduce gradually. So, it is hard to provide high quality music within the battery voltage range. AW87319 uses unique Triple-Level Triple-Rate technology, within lithium battery voltage range (3.3V~ 4.35V), to guarantee that output power is constant, and the output power will not drop along with the decrease of lithium battery voltage. Even if the battery voltage drops, AW87319 can still provide high quality large volume music enjoyment. The output power of AW87319 can be configured from 0.5W to 1.5W via I2C matching general speakers. Unique Triple-Level Triple-Rate AGC technology can bring high-quality music enjoyment. Triple-Level Triple-Rate AGC technology Awinic proprietary Triple-Level Triple-Rate AGC technology is designed for the protection of the high voltage power amplifier, which is divided into AGC1, AGC2 and AGC3 power levels, to obtain a large volume while maintaining excellent sound quality. In practical applications, speaker can continuously work long hours at rated power, and also can work short-term at high power. For example, in the standard reliability of the loudspeaker experiment, the powder of peak power reached around four times of the rated power. For achieving larger volume and better sound quality, speakers need to work at high power for short periods of time, in order to improve the performance of the speaker. AW87319 Triple-Level Triple-Rate AGC technology can fit the speaker better. AGC1 prevents output signal clipping by detecting output voltage in a very short time after clipping, which can effectively restrain the noise clipping; AGC2 can improve the dynamic range of the music in a relatively short period of time; AGC3 can make the speaker work under rated power, which can effectively improve the volume and protect the speaker. Triple-Level Triple-Rate AGC can obtain more excellent overall performance. Triple-Level Triple-Rate AGC detects the peak output voltage of the power amplifier, when the output peak voltage is higher than the compression threshold voltage, the amplifier gain decreases in 0.5dB step. When the output peak voltage is lower than the release threshold voltage, the amplifier gain is recovery to the initial gain in 0.5dB step. The detailed process can be described as follows: (c) 2016 www.awinic.com.cn 13 AW87319 datasheet Dec. 2016 V1.2 Vin AGC1 Compression threshold voltage Vth_at1 Vth_at2 Vth_at3 Vth_rt AGC2 Compression threshold voltage AGC3 Compression threshold voltage The release threshold voltage Vout Gain A B C AGC1 compression AGC2 compression Figure 7 A: B: C: D: E: F: G: D E AGC3 compression F hold G H release Triple-Level Triple-Rate AGC Operation Principle The output voltage is lower than threshold voltage Vth_at3, AGC don't work. Input voltage becomes large. It leads to the output voltage clipping, AGC1 starts work, the attack time is set through the I2C register 0x09h [2:1], when the output voltage is higher than Vth_at1, and gain register began to decrease. Gain decreases when the output signal passes through the zero. It eliminates the clipping noise as soon as possible. When the output voltage is not clipping and higher than threshold voltage Vth_at2, AGC2 starts work, the attack time is set through the I2C register 0x08h [4:2], gain register begins to decrease at a certain rate. Gain register began to decrease. Gain decreases when the output signal passes through the zero. The output voltage gradually decreases to below the AGC2 attack threshold voltage Vth_at2, which can protect the speaker and enhance the sound. When the output voltage is lower than the AGC2 attack threshold voltage Vth_at2 and higher than the AGC3 attack threshold voltage Vth_at3, AGC3 starts work, the attack time is set through the I2C register 0x07h [4:2], and gain register began to decrease at a certain rate. Gain decreases when the output signal passes through the zero, so the output voltage gradually decreases to below the AGC3 attack threshold voltage Vth_at3. Attack time ends, Amplifier output power is close to the speaker rated power. Input voltage decreases, the output voltage becomes lower than the release threshold voltage Vth_rt, at this point, gain remains the same in the maintain time (10 ms~20 ms). Gain increases When the time of output voltage lower than the release threshold voltage Vth_rt is (c) 2016 www.awinic.com.cn 14 AW87319 datasheet Dec. 2016 V1.2 longer than the holding time. The release time can be set through I2C register 0x07h [7:5]. H: Stop release when the output signal is larger than the release threshold or the gain is equal to the initial value. The output voltage remains constant. Triple-Level Triple-Rate AGC can switch independently according to different application requirements. Such as close AGC1 and AGC2, retain only AGC3, this is the single-AGC mode, similar to AW8736(AGC3 attack time is set to 1.28ms/dB; release time is set to 41ms/dB); Close AGC2, open AGC1 and AGC3this is Multi_level AGC. It can be set similar to AW8738 (AGC1 attack time is set to 80us/dB; AGC3 attack time is set to 0.64ms/dB; release time is set to 10.24ms/dB). Zero-Crossing Adjustment Technology Traditional AGC doesn't contain zero adjustment technology; AGC gain changes generally at the peak, the gain variation at the peak would generate a certain transient distortion, such distortions are audibly imperceptible. no zero-crossing adjustment Figure 8 zero-crossing adjustment Zero-adjust Comparison As shown above, when there is no zero-adjustment technology, it can be seen the obvious step change at the peak of large signal, the steps sound slightly perceived in special audio. Gain changes at zero. The steps disappear by using zero-crossing detection technology. Using zero detection technology can make the music pure and natural. Low-voltage protection AGC technology Mobile phone battery voltage will decrease in use, but the current will increase. When the battery voltage is low, high current maybe cause the battery protection or mobile phone automatically shut down. Awinic proprietary low voltage protection AGC technology can solve the problems, to prevent high current when the battery voltage is too low. AW87319 is built-in low voltage protection AGC technology to real-time detection the battery voltage. Gain decreases rapidly when the battery voltage is below the safety threshold, so as to decrease the output voltage and the power supply current, which effectively prevents high current. (c) 2016 www.awinic.com.cn 15 AW87319 datasheet Dec. 2016 V1.2 Maximum output amplitude(Vp) Low-voltage protection Unprotected(V) Protection limit(V) Lower limit protection(V) The battery voltage(V) Figure 11 Low voltage protection The protection safety threshold voltage is set to 3.5 V~3.6 V through the I2C register 0x02h [4:3]. The maximum protection output voltage is set to 5Vp ~ 6.5Vp through I2C register 0x02h [1:0]. Only when the register 0x02h [2] is set to 1, low voltage protection AGC technology is enabled. Synchronous Boost technology AW87319 integrated peak current mode synchronous PWM Boost as Class D power stage supply, significantly increase the output voltage dynamic range. Reduces the size of external components and saves PCB space by using 1.6 MHz switching frequency. Boost output voltage can be set through the I2C register 0x03h [2:0]; Boost current limit can be set through register 0x04h [2:0]. AW87319 synchronous Boost with soft-start function to prevent overshoot current at powering-on; integrated the output protection circuit and self-recovery function; integrated Anti-Ring circuit to reduce EMI in DCM mode; built-in substrate switching shutdown circuit, effectively preventing the input and output leakage current anti-irrigation. 2-in-1 application AW87319 is easy to realize the speaker and receiver 2-in-1 application, better save cost and board space. AW87319 can set the gain through the I2C register 0x05h [3:0]. The typical value of input capacitance is a 47nF, gain is 16V/V in default in speaker mode; the cutoff frequency is 376Hz; the gain is 1V/V in default in receiver mode; the noise is 20V; the cutoff frequency is 36Hz. Realize 2-in-1 application without changing any hardware. Class D power stage voltage is straightly supplied by battery in receiver mode. RNS (RF TDD Noise Suppression) GSM radios transmit using time-division multiple access with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers. In RF applications, improvements to both layout and component selection decrease the AW87319's susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Minimizing the trace length prevents them from functioning as antennas and coupling RF signals into the AW87319. Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors so as to exhibit the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to (c) 2016 www.awinic.com.cn 16 AW87319 datasheet Dec. 2016 V1.2 20pF capacitors typically exhibit self resonance at RF frequencies. These capacitors, when placed at the input pins, can effectively shunt the RF noise at the inputs of the AW87319. For these capacitors to be effective, they must have a low-impedance and low-inductance path to the ground plane. Some RF energy will couple onto audio traces regardless of the effort to prevent this phenomenon from occurring, form audible TDD Noise. The AW87319 features a unique RNS technology, which effectively reduces RF energy, attenuate the RF TDD-noise, an acceptable audible level to the customer. VDD Cin INP VOP INN AW87319VON Rin GND Figure 10 RF Radiation coupling schematic diagram Filter-Free Modulation Scheme The AW87319 features a filter-free PWM architecture that reduces the LC filter of the traditional Class-D amplifier, increasing efficiency, reducing board area consumption and system cost. EEE The AW87319 features a unique Enhanced Emission Elimination (EEE) technology, that controls fast transition on the output, greatly reduces EMI over the full bandwidth. Pop-Click Suppression The AW87319 features unique timing control circuit, that comprehensively suppresses pop-click noise, eliminates audible transients on shutdown, wakeup, and power-up/down. Over temperature protection AW87319 has automatic temperature detection mechanism. When the chip operates in a fault condition, the chip temperature is too high, up to a preset temperature protection temperature threshold (160C), the system starts overheating protection, the chip powered off. AW87319 restarts to resume normal work when the chip temperature returns to normal operating range (less than 130C). Protection Function When a short occurs between VOP/VON pin and VDD/GND or VOP and VON, the device will shut down, preventing the device from being damaged. AW87319 can automatically recover when the condition is (c) 2016 www.awinic.com.cn 17 AW87319 datasheet Dec. 2016 V1.2 removed. The device shuts down when the junction temperature is high. The device returns to normal operation when the temperature decreases to safe levels. I2C Timing feature Parameter MIN Name TYP MAX UNIT 400 kHz No. Sym 1 fSCL SCL Clock frequency 2 tLOW SCL Low level Duration 0.6 s 3 tHIGH SCL High level Duration 1.3 s 4 tRISE SCL, SDA rise time 0.3 s 5 tFALL SCL, SDA fall time 0.3 s 6 tSU:STA Setup time SCL to START state 0.6 s 7 tHD:STA START state to STL holding time 0.6 s 8 tSU:STO Setup time SCL to STOP state 0.6 s 9 tBUF the Bus idle time START state to STOP state 1.3 s 10 tSU:DAT SDA to SCL setup time 0.1 s 11 tHD:DAT SCL to SDA hold time 10 ns (3) (2) tHIGH tLOW tRISE tFALL (4) (5) SCL tSU:DAT tHD:DAT (10) (11) SDA Figure 11 SCL and SDA timing relationships in the data transmission process SCL tHD:STA tSU:STO (7) (8) (6) (9) tSU:STA tBUF SDA Figure 12 The timing relationship between START and STOP state General I2C Operation The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The device is addressed by a unique 7-bit address; the same device can send and receive data. In addition, Communications equipment has distinguish master from slave device: In the communication process, only the master device can initiate a transfer and terminate data and generate a corresponding clock signal. The devices using the address access during transmission can be seen as a slave device. SDA and SCL connect to the power supply through the current source or pull-up resistor. SDA and SCL default is a high level. There is no limit on the number of bytes that can be transmitted between start and (c) 2016 www.awinic.com.cn 18 AW87319 datasheet Dec. 2016 V1.2 stop conditions. When the last word transfers, the master generates a stop condition to release the bus. START stateThe SCL maintain a high level, SDA from high to low level STOP stateThe SCL maintain a high level, SDA pulled low to high level Start and Stop states can be only generated by the master device. In addition, if the device does not produce STOP state after the data transmission is completed, instead re-generate a START state (Repeated START, Sr), and it is believed that this bus is still in the process of data transmission. Functionally, Sr state and START state is the same. As shown in figure 13. SCL START (S) STOP (P) SDA Figure 13 START and STOP state generation process In the data transmission process, when the clock line SCL maintains a high level, the data line SDA must remain the same. Only when the SCL maintain a low level, the data line SDA can be changed, as shown in figure 14. Each transmission of information on the SDA is 9 bits as a unit. The first eight bits are the data to be transmitted, and the first one is the most significant bit (Most Significant Bit, MSB), the ninth bit is an confirmation bit (Acknowledge, ACK or A ), as shown in figure 15. When the SDA transmits a low level in ninth clock pulse, it means the acknowledgment bit is 1, namely the current transmission of 8 bits data are confirmed, otherwise it means that the data transmission has not been confirmed. Any amount of data can be transferred between START and STOP state. SCL SDA Data cable Remains the same: At this point the data is valid Figure 14 Data transmission: In this case the data is invalid The data transfer rules on the I2C bus The whole process of actual data transmission is shown in figure 15. When generating a START condition, the master device sends an 8-bit data, including a 7-bit slave addresses (Slave Address), and followed by a "read / write" flag ( R/W ). The flag is used to specify the direction of transmission of subsequent data. The master device will produce the STOP state to end the process after the data transmission is completed. However, if the master device intends to continue data transmission, you can directly send a Repeated START state, without the need to use the STOP state to end transmission. (c) 2016 www.awinic.com.cn 19 AW87319 datasheet Dec. 2016 V1.2 SCL START or repeated START (S or Sr) 1 2 8 9 1 R/W ACK MSB 2 8 9 STOP or Repeated START (P or Sr) SDA MSB ACK Data transmission on the I2C bus Figure 15 I2C Read/Write Processes The following describes two kinds of ways of the I2C bus data transmission: Write Process Writing process refers to the master device write data into the slave device. In this process, the transfer direction of the data is always unchanged from the master device to the slave device. All acknowledge bits are transferred by the slave device, in particular, AW87319 as the slave device, the transmission process in accordance with the following steps, as shown in figure 16: Master device generates START state. The START state is produced by pulling the data line SDA to a low level when the clock SCL signal is a high level. Master device transmits the 7-bits device address of the slave device, followed by the "read / write" flag (flag R/W = 0); The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is correct; The master device transmits the 8-bit AW87319 register address to which the first data byte will written The slave device asserts an acknowledgment (ACK) bit to confirm the register address is correct; Master sends 8 bits of data to register which needs to be written; The slave device asserts an acknowledgment bit (ACK) to confirm whether the data is sent successfully; If the master device needs to continue transmitting data by sending another pair of data bytes, just need to repeat the sequence from step 6. In the latter case, the targeted register address will have been auto-incremented by the AW87319. The master device generates the STOP state to end the data transmission. (1) START (2) slave device address R/W (3) (4) A Register address `0'(write) data transmission direction (5) (6) (7) (6r) (7r) A write data A write data A (9) STOP Data Transmission: 8 + 1 bit data acknowledge bit (ACK) Register address auto increment - (8) From the master to the slave device From slave to master device Figure 16 Writing process (data transmission direction remains the same) Read Process Reading process refers to the slave device reading data back to the master device. In this process, the direction of data transmission will change. Before and after the change, the master device sends START state and slave address twice, and sends the opposite "read/write" flag. In particular, AW87319 as the slave device, the transmission process carried out by following steps listed in figure 17: Master device asserts a start condition; Master device transmits the 7 bits address of AW87319, and followed by a "read / write" flag ( R/W = 0); (c) 2016 www.awinic.com.cn 20 AW87319 datasheet Dec. 2016 V1.2 The slave device asserts an acknowledgment bit (ACK) to confirm whether the device address is correct; The master device transmits the AW87319 register address to make sure where the first data byte will read; The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is correct or not; The master device restarts the data transfer process by continuously generating STOP state and START state or a separate Repeated START; Master sends 7-bits address of the slave device and followed by a read / write flag (flag R/W = 1) again; The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is correct or not; Master transmits 8 bits of data to register which needs to be read; The slave device sends an acknowledgment bit (ACK) to confirm whether the data is sent successfully; AW87319 automatically increment register address once after sent each acknowledge bit (ACK), The master device generates the STOP state to end the data transmission. (1) (2) START slave device address R/W (3) (4) (5) (6) A Register address A Sr (7) slave device address `0'(write) data transmission direction From the master to the slave device From slave to master device Figure 17 (8) R/W A (9) (10) Read data A (9r) (10r) Read data A (12) STOP `1'(read) Data Transmission: 8 + 1 bit data acknowledge bit (ACK) Sr = repeated START or Send STOP state before sending START state Register address auto increment - (11) Reading process (data transmission direction remains the same) (c) 2016 www.awinic.com.cn 21 AW87319 datasheet Dec. 2016 V1.2 Register List addr ess 0x00 0x01 0x02 0x03 0x04 0x05 0x06 name Chip ID SYSCTRL BATSAFE BOV(4) BP Gain AGC3_Po AGC3 AGC2 AGC1 (1) (2) (3) (4) (5) Bit7 Bit6 Bit5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 AGC3_R 0x07 AGC3_RT[2] AGC3_RT[0] T[1] AGC2_P 0x08 AGC2_Po[2] AGC2_Po[0] o[1] 0x09 0 0 0 BSTV: Battery_Safeguard_Threshold_Voltage EN_SS: EN_Software_Safeguard BSMOL: Battery_Safeguard_Max_Output_Level BOV: Boost_Output_Voltage BMCPC: Boost_Maxim_Coil_Peak_Current Bit4 Bit3 Bit2 Bit1 Bit0 1 0 BSTV(1)[1] 0 0 0 0 1 0 BSTV(1)[0] 0 0 Gain[3] AGC3_Po[3] 0 EN_SW EN_SS (2) 1 BMCPC(5)[2] Gain[2] AGC3_Po[2] 1 EN_ClassD BSMOL(3)[1] BOV(4)[1] BMCPC(5)[1] Gain[1] AGC3_Po[1] 1 EN_Boost BSMOL(3)[0] BOV(4)[0] BMCPC(5)[0] Gain[0] AGC3_Po[0] AGC3_AT[2] AGC3_AT[1] AGC3_AT[0] 1 0 AGC2_AT[2] AGC2_AT[1] AGC2_AT[0] 0 0 0 0 AGC1_AT[1] AGC1_AT[0] PD_AGC1 1 0 0 0 0 0 0 register 0x00 0x01 0x02 0x03 0x04 Default 0x9B 0x03 0x28 0x05 0x04 0x05 0x06 0x07 0x08 0x09 0x03 0x52 0x28 0x02 0x02 (EN_Boost=0) 0x0D (EN_Boost=1) Table 2. AW87319 Register Default value Any register address which is more than 0x09 and all reserved bits are reserved for debugging and testing purposes. Changing their values may affect the normal function of the power amplifier; Reading them will get any possible values. AW87319's I2C address is 10110A2A1, which, in order to avoid conflict with other I2C devices address, you can pull up or pull-down AW87319 of AD2 and AD1 pins to set the value of A2 and A1, respectively. The following lists specific information about all visible registers, including default values and programmable ranges. CHIP ID Register (address: 0x00) 2 I C Bit Name R/W Default 7:0 IDCODE R 0x9B Description Chip ID will be returned after reading. All configuration registers will be reset to default values after 0xAA is written. SYSTEM CONTROL (SYSCTRL) Register (address: 0x01) I2C Bit 7:3 Name -- R/W -- Default 0000 0 2 EN_SW R/W 0 1 EN_ClassD R/W 1 0 EN_Boost R/W 1 Description Reserved and Unused Chip Software Enable 0: Chip Software Disable: Shutdown the whole chip except BIAS and OSC. 1: Chip Software Enable Class D Enable 0: Class D Disable 1: Class D Enable Boost Enable: This bit must be unchanged when EN_SW=1. 0: Boost Disable 1: Boost Enable (c) 2016 www.awinic.com.cn 22 AW87319 datasheet Dec. 2016 V1.2 BATTERY SAFEGUARDS (BATSAFE) Register (address: 0x02) I2C Bit 7:5 Name -- R/W -- Default 001 4:3 Battery_Safeguard_ Threshold_Voltage R/W 01 2 EN_Software_Safeguard R/W 0 1:0 Battery_Safeguard_Max_ Output_Level R/W 00 Description Reserved and Unused Setting Battery Threshold Voltage for Triggering Battery Safeguard Mode: When EN_Boost=0, these bits are fixed in `00'. 00: On-Chip Threshold Detect Disable: Use off-chip signal to control mode switch. 01: Threshold Voltage is 3.50V 10: Threshold Voltage is 3.55V 11: Threshold Voltage is 3.60V Battery Safeguard Mode Software Enable 0: Battery Safeguard Mode Software Disable 1: Battery Safeguard Mode Software Enable Setting Maximum Output Level when Battery Safeguard Mode Triggered 00: 5.5Vp 01: 5.0Vp 10: 6.0Vp 11: 6.5Vp BOOST OUTPUT VOLTAGE (BOV) Register (address: 0x03) 2 I C Bit 7:3 Name -- R/W -- Default 0000 0 2:0 Boost_Output_Voltage R/W 101 Description Reserved and Unused Setting Boost Output Voltage 111: 8.5V 110: 8.25V 101: 8.0V 100: 7.75V 0XX: Unavailable BOOST PARAMETER (BP) Register (address: 0x04) 2 I C Bit 7:3 Name -- R/W -- Default 0000 0 2:0 Boost_Max_Coil_Peak_Current R/W 100 Description Reserved and Unused Setting Boost Max Inductor Peak Current 000: 1.50A 001: 2.00A 010: 2.50A 011: 3.00A 100: 3.25A 101: 3.50A 110: 3.75A 111: 4.00A (c) 2016 www.awinic.com.cn 23 AW87319 datasheet Dec. 2016 V1.2 CLASS D GAIN (Gain) Register (address: 0x05) For EN_Boost=0 (Receiver Mode): I2C Bit 7:4 Name -- R/W -- Default 0000 3:0 Class_D_Gain R/W 0010 Description Reserved and Unused Setting Class D Amplifying Gain 0000: -3.0dB Rini=134k 0001: -1.5dB Rini=113k 0010: 0.0dB Rini=95k 0011: 1.5dB Rini=80k 0100: 3.0dB Rini=67k 0101: 4.5dB Rini=57k 0110: 6.0dB Rini=47k 0111: 7.5dB Rini=40k 1000: 9.0dB Rini=34k 1XXX (XXX000): Unavailable For EN_Boost=1 (Boost Mode): I2C Bit 7:4 Name -- R/W -- Default 0000 3:0 Class_D_Gain R/W 1101 Description Reserved and Unused Setting Class D Amplifying Gain 0XXX: Unavailable 1000: Unavailable 1001: 18.0dB Rini=18k 1010: 19.5dB Rini=15k 1011: 21.0dB Rini=13k 1100: 22.5dB Rini=11k 1101: 24.0dB Rini=9k 1110: 25.5dB Rini=8k 1111: 27.0dB Rini=6.5k CLASS D AGC3 OUTPUT POWER (AGC3_Po) Register (address: 0x06) I2C Bit 7:4 Name -- R/W -- Default 0000 3:0 AGC3_Output_Power R/W 0011 Description Reserved and Unused Setting AGC3 Output Power for Protecting Speaker 0000: 0.5W@8 0.67W@6 0001: 0.6W@8 0.80W@6 0010: 0.7W@8 0.93W@6 0011: 0.8W@8 1.07W@6 0100: 0.9W@8 1.20W@6 0101:1.0W@8 1.33W@6 0110: 1.1W@8 1.47W@6 0111: 1.2W@8 1.60W@6 1000: 1.3W@8 1.73W@6 1001: 1.4W@8 1.87W@6 1010: 1.5W@8 2.00W@6 1011: AGC3 Disable 1100~1111: Unavailable (c) 2016 www.awinic.com.cn 24 AW87319 datasheet Dec. 2016 V1.2 CLASS D AGC3 PARAMETER (AGC3) Register (address: 0x07) I2C Bit Name R/W Default 7:5 AGC3_Release_Time R/W 010 4:2 AGC3_Attack_Time R/W 100 1:0 - - 10 Description Setting Release Time of AGC3: 000: 5.12ms/dB 001: 10.24ms/dB 010: 21 ms/dB 011: 41 ms/dB 100: 82 ms/dB 101: 164 ms/dB 110: 328 ms/dB 111: Unavailable Setting Attack Time of AGC3: 000: 0.64ms/dB 001: 1.28ms/dB 010: 2.56ms/dB 011: 10.24ms/dB 100: 41ms/dB 101~111: Unavailable Reserved and Unused CLASS D AGC2 PARAMETER (AGC2) Register (address: 0x08) I2C Bit Name R/W Default 7:5 AGC2_Output_Power R/W 001 4:2 AGC2_Attack_Time R/W 010 1:0 -- -- 00 Description Setting AGC2 Output Power: 000: 1.2W@8 1.6W@6 001: 1.5W@8 2.0W@6 010: 1.8W@8 2.4W@6 011: 2.1W@8 2.8W@6 100: 2.4W@8 3.2W@6 101: AGC2 Disable 110~111: Unavailable Setting Attack Time of AGC2: 000: 0.16ms/dB 001: 0.32ms/ dB 010: 0.64ms/dB 011: 2.56ms/dB 100: 10.24ms/dB 101: 41ms/dB 110~111: Unavailable Reserved and Unused CLASS D AGC1 PARAMETER (AGC1) Register (address: 0x09) I2C Bit 7:3 Name -- R/W -- Default 0000 2:1 Fastest_Level_AGC_Attack_Time R/W 01 0 PD_Fastest_Level_AGC R/W 0 Description Reserved and Unused Setting Fastest Level AGC Attack Time: 00: 0.04ms/dB 01: 0.08ms/dB 10: 0.16ms/dB 11: 0.32ms/dB Fastest Level AGC Disable: 0: Fastest Level AGC Enable 1: Fastest Level AGC Disable (c) 2016 www.awinic.com.cn 25 AW87319 datasheet Dec. 2016 V1.2 APPLICATION INFORMATION Boost Inductor Selection Selecting inductor needs to consider Inductance, size, magnetic shielding, saturation current and temperature current. a) Inductance Inductance value is limited by the boost converter's internal loop compensation. In order to ensure phase margin sufficient under all operating conditions, recommended 1H inductor. b) Size For a certain value of inductor, the smaller the size, the greater the parasitic series resistance of the inductor DCR, the higher the loss, corresponds to the lower efficiency. c) Magnetic shielding Magnetic shielding can effectively prevent the inductance of the electromagnetic radiation interference. It is much better to choose inductance with magnetic shielding in the application of EMI sensitive environment. d) Saturation current and temperature rise of current Inductor saturation current and temperature rise current value are important basis for selecting the inductor. As the inductor current increases, on the one hand, since the magnetic core begins to saturate, inductance value will decline; on the other hand, the inductor's parasitic resistance inductance and magnetic core loss can lead to temperature rise. In general, the current value is defined as the saturation current ISAT when the inductance value drops to 70%; the current value is defined as temperature rise current IRMS when inductance temperature rise 40. For particular applications, need to calculate the maximum IL_PEAK and IL_RMS, which is a basis of selecting the inductor. When VDD = 4.2V, PVDD=8.5V, RL = 8amplifier RDSON = 250m, when THD = 1% (the maximum power without distortion), the output power is calculated as follows: 2 POUT RL VOUT RL 2 RDSON 2 RL 1 2.3% 2 8 8.5 8 2 0 . 25 W 4.1W 2 8 0.977 Where the coefficients in the denominator of (0.977) is the power ratio of no truncation maximum output (the power at THD = 1%). In such a large output power, the overall efficiency of the power amplifier is typically 68%, in order to calculate the maximum average current IMAX_AVG_VDD and maximum peak current IMAX_PEAK_VDD drawn from VDD: I MAX _ AVG _ VDD POUT 4.1 A 1.436A VDD 4.2 0.68 I MAX _ PEAK _ VDD 2 I MAX _ AVG _ VDD 2 1.436A 2.872A If inductor DCR is 50m, then when the output power of 4.1W, the inductor power loss is: 2 2 PDCR,LOSS 1.5 I MAX _ AVG _ VDD DCR 1.5 1.436 0.05W 155mW Wherein the coefficient 1.5 is the square of the ratio of the sine wave current RMS value and average value (there is no consideration of the impact of the inductor ripple, the actual DCR loss will be even greater). If the loss which is resulting from DCR is less than 1% at maximum efficiency (POUT = 2.5W, = (c) 2016 www.awinic.com.cn 26 AW87319 datasheet Dec. 2016 V1.2 72%), then: I AVG _ VDD DCR POUT 2.5 A 0.827A VDD 4.2 0.72 PDCR, LOSS 1.5 I 2 AVG _ VDD 0.01 POUT 1.5 I 2 AVG _ VDD 0.01 2.5 34m 1.5 0.827 2 0.72 According to the working principle of the Boost, we can calculate the size of the inductor current ripple IL: I L VIN VOUT VIN . . . A .A VOUT f L . . Thus, the maximum peak inductor current IL_PEAK and maximum effective inductor current IL_RMS is: I L _ PEAK I MAX _ PEAK _ VDD I L . . A .A I L_RMS I MAX _ PEAK _ VDD I L . . A .A From the above calculation results: 1) For typical DCR about 50m inductance, the efficiency loss caused by around1.5%; 2) Need to choose AW87319 inductance input current limit value ILIMIT is greater than IL_PEAK = 3.54 A (< ILIMIT = 4A), to guarantee the amplifier output power can be achieved when THD = 1% (= 4.1W) but not limited by value ILIMIT; 3) In practice, the maximum output power of the amplifier is likely to reach 4.1W in an instant, so the selected inductor saturation current ISAT requires more than the maximum inductor peak current IL_PEAK, and cannot be less than 3.6A; 4) In some cases, if the IL_PEAK calculated according to the above method is greater than the set of input inductor current limit value ILIMIT, shows the power amplifier is restricted by inductance input current limit, the actual maximum output power is less than the calculated value, the measured value shall prevail, and ISAT need greater than the set current limiting value ILIMIT, and cannot be less than 3.6A; 5) Take PVDD = 8.5V for example, under different conditions, the typical method of selecting I SAT in the following table: VDD (V) PVDD (V) RL () ILIMIT (A) Efficiency() (%) PO@THD=1% (W) 4.2 8.5 8 4 68 4.1 (4.1) 3.6 8.5 8 4 60 3.6 (4.1) 4.2 8.5 6 4 67 4.7 (5.3) 3.6 8.5 6 4 60 3.7 (5.3) note1 note1 note1 note1 IL_PEAK (A) Inductor saturation current ISAT minimum value (A) 3.54 3.6 4.44 4.0 4.40 4.0 5.51 4.0 note2 (c) 2016 www.awinic.com.cn 27 AW87319 datasheet Dec. 2016 V1.2 Note 1: The values in parentheses are calculated PO @ THD = 1% when there is no "inductor input current limit" Note 2: IL_PEAK is in parentheses in the "note 1" for power and actual efficiency calculated, if its value is greater than ILIMIT, then triggers the inductance input current limit. 6) As the result of the action of TLTR-AGCamplifier will not work long hours at maximum power without distortion (4.1W), the actual average inductor current is far less than the maximum inductor current effective IL_RMS, so when selecting the inductor, the inductor temperature rise current is not usually a limiting factor; 7) Inductor Selection example: Sunlord WPN252012H1R0MT inductance. The inductor package size is 252012, inductance value is 1H, DCR Typical value is 48m, the typical saturation current ISAT is 4.2A, the typical temperature rise current IRMS is 3.4A, suitable for VDD=3.6V, PVDD=8.5 V, speaker impedance RL=8, inductor input current limit ILIMIT= 4A. If you choose ISAT or IRMS of the inductance is too small, it is possible to cause the chip don't work properly, or the temperature of the inductance is too high. Model Inductance value producer size WPN252012H1R0MT 1uH Sunlord 2.5x2.0x1.2mm DCR ISATA IRMSA 0.054 4.2 3.4 (c) 2016 www.awinic.com.cn 28 AW87319 datasheet Dec. 2016 V1.2 Boost capacitor Selection Boost output capacitor is usually within the range 0.1uF~47uF. It needs to use Class II type (EIA) multilayer ceramic capacitors (MLCC). Its internal dielectric is ferroelectric material (typically BaTiO 3), a high the dielectric constant in order to achieve smaller size, but at the same Class II type (EIA) multilayer ceramic capacitors has poor temperature stability and voltage stability as compared to the Class I type (EIA) capacitance. Capacitor is selected based on the requirements of temperature stability and voltage stability, considering the capacitance material, capacitor voltage, and capacitor size and capacitance values. A) temperature stability Class II capacitance have different temperature stability in different materials, usually choose X5R type in order to ensure enough temperature stability, and X7R type capacitance has better properties, the price is relatively more expensive; X5R capacitance change within 15% in temperature range of 55C to 85C, X7R capacitance change within 15% in temperature range of -55C~125C. The Boost output capacitance of AW87319 recommends X5R ceramic capacitors. B) Voltage Stability Class II type capacitor has poor voltage stability Capacitance values falling fast along with the DC bias voltage applied across the capacitor increasing. The rate of decline is related to capacitance material, capacitors rated voltage, capacitance volume. Take for TDK C series X5R for example, its pressure voltage value is 16V or 25V; the package size is 0805, 1206 or 0603, the capacitance value is 10uF. The capacitor's voltage stability of different types of capacitor is as shown below: Capacitor Variation v.s. DC Voltage 10 0603,X5R,16V,10uF,0.80mm 0603,X5R,25V,10uF,0.80mm 0805,X5R,16V,10uF,0.85mm 0805,X5R,16V,10uF,1.25mm 0805,X5R,25V,10uF,0.85mm 0805,X5R,25V,10uF,1.25mm 1206,X5R,16V,10uF,0.85mm 1206,X5R,16V,10uF,1.60mm 1206,X5R,25V,10uF,0.85mm 1206,X5R,25V,10uF,1.60mm 0 -10 C-Change (%) -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 VDC (V) Figure 18 Different types of capacitive voltage stability Among them, the space remaining value of different types of capacitors at VDC = 8.5 V as shown in the (c) 2016 www.awinic.com.cn 29 AW87319 datasheet Dec. 2016 V1.2 figure 19: Cap@VDC=8.5V 9 7.68uF 6.47uF 6.35uF VDC=8.5V 2.84uF 2.70uF 1206,X5R,25V,10uF,1.60mm 1206,X5R,25V,10uF,0.85mm 1206,X5R,16V,10uF,1.60mm 1206,X5R,16V,10uF,0.85mm 0805,X5R,25V,10uF,1.25mm 0805,X5R,25V,10uF,0.85mm 0805,X5R,16V,10uF,1.25mm 0805,X5R,16V,10uF,0.85mm 0603,X5R,25V,10uF,0.80mm 0603,X5R,16V,10uF,0.80mm 2.34uF 2.20uF 1.93uF 1.74uF 1.72uF 8 0 1 Figure 19 2 3 4 5 6 C (uF) 7 8 9 10 The space remaining value of different types of capacitors at VDC = 8.5 V It can be found that the rate of capacitance capacity value descent becomes slow along with "large capacitor size, capacitance pressure voltage rise". The larger the package size, the better voltage stability. the higher the height, the better voltage stability with the same length and width of the capacitance. Voltage stability of smaller package size (0603) capacitor change affected by the pressure value is very small. In AW87319 typical applications, it is necessary to ensure the output value of the capacitor Boost5uF when PVDD=8.5V. Take the above TDK capacitor for example; recommend the following capacitance combination as the Boost of the output capacitor: model value material size (mm3) rated voltage (V) quantity value@8.5V C1608X5R1C106M080AB 10uF X5R 1.60x0.80x0.80 (0603) 16 3 5.1uF C1608X5R1E106M080AC 10uF X5R 1.60x0.80x0.80 (0603) 25 3 5.2uF C2012X5R1E106M125AB 10uF X5R 2.00x1.25x1.25 (0805) 25 2 5.4uF C3216X5R1C106M160AA 10uF X5R 3.20x1.60x1.60 (1206) 16 1 6.4uF C3216X5R1E106M085AC 10uF X5R 3.20x1.60x0.85 (1206) 25 1 6.5uF Notice that the analysis is only for TDK capacitors, when elected other manufacturers' capacitance, it still need to determine the type and quantity of the capacitors through the capacitor voltage stability data provided by the manufacturer. Different manufacturer's approximate specifications of the capacitor may still have some difference. Construing a different circumstance needs deducting in a different approach. Input Capacitor-Cininput high-pass cutoff frequency The input coupling capacitor blocks the DC voltage at the amplifier input terminal. The input capacitors (c) 2016 www.awinic.com.cn 30 AW87319 datasheet Dec. 2016 V1.2 and input resistors form a high-pass filter with the corner frequency: fH ( 3dB) 1 (Hz) 2 Rintotal Cin Setting the high-pass filter point high can block the 217Hz GSM noise coupled to inputs. Better matching of the input capacitors improves performance of the circuit and also helps to suppress pop-click noise. Take typical application as an example, the input high-pass cutoff frequency is calculated as below: f H ( 3dB) 1 1 (Hz) (Hz) 376Hz 2 R intotal Cin 2 9k 47nF Supply Decoupling CapacitorCS The AW87319 is a high-performance audio amplifier that requires adequate power supply decoupling. Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F. This choice of capacitor and placement helps with higher frequency transients, spikes, or digital hash on the line. Additionally, placing this decoupling capacitor close to the AW87319 is important, as any parasitic resistance or inductance between the device and the capacitor causes efficiency loss. In addition to the 0.1F ceramic capacitor, place a 10F capacitor on the VBAT supply trace. This larger capacitor acts as a charge reservoir, providing energy faster than the board supply, thus helping to prevent any droop in the supply voltage. Output beads, capacitors, TVS The AW87319 passed FCC and CE radiated emissions with no ferrite chip beads and capacitors. Use ferrite chip beads and capacitors if device near the EMI sensitive circuits and/or there are long leads from amplifier to speaker, placed as close as possible to the output pin. In the class K mode, the output is a square wave signal, which causing switch current at the output capacitor, increasing static power consumption, and therefore output capacitor should not be too large, 0.1nF ceramic capacitors is recommended. bead VOP 0.1nF 12V bead VON 0.1nF 12V Figure 20 Ferrite Chip Bead and capacitor (c) 2016 www.awinic.com.cn 31 AW87319 datasheet Dec. 2016 V1.2 Amplifier output is a square wave signal. The voltage across the capacitor will be much larger than the PVDD voltage after increasing the bead capacitor. It suggested the use of rated voltage above 16V capacitor. At the same time a square wave signal at the output capacitor switching current form, the static power consumption increases, so the output capacitance should not be too much which is recommended 0.1nF ceramic capacitor rated voltage of 16V. If you want to get better EMI suppression performance, can use 1nF, rated voltage 16V capacitor, but quiescent current will increase. Power amplifier output PWM signals of high voltage to PVDD voltage, voltage to 8.5 V, will produce some ringing after bead capacitor, resulting in higher peak voltage. Recommended choose the operating voltage of 12V TVS. (c) 2016 www.awinic.com.cn 32 AW87319 datasheet Dec. 2016 V1.2 PCB AND DEVICE LAYOUT CONSIDERATION In order to obtain excellent performance of AW87319, PCB layout must be carefully considered. The design consideration should follow the following principles: 1. In AW87319 peripheral device layout, you first need to guarantee the Boost output capacitance close to PVDD pin. 2. Try to provide a separate short and thick power line to AW87319, the copper width is recommended to be larger than 0.75mm. The decoupling capacitors should be placed as close as possible to boost power supply pin. 3. The input capacitors and resistors should be close to AW87319 INN and INP input pin, the input line should be parallel to suppress noise coupling. 4. The beads and capacitor should be placed near to AW87319 VON and VOP pin. The output line from AW87319 to speaker should be as short and thick as possible. The width is recommended to be larger than 0.5mm. (c) 2016 www.awinic.com.cn 33 AW87319 datasheet Dec. 2016 V1.2 PACKAGE DESCRIPTION BOTTOM VIEW TOP VIEW 2. 00 2.760.025 0. 50 0.33 0.43 0.43 4 3 0. 50 1. 50 2.360.025 2 1 0.43 D E PIN A1 CORNER B C 0.05 A 19 X 0.270.02 CSP 19 19 - Ball Wafer Level Chip Scale Package SIDE VIEW LAND PATTERN 2.00 0.43 0.5 0.5 0.5 0.5 0.33 0.040.01 VDD SCL RSTN SDA INN PVDD VON INP PVDD PGND AD1 PVDD Unit: mm VOP 1.5 0.5 GND SEATING PLANE AD2 0.5 SW 0.1950.02 BGND SW 0.5950.055 BGND 0.43 0.360.025 0.5 0.43 O0.27 (c) 2016 www.awinic.com.cn 34 AW87319 datasheet Dec. 2016 V1.2 Tape Description Carrier Tape Pin1 . . . . . Reel (c) 2016 www.awinic.com.cn 35 AW87319 datasheet Dec. 2016 V1.2 Reflow Soldering curve (c) 2016 www.awinic.com.cn 36 AW87319 datasheet Dec. 2016 V1.2 VERSION INFORMATION Description Version Date V1.0 2015-11-30 AW87319CSR datasheet V1.0 V1.1 2016-11-10 Boost inductor Selection IL_PEAK cannot be less than 3.5A modified to not less than 3.6A (page 26) Tape description increase the position description of pin1 (page 34) Add Reflow soldering curve (page35) Product information added MSL instructions (page3) "the SDA transmits a high level in ninth clock pulse" modify to "the SDA transmits a low level in ninth clock pulse" (page18) The functional block diagram add feedback loop (page4) Add PVDD,SW,VON,VOP absolute maximum rating V1.2 2016-12-10 Add information about CDM Add Environmental Information (c) 2016 www.awinic.com.cn 37 AW87319 datasheet Dec. 2016 V1.2 AWINIC Technology cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AWINIC Technologies product. No intellectual property or circuit patent licenses are implied. AWINIC Technology reserves the right to change the circuitry and specifications without notice at any time. (c) 2016 www.awinic.com.cn 38