ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS8752I is a low voltage, low skew LVCMOS clock generator and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. With output frequencies up to 240MHz, the ICS8752I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS8752I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay". * Fully integrated PLL Dual clock inputs, CLK0 and CLK1, support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively. * External feedback for "zero delay" clock regeneration ICS * 8 LVCMOS outputs, 7 typical output impedance * Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications * Input/Output frequency range: 18.33MHz to 240MHz at VCC = 3.3V 5% * VCO range: 220MHz to 480MHz * Cycle-to-cycle jitter: 75ps (maximum), (all outputs are the same frequency) * Output skew: 100ps (maximum) For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state. * Bank skew: 55ps (maximum) * Full 3.3V or 2.5V supply voltage * -40C to 85C ambient operating temperature The low impedance LVCMOS outputs of the ICS8752I are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines. * Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT VDDO 00 01 10 11 QB2 /2 /4 /6 /8 /12 QB3 1 GND VCO GND CLK0 0 CLK1 1 PHASE DETECTOR nc VDD PLL FB_IN PLL_SEL PLL_SEL 32 31 30 29 28 27 26 25 QA0 DIV_SELB0 1 24 GND QA1 DIV_SELB1 2 23 QB1 DIV_SELA1 QA2 DIV_SELA0 3 22 QB0 DIV_SELA0 QA3 DIV_SELA1 4 21 VDDO MR/nOE 5 20 VDDO CLK0 6 19 QA3 GND 7 18 QA2 FB_IN 8 17 GND CLK_SEL 0 00 01 10 11 QB0 QB1 DIV_SELB1 QB2 DIV_SELB0 QB3 ICS8752I 9 10 11 12 13 14 15 16 VDDO QA1 QA0 GND CLK1 VDD MR/nOE 8752CYI VDDA CLK_SEL 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View www.icst.com/products/hiperclocks.html 1 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 4 Name DIV_SELB0, DIV_SELB1 DIV_SELA0, DIV_SELA1 Type Input Input 5 MR/nOE Input Description Determines output divider values for Bank B as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. When logic HIGH, the internal dividers are reset and the outputs are Pulldown disabled. When logic LOW, the master reset is disabled and the outputs are enabled. LVCMOS / LVTTL interface levels. 6 CLK0 Input 7, 13, 17, 24, 28, 29 Pulldown Clock input. LVCMOS / LVTTL interface levels. GND Power 8 FB_IN Input 9 CLK_SEL Input 10 VDDA Power Analog supply pin. 1 1, 32 VDD Power Core supply pins. Power supply ground. Feedback input to phase detector for generating clocks with "zero delay". LVCMOS / LVTTL interface levels. Clock select input. Selects between CLK0 or CLK1 as phase detector Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Pulldown 12 CLK1 Input 14, 15, 18, 19 16, 20, 21, 25 22, 23, 26, 27 QA0, QA1, QA2, QA3 Pulldown Clock input. LVCMOS / LVTTL interface levels. Output Bank A clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. VDDO Power Output supply pins. QB0, QB1, QB2, QB3 Output Bank B clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. 30 nc Unused No connect. 31 PLL_SEL Input Pullup Selects between the PLL and CLK0 or CLK1 as the input to the dividers. When HIGH selects PLL. When LOW selects CLK0 or CLK1. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 k 23 pF 7 CPD ROUT 8752CYI Test Conditions Minimum VDDA, VDD, VDDO = 3.465V www.icst.com/products/hiperclocks.html 2 Typical Maximum REV. B Units MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 3. CONTROL INPUT FUNCTION TABLE MR/nOE PLL_SEL Inputs DIV_ SELA1 X CLK_SEL Outputs DIV_ SELA0 X DIV_ SELB1 X DIV_ SELB0 X QAx QBx 1 X X Hi-Z Hi-Z 0 1 X 0 0 0 0 fVCO/2 fVCO/4 0 1 X 0 1 0 1 fVCO/4 fVCO/6 0 1 X 1 0 1 0 fVCO/6 fVCO/8 0 1 X 1 1 1 1 fVCO/8 fVCO/12 0 0 0 0 0 0 0 fCLK0/2 fCLK0/4 0 0 0 0 1 0 1 fCLK0/4 fCLK0/6 0 0 0 1 0 1 0 fCLK0/6 fCLK0/8 0 0 0 1 1 1 1 fCLK0/8 fCLK0/12 0 0 1 0 0 0 0 fCLK1/2 fCLK1/4 0 0 1 0 1 0 1 fCLK1/4 fCLK1/6 0 0 1 1 0 1 0 fCLK1/6 fCLK1/8 0 0 1 1 1 1 1 fCLK1/8 fCLK1/12 NOTE: For normal operation, MR/nOE is LOW. When MR/nOE is HIGH, all ouputs are disabled. TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB Inputs FB_IN QB QB QB QB DIV_ DIV_ SELB1 SELB0 0 0 1 1 0 1 0 1 QB Output Divider Mode (NOTE 2) /4 /6 /8 /12 Outputs CLK0, CLK1 (MHz) (NOTE 1) Minimum Maximum 55 36.66 27.5 18.33 120 80 60 40 DIV_ SELA1 DIV_ SELA0 QA Output Divider Mode QA Multiplier (NOTE 2) 0 0 /2 2 0 1 /4 1 1 0 /6 0.667 1 1 /8 0.5 0 0 /2 3 0 1 /4 1.5 1 0 /6 1 1 1 /8 0.75 0 0 /2 4 0 1 /4 2 1 0 /6 1.33 1 1 /8 1 0 1 /2 6 0 1 /4 3 1 0 /6 2 1 1 /8 1.5 NOTE 1: VCO frequency range is 220MHz to 480MHz. NOTE 2: QA output frequency equal to CLKx frequency times the multiplier ; QB output frequency equal to CLKx. 8752CYI www.icst.com/products/hiperclocks.html 3 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA FB_IN QA QA QA DIV_ SELA1 0 0 1 DIV_ SELA0 0 1 0 QA Output Divider Mode (NOTE 2) /2 /4 /6 Inputs CLK0, CLK1 (MHz) (NOTE 1) Minimum Maximum 110 55 36.66 240 (NOTE 3) 120 80 Outputs DIV_ SELB1 DIV_ SELB0 QB Output Divider Mode QB Multiplier (NOTE 2) 0 0 /4 0.5 0 1 /6 0.333 1 0 /8 0.25 1 1 /12 0.167 0 0 /4 1 0 1 /6 0.667 1 0 /8 0.5 1 1 /12 0.333 0 0 /4 1.5 0 1 /6 1 1 0 /8 0.75 1 1 /12 0.5 0 1 /4 2 0 1 /6 1.333 1 0 /8 1 1 NOTE 1: VCO frequency range is 220MHz to 480MHz. NOTE 2: QB output frequency equal to CLKx frequency times the multiplier ; QA output frequency equal to CLKx. NOTE 3: Maximum frequency of 240MHz valid for VCC = 3.3V 5% only. 1 /12 0.667 QA 8752CYI 1 1 /8 27.5 60 www.icst.com/products/hiperclocks.html 4 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Supply Voltage 3.465 V IDD Power Supply Current 105 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 20 mA Maximum Units TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 20 mA 8752CYI www.icst.com/products/hiperclocks.html 5 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH DIV_ SELx0, DIV_SELx1, CLK0, CLK1, FB_IN, CLK_SEL, Input High Current MR/nOE IIL VOH Maximum Units VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 150 A 5 A or 2.625V VDD = VIN = 3.465V or 2.625V DIV_ SELx0, DIV_SELx1, CLK0, CLK1, FB_IN, CLK_SEL, MR/nOE PLL_SEL Typical VDD = VIN = 3.465V PLL_SEL Input Low Current Minimum VDD = 3.465V or 2.625V, -5 A VDD = 3.465V or 2.625V, VIN = 0V -150 A VDDO = VIN = 3.465V 2.6 V VDDO = VIN = 2.625V 1.8 V VIN = 0V Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, "Output Load Test Circuit" diagrams. 0.5 V Maximum Units 240 MHz Maximum Units 120 MHz TABLE 6A. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Input Reference Frequency NOTE: Input reference frequency is limited by fREF the divider selection and the VCO lock range. Test Conditions Minimum Typical 20 TABLE 6B. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter Input Reference Frequency NOTE: Input reference frequency is limited by fREF the divider selection and the VCO lock range. 8752CYI Test Conditions Minimum 20 www.icst.com/products/hiperclocks.html 6 Typical REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol fOUT fVCO Parameter Test Conditions Minimum Maximum Units /2 110 240 MHz /4 55 120 MHz /6 36.67 80 MHz /8 27.5 60 MHz /12 18.33 40 MHz 220 480 MHz 170 ps 55 ps 100 ps 400 ps 75 ps Output Frequency (PLL Mode) PLL VCO Lock Range t(O) Static Phase Offset; NOTE 1 tsk(b) Bank Skew; NOTE 2, 4 tsk(o) Output Skew; NOTE 3, 4 tjit(cc) Cycle-to-Cycle Jitter ; NOTE 4 fVCO = 400MHz, Feedback / 8 Measured on rising edge at VDDO/2 -30 Measured on rising edge at VDDO/2 Different Frequencies on Different Banks All Outputs at Same Frequency tL PLL Lock Time tR / tF Output Rise/Fall Time Typical 70 1 mS 950 ps odc Output Duty Cycle 47 50 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % 8752CYI 20% to 80% www.icst.com/products/hiperclocks.html 7 400 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol fOUT Parameter Test Conditions Minimum /2 Output Frequency (PLL Mode) Typical Maximum Units 110 240 MHz /4 55 120 MHz /6 36.67 80 MHz /8 27.5 60 MHz /12 18.33 40 MHz 220 480 MHz 190 ps 55 ps 90 ps 400 ps 75 ps 1 mS 950 ps odc Output Duty Cycle 45 50 55 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % fVCO PLL VCO Lock Range t(O) Static Phase Offset; NOTE 1 tsk(b) Bank Skew; NOTE 2, 4 tsk(o) Output Skew; NOTE 3, 4 tjit(cc) Cycle-to-Cycle Jitter ; NOTE 4 -90 Different Frequencies on Different Banks All Outputs at Same Frequency tL PLL Lock Time tR / tF Output Rise/Fall Time 8752CYI fVCO = 400MHz Feedback / 8 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 20% to 80% www.icst.com/products/hiperclocks.html 8 400 50 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 1.25V5% 1.65V5% SCOPE VDD, VDDA,VDDO Qx LVCMOS SCOPE VDD, VDDA,V DDO Qx LVCMOS GND GND -1.65V5% -1.25V5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT (Where X denotes outputs in the same Bank) VDDO 2 V DDO Qx QX0:QX3 2 VDDO 2 V DDO QX0:QX3 2 t sk(o) Qy t sk(b) OUTPUT SKEW BANK SKEW DDO 2 DDO 2 tcycle 2 CLK0, CLK1 2 tcycle n+1 n VDD V V DDO VDD 2 FB_IN t jit(cc) = tcycle n -tcycle n+1 t (O) V QA0:QA3, QB0:QB3 1000 Cycles STATIC PHASE OFFSET CYCLE-TO-CYCLE JITTER V DDO QA0:QA3, QB0:QB3 80% 2 Pulse Width t odc = Clock Outputs PERIOD 80% 20% 20% tR tF t PW t PERIOD OUTPUT DUTY CYLCLE/PULSE WIDTH/PERIOD 8752CYI OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 9 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W 200 500 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8752I is: 1546 Functionally compatible with MPC952 in some applications 8752CYI www.icst.com/products/hiperclocks.html 10 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e 0.60 0.75 L 0.45 0 -- 7 ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8752CYI www.icst.com/products/hiperclocks.html 11 REV. B MAY 2, 2005 ICS8752I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8752CYI ICS8752CYI 32 Lead LQFP tray -40C to 85C ICS8752CYIT ICS8752CYI 32 Lead LQFP 1000 tape & reel -40C to 85C ICS8752CYILF TBD 32 Lead "Lead-Free" LQFP tray -40C to 85C ICS8752CYILFT TBD 32 Lead "Lead-Free" LQFP 1000 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial or industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8752CYI www.icst.com/products/hiperclocks.html 12 REV. B MAY 2, 2005 Integrated Circuit Systems, Inc. ICS8752I LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER REVISION HISTORY SHEET Rev Table 7A & 7B Page 6&8 7B 1 8 2 1 2 2 12 A A B 8752CYI T1 T2 T9 Description of Change AC Characterisitics tables, Static Phase Offset/Test Conditions changed Feedback / 4 to Feedback / 8. Date 6/17/02 Bank Skew should read 55ps Max. from 40ps Max. Pin Description Table - revised MR/nOE description. Features Section - added Lead-Free Bullet Pin Description Table - correct Pin 5, MR/nOE. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Added Lead-Free par t number. Updated datasheet format. www.icst.com/products/hiperclocks.html 13 8/19/02 5/2/05 REV. B MAY 2, 2005